Project report final year

A Report on

“HIGH SPEED MIXED MODE CMOS ADDER CIRCUIT”

Submitted for partial fulfillment of award of

BACHELOR OF TECHNOLOGY

Degree

In

ELECTRONICS AND COMMUNICATION ENGINEERING

Submitted by

Hemraj chonker (1206431042)

Kapileshwar (1206431047)

Ketan upadhyay (1206431048)

Kishan gupta (1206431051)

Guided by:

Ms. Anushree gupta

HINDUSTAN COLLEGE OF SCIENCE AND TECHNOLOGY, FARAH

MATHURA

UTTAR PRADESH TECHNICAL UNIVERSITY, LUCKHNOW

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CERTIFICATE

This is to certify that project report entitled “HIGH SPEED MIXED MODE ADDER CIRCUIT” which is submitted by HEMRAJ CHONKER, KAPILESHWAR, KETAN UPADHYAY, KISHAN GUPTA in partial fulfillment of the requirement for the award of degree B.Tech in department of ELECTRONICS AND COMMUNICATION of U.P. Technical university, is a record of the candidate own work carried out by him under my/our supervision. The matter embodied in this thesis is original and has not been submitted for the award of any other degree.

Ms. Anushree gupta Mrs. Deepti gupta Prof. Sanjay jain

(Project guide) (Project Co-ordinator) (H.O.D ECE dept.)

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DECLARATION

We hereby declare that this submission is our own work and that, to the best of our knowledge and belief, it contains no material previously published or written by another person nor material which to a substantial extent has been accepted for the award of any other degree or diploma of the university or other institute of higher learning, except where due acknowledgment has been made in the text.

Hemraj chonker (1206431042)

Kapileshwar (1206431047)

Ketan upadhyay (1206431048)

Kishan gupta (1206431051)

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ACKNOWLEDGEMENT

It gives us a great sense of pleasure to present the report of the B.Tech project undertaken during B.Tech final year. We owe special debt of graduate to MS. Anushree,Assistant professor, Department of Electronics and Communication, Hindustan college of science and technology for his constant support and guidance throughout the course of our work. Her sincerity, thoroughness and perseverance have been a constant source of inspiration for us. It is only her cognizant efforts that our endeavors have seen light of the day.

We also take the opportunity to acknowledge the contribution of Prof. Sanjay jain, head, Department of electronics & communication, Hindustan College of Science & Technology for his full support and assistance during the development of the project.

We also do not like to miss the opportunity to acknowledge the contribution of all faculty members of the department for their kind assistance and cooperation during the development of our project. Last but not the least, we acknowledge our friends for their contribution in the completion of the project.

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TABLE OF CONTENTS

NOMENCLATURE PAGE

CERTIFICATE 2

DECLARATION 3

ACKNOWLEDGEMENT 4

CHAPTER 1 (PROJECT OVERVIEW)

1.1 INTRODUCTION 101.2 MOTIVATION AND BACKGROUND 111.3 OBJECTIVE OF PROJECT 111.4 SCOPE OF PROJECT 111.5 METHODOLOGY 111.6 DESIGN PROCEDURE 121.7 COMPARISION WITH PREVIOUS FULL

ADDER DESIGN 15

1.8 TOOL USED 16

CHAPTER 2 (BASICS OF FULL ADDER)

2.1 FULL ADDER 18

2.1.1 BASICS OF FULL ADDER 18

2.2 REVIEW OF FULL ADDER TOPOLOGIES 20

2.2.1 LOGIC DEPTH 20

2.2.2 LOGIC FAMILY SELECTION 20

2.2.3 PREFIX SELECTION 20

2.2.4 LOAD BUFFERING 20

CHAPTER 3 (DIFFERENT FUNCTION OF MIXED MODE FULL

ADDER)

3.1 CMOS BRIDGE CIRCUIT 23

3.2 MAJORITY FUNCTION 24

3.3 MAJORITY NOT FUNCTION 24

3.4 MAJORITY FUNCTION BASED CURRENT MODE

LOGIC 25

CHAPTER 4 MIX MODE FULL ADDER DESIGN

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4.1 MIX MODE ADDER CIRCUIT 28

4.2 CREATING ADDER CIRCUIT SCHEMATIC 28

CHAPTER 5 (RESULT AND ANALYSIS)

5.1 MIXED MODE FULL ADDER 35

5.1.1 VOLTAGE MODE CIRCUIT 35

5.1.2 CURRENT MODE CIRCUIT 36

5.2 CARRYBAR & SUM OUTPUT WAVEFORM 38

5.3 CONCLUSION 43

REFERENCES 45

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LIST OF FIGURES

FIGURE NO. TITLE PAGE NO.

FIGURE 1.1 KCL RULE 12

FIGURE 1.2 TRUTH TABLE OF MAJORITY FUNCTION 12

FIGURE 1.3 LOGIC GATE FOR MAJORITY FUNCTION 13

FIGURE 1.4 FULL ADDER ON MAJORITY NOT FUNCTION 13

FIGURE 1.5 CURRENT MODE LOGIC 14

FIGURE 2.1 FULL ADDER CIRCUIT 18

FIGURE 2.2 K MAP OF FULL ADDER FOR CARRY 19

FIGURE 2.3 K MAP OF FULL ADDER FOR SUM 19

FIGURE 3.1 CARRY GENERATOR CIRCUIT 23

FIGURE 3.2 IMPLEMENTATION OF MAJORITY NOT

FUNCTION 24

FIGURE 3.3 MAJORITY NOT GATE 25

FIGURE 3.4 LOGIC CIRCUIT IN CURRENT MODE MAJORITY

FUNCTION 26

FIGURE 4.0 SCHEMATIC OF FULL ADDER CIRCUIT 28

FIGURE 4.1 LTspice IV SOFTWARE 28

FIGURE 4.2 SELECT NEW SCHEMATIC 29

FIGURE 4.3 SELECT COMPONENT SYMBOL 29

FIGURE 4.4 SELECT NMOS SYMBOL 30

FIGURE 4.5 PLACE NMOS SYMBOL 30

FIGURE 4.6 SELECT PMOS SYMBOL 31

FIGURE 4.7 PLACE PMOS SYMBOL 32

FIGURE 4.8 SELECT VOLTAGE COMPONENT 32

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FIGURE 4.10 SELECT DRAW WIRE 33

FIGURE 4.11 WIRE ALL COMPONENTS 33

FIGURE 5.1 VOLTAGE MODE CIRCUIT 35

FIGURE 5.2 CURRENT MODE CIRCUIT 36

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CHAPTER 1

PROJECT OVERVIEW

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1.1 INTRODUCTION

The current mode circuits have now developed into a solid competitor for the voltage mode circuits. Free algebraic summation, simplicity of the design and accessible approach to the desired speed by adjusting the current and several other ascendancies, have induced the current circuits to acquire a particular position in the logic styles. Notwithstanding all these advantages, the structured gates in the current mode possess some weak points which are originated from essence of voltage element. For instance, high noise acceptability of current mode gates, have always been an obstacle in the technique of operative circuits.

Instead, voltage mode gates, in contrary of the current mode gates, were used for many years. These gates are much older than their newer counterparts, so called as current mode circuits and the deficiencies in them have over time been improved. High resistance against noise, simplicity of the design, considerable logic production, uncomplicated production of the inputs and some other positive features confirm partial dominance of built logic in this mode, over the current mode circuits.Thus, if there is a gate which possesses both modes of voltage and current outputs, it can enjoy the benefits of both designs.

Addition is one of the fundamental arithmetic operations. It is used extensively in many VLSI systems such as microprocessors and application specific DSP architectures. In addition to its main task, which is adding two numbers, it is the nucleus of many other useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systems the adder lies in the critical path that determines the overall speed of the system. That is why enhancing the performance of the 1-bit full adder cell (the building block of the adder) has been of a continuous interest. Since the available sources had been of voltage type previously, the internal circuits of preliminary gates were traditionally built according to inputs and outputs of voltage. All the famous logic families have been designed in this mode.

There are two types of full adders in case of logic structure. One is static style and the other is dynamic style. Static full adders are commonly more reliable, simpler and of lower power than dynamic ones. Dynamic is an alternative logic style to design a logic function. It has some advantages in comparison with static mode such as faster switching speeds, no static power consumption, non-ratioed logic, full swing voltage levels and less number of transistors. For an N input logic function, it requires N+2 transistors versus 2N transistors in the standard CMOS logic.

The area advantage comes from the fact that the pMOS network of a dynamic CMOS gate consists of only one transistor. This also results in a reduction in the capacitive load at the output node, which is the basis for the high-speed advantage. Dynamic CMOS logic style provides high performance because this logic style is constructed with only high mobility nMOS transistors. Also, due to the absence of the pMOS transistors, the input capacitance is lower. Dynamic full adders suffer from charge sharing, high power due to high switching activity, clock load and complexity. However, dynamic full adders are faster and some times more compact than static full adders. Many researchers have combined these two structures and have proposed hybrid dynamic-static full adders.

As mentioned before, several logic styles have been used in the past to design full adder cells. In addition we review previous dynamic full adders. Then we present the new mixed mode current and dynamic full adder. The circuit simulation for delay performance and the results are analyzed and compared in section Results and Discussion.

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1.2 MOTIVATION & BACKGROUND

The development of very compact and high speed adders are of great importance for the reduction in size of high end devices like computer, laptop, phone etc. these adders are of great importance for the improvement and speed of the future devices. Adders represented in this report are compact in size and they have very less propagation delay. These adders require very less area over the chip which allows us to fabricate more number of adders on the smaller chip area.

The static Majority function (bridge) design style enjoys a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as lower power consumption by using bridge transistors. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of mixed mode logic designs. 1.3 OBJECTIVE OF PROJECT

The objective of this work is to present a new full adder design circuits combined with current mode circuit in one unit to implement a full adder cell. To enhance the performance of full adder by reducing the propagation delay, area on chip & reducing the complexity of circuit.

1.4 SCOPE OF PROJECT

Low-power design of VLSI circuits has been identified as a critical technological need in recent years due to high demand for portable consumer electronics products. With the explosive growth in laptops, portable personal communication systems and the evolution of the shrinking technology, the research effort in low-power microelectronics has been intensified and low-power VLSI systems have emerged high in demand. Adder is one of the most important components of a CPU (central processing unit), Arithmetic logic unit (ALU), floating-point unit and address generation unit like cache or memory access unit.

The proposed design helps in reducing the number of components, size and complexity of the circuit.Full adders are important components in applications such as Digital signal processing (DSP) architectures and microprocessors. Arithmetic functions such as addition, subtraction, multiplication and division these are the applications most required for calculator and CPU.

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1.5 METHODOLOGY

The basic idea to generate Sum from Carry bar by using 5 inputs majority-not function with threeinput signals (A,B,C ) and with two Carry bar input signals are :

carry=Maj(A , B ,C ) ……… (eq.1 )

∑ ¿Maj (A ,B ,C , carry , carry) ……….(eq. 2)

The designed circuits in current mode use the natural traits of current for logic circuits. For example, according to the KCL rule, the sum of input currents to one point is always equal to sum of the output currents from that point. In this discipline, Fig. 1 could be a three input adder in current mode

Fig.1.1

As it can be observed in Fig. 1, with a short circuit of three lines as the input lines and one line as output we built a 3-bit adder. With the same pattern, if we want to have an n-bit adder in a current mode, we must consider a short circuit of n+1 line and then one line as an output and the other n lines as the input lines. In this mode, with use of the natural traits of current, we could implement different aspects of logic gates in an interesting fashion.

Consider Fig. 2. In the Circuit illustrated in Fig. 2, both inputs and outputs are of current in gender.M1 transistor converts quantities of the input currents into voltage and provides it to an inverter. Thethreshold voltage of the inverter is pointed out with TD and provided to the designer.

Fig.1.2

M2 transistor is switched on and off under the control of the inverter, thus connects and disconnectsthe output current. Despite of the constant shape of this circuit, it can implement the functions of AND, OR, Majority Function, Minority Function and many other functions. In the circuit illustrated in Fig. 2, the only variant is the quantity of TD. If different quantities of TD are specified, the produced functions in the output of this circuit are also changed.

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The majority function is a logic circuit that performs a majority vote to determine the output of the circuit. In this part, we describe how the circuit of the full adder based on majority function could be designed.

The full adder can be operated as follows: given the three input A, B and Cin, it is desired to calculate two 1-bit outputs SUM and Cout. Fig. 3 illustrates (a) the truth table and (b) the logic equations of full adder cell.

Fig 1.3 a. truth table b. logic eqations of full adder

As previous equations show, Cout can be implemented with three inputs Majority function as shown in Fig. 4(a) and if we invert the output of the circuit, out C is produced with Majority Not function circuit as shown in Fig. 4(b).

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Fig 1.4 logic gates for (a) majority function (b)majority not function

The new notation that has been implemented in pattern of this circuit in Current Mode to produce SUM has been illustrated in Fig. 5

Fig 1.5 full adder based on majority function & majority not function

Initially, Cout is produced according to the Majority Not Function and then Cout with two option and three input of A,B and C witheach one option is presented to a Majority Function to produce Sum.In this pattern of majority not function in voltage mode (Dynamic) is the matching part of majority function in current mode.

TABLE 1.1 TRUTH TABLE OF Cout, SUM & MAJORITY FFUNCTION

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With regard to the designed circuit and the truth table, out C enters into the M9 transistor gate and to provide it with tow option, since we are in the Current Mode, the current which is pulled from the M9 Transistor must be twice as much as the current from M10-12.so:

Fig 1.6

1.6 DESING PROCEDURE STEP 1- firstly design the mixed mode full adder on ltspice.

STEP 2- after designing we simulate the circuit for getting the sum & carry bar waveforms.

1.7 COMPARISON WITH PREVIOUS FULL ADDER DESIGNS

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TABLE 1.2

DESIGN TYPES COMPONENTS USED

HYFA1 16T 4C

HYFA2 16T 3C

HYFA3 15T 3C

HYFA4 16T 4C

HYFA5 12T 4C

MIXFA1 16T

MIXFA2 19T

Where T=Transistors & C=Capacitors

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1.8 SOFTWARE USED

Design & analysis in this project is done on LTspice IV. LTspice IV provides a schematic capture and waveform viewer with enhancements and models to speed the simulation of switching regulators. Supplied with LTspice IV are macro models for 80% of LTC's switching regulators and operational amplifiers, transistors,MOSFETs, and passive components.

LTspice IV is node-unlimited and third-party models can be imported. Circuit simulations based on transient, AC, noise and DC analysis can be plotted as well as Fourier analysis. Heat dissipation of components can be calculated and efficiency reports can also be generated.

LTspice IV is used within LTC, and by many users in fields including radio frequency electronics, power electronics, digital electronics, and other disciplines. LTspice IV does not generate printed circuit board (PCB) layouts, but netlists can be imported into layout programs. LTSpice IV can't simulate a complex digital logic. LTspice was originally called SwitcherCAD and is sometimes still called by that name.

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CHAPTER 2

BASICS OF FULL ADDER

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2.1 FULL ADDER :

Full Adder is a combinational circuit that performs addition of three bits. It consists of three inputs and two ouputs. Two of the inputs denoted by A and B are augend and addend bits that are to be added, & third input denoted by Ci represents the carry bit from the previous lower significant position. The two O/Ps are the sum ‘S’ of A and B and the carry bit, denoted by C.

2.1.1 BASICS OF FULL ADDER :

The full-adder circuit adds three one-bit binary numbers (C A B) and outputs two one-bit binary numbers, a sum (S) and a carry (C1). The full-adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. binary numbers. The carry input for the full-adder circuit is from the carry output from the circuit "above" itself in the cascade. The carry output from the full adder is fed to another full adder "below" itself in the cascade. If you look closely, you'll see the full adder is simply two half adders joined by an OR.

Figure 2.1 Full-adder circuit.

This type of adder is a little more difficult to implement than a half-adder. The main difference between a half-adder and a full-adder is that the full-adder has three inputs and two outputs. The first two inputs are A and B and the third input is an input carry designated as CIN. When a full adder logic is designed we will be able to string eight of them together to create a byte-wide adder and cascade the carry bit from one adder to the next.

TABLE 2 TRUTH TABLE OF FULL ADDER :

Symbolic addition of a column of three bits , and truth table specifying the results for each possible

combination of inputs. From the above truth-table, the full adder logic can be implemented.

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We can see that the output S is an EXOR between the input A and the half-adder SUM output with B and CIN inputs. We must also note that the COUT will only be true if any of the two inputs out of the three are HIGH.

K MAP OF FULL ADDER FOR CARRY :

Fig 2.2

K MAP OF FULL ADDER FOR SUM :

Fig 2.3

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2.2 REVIEW OF FULL ADDER TOPOLOGIES :

2.2.1 Logic Depth (LD):

The maximum number of logic stages from output to inputs. Each logic gate is counted as a stage for fully static implementation. However, in compound designs, the dynamic gate and the following static gate are counted as one stage. The number of stages depends on the prefix of design. Minimum depth adders are used when high performance is required.

2.2.2 Logic Family Selection:

In VLSI design, the selection of logic family is dictated by the system performance target. In structures where the performance target is relaxed or where energy is the primary constraint, static circuits are preferred due to their lower switching activity. In addition to that, static circuits are robust and have become more preferable as technology scales down. However, in high-performance microprocessors, dynamic circuits are often required in order to achieve desired target frequency. There are two types of dynamic circuit families used in modern digital systems: (a) dynamic CMOS domino and (b) CMOS compound domino. The main difference between these families is that CMOS domino utilizes a static inverter at the output, while CMOS compound domino uses a static inverting logic stage. This helps in reducing the power by eliminating power hungry dynamic stages and bundling their functionality in the static CMOS inverting stage. As a summary, static circuits are good for power and domino circuits are good for speed. Compound domino designs can combine the speed advantage of dynamic designs and the power advantage of static designs.

Prefix (p):

The number of bits combined at each logic stage as defined above. For example, the two-input dynamic gate and the following two-input static gate is defined as prefix-2 stages for domino designs. The two-input dynamic gate and the following two-input static gate is defined as a prefix-4 stage for compound domino designs. Prefix adders are consisting of two blocks, namely, Sum and Carry blocks. A basic cell in digital computing systems is 1-bit full adder which has 1-bit inputs (A, B, C) and two 1-bit outputs (Sum and Carry).

2.2.3 Prefix Selection:

In static CMOS logic, the prefix is mostly limited to 2 because of transistor stack height limitation while dynamic designs enable to use of higher prefixes. As prefix of the design increases the logic depth decreases and it is expected to lead to delay improvement. However, higher prefix requires more complex gates with increased stack height resulting in higher gate delay. Therefore, there is an optimal prefix that depends on the design constraints and implementation.

2.2.4 Load Buffering:

Addition of inverters is used to drive the output load because inverters are the most energy-efficient drivers. Extra delays come from the parasitic and effort delay of the added inverters. However, the delay of the original circuit will be reduced since it drives added inverters that are smaller than the output load. In addition, extra energy is consumed by added inverters but the original circuit’s size is reduced. There is a tradeoff between the saved delay/energy and extra delay/energy coming from the added inverters. Load buffering provides energy savings for heavily loaded designs under the same delay constraints. As the load is reduced, the energy saving of the adder circuit cannot compensate for

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the extra energy consumed by the extra inverters. The energy saving of load buffering depends on the driving strength of the original circuit and the path gain.

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CHAPTER 3

DIFFERENT FUNCTION

OF

MIXED MODE FULL ADEER

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3.1 CMOS BRIDGE CIRCUIT

Bridge circuits provide a conditional conjunction between two circuit nodes. Since one of the important parameters in circuit design is the chip area, the bridge style might reduce area or increase density of transistors in unit of area. Circuits can be implemented faster and smaller than the conventional as shown in Figure 3.1. Bridge transistors make it possible to create a new path from supply lines to an output through sharing transistors of different paths. These transistors are arranged in such a way that validates the correctness of the circuit, and also preserves pull-up and pull-down networks mutually exclusive.

Figure 3.1 carry generator circuits (Three input majority not function)

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3.2 MAJORITY FUNCTION

In Boolean logic, the majority function (also called the median operator) is a function from n inputs to one output. The value of the operation is false when n/2 or more arguments are false, and true otherwise. Alternatively, representing true values as 1 and false values as 0, we may use the formula

The “−1/2” in the formula serves to break ties in favor of zeros when n is even. If the term “−1/2” is omitted, the formula can be used for a function that breaks ties in favor of ones.

A majority gate is a logical gate used in circuit complexity and other applications of Boolean circuits. A majority gate returns true if and only if more than 50% of its inputs are true.

For instance, in a full adder the carry output is found by applying a majority function to the three inputs, although frequently this part of the adder is broken down into several simpler logical gates.

Many systems have triple modular redundancy they use the majority function for majority logic decoding. To implement error correction.

A major result in circuit complexity asserts that the majority function cannot be computed by AC0 circuits of subexponential size.

The majority function produces “1” when more than half of the inputs are 1; it produces “0” when more than half the inputs are 0. Most applications deliberately force an odd number of inputs so they don’t have to deal with the question of what happens when exactly half the inputs are 0 and exactly half the inputs are 1. The few systems that calculate the majority function on an even number of inputs are often biased towards “0”—they produce “0” when exactly half the inputs are 0 – for example, a 4-input majority gate has a 0 output only when two or more 0’s appear at its inputs.In a few systems, a 4-input majority network randomly chooses “1” or “0” when exactly two 0’s appear at its inputs.

3.3 MAJORITY NOT FUNCTION

The majority structure is implemented by three input capacitors. These three input capacitors prepare an input voltage that is applied for driving static CMOS inverter. For implementation, the majority not function circuit as shown in Figure 3.2, high threshold voltage (Vth) transistors have been used.

Figure 3.2 implementation of majority NOT function

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The majority gates may be designed with more inputs by this method by increasing the number of input capacitors. The capacitor network is used to provide voltage division for implementing majority logic. When the majority of inputs are ‘0’, the output of capacitor network is considered as logic ‘0’ by the CMOS inverter and consequently the output of inverter is VDD. When the majority of inputs are logic ‘1’, the output of capacitor network is considered logic ‘1’ by the CMOS inverter and consequently the output of inverter is 0V. The input capacitance of the CMOS inverter is negligible and has no effect on operation of the circuit.

Figure 3.3 majority NOT Gate

Majority Not function is a logic gate with odd numbers of inputs, and its output is high when the numbers of logic ‘1’s is less then the number of ‘logic 0’s in the input of the logic gate. The Majority not function is implemented efficiently by using only capacitors and a static CMOS inverter. Figure 3.3 shows a circuit used to implement majority-not function with inverter utilizing high-Vth for both Nmos and Pmos. This circuit can be used to implement NAND gate using high-Vth Nmos and low-Vth Pmos, and NOR gate using low-Vth Nmos and high-Vth.

3.4 MAJORITY FUNCTION BASED CURRENT MODE LOGIC

Current Mode Logic (CML) has some advantages over voltage mode MVL. Implementing voltage-mode multiple-valued logic (MVL) requires partitioning the total voltage range, zero to supply voltage in to many discrete levels. Thus, the dynamic range and the noise margin are highly dependent on the supply voltage. In current-mode circuits, currents are usually defined to have logical levels that are integer multiple of a reference current unit. Current can be copied, scaled and algebraically sign-changed with a simple current mirror circuit. The main advantage of current mode comparing to the voltage mode is that the summation in current mode requires no extra elements. Another feature in current mode is that the direction of current can be used to show the sign and as a result the additional bit for representing the sign in numeric system, can be eliminated.

The main feature in current mode circuits is that we can design various logic circuits using threshold detector by changing threshold value and sometimes by increasing or decreasing the number of inputs. The designing of threshold value is possible by changing only the threshold detector transistors dimensions. As can be observed, the uniform structure of current mode circuits, easily allows the designer to increase the number of inputs, while in the voltage mode, this is only possible with increasing the number of transistors. The implementation of majority function in current mode with given equation I1I2+I1I3+I2I3, is shown in Figure 3.4. If the sum of the inputs is greater than logic 1.5 (threshold value) then the output current will be equal to reference current else, there is no current at the output.

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(a) Current mode with a source output (b) current mode with a sink outputFigure 3.4 Logic Circuit in Current Mode Majority Function

The threshold function is simply implemented by CMOS inverter. In the circuit illustrated in Figure 3.4(a), both inputs and outputs are of current in gender. M1 transistor converts quantities of the input currents into voltage and provide it to an inverter. The threshold voltage of the inverter is pointed out with TD and provided to the designer. M2 transistor is switched on and off under the control of the inverter, thus connects and disconnects the output current. Despite of the constant shape of this circuit, it can implement the functions of AND, OR, Majority Function, Majority Not Function and many other functions. If different quantities of TD are specified, the produced functions in the output of this circuit are also changed. As an instance, with a threshold detector from 0.5 OR gate, with the threshold detector from 2.5 AND gate and also with TD from 2 majority function shall be obtained. The circuit in Figure 3.4(b) is same as the circuit of Figure 3.4(a) with a difference that in the output which is sinking instead of source.

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CHAPTER 4

MIX MODE FULL ADDER DESIGN

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4.1 MIXED MODE ADDER CIRCUIT

Mixed-mode simulation applies more than one algorithm to the circuit. The circuit is partitioned into parts to which each algorithm is applied. It often does not mean mixed analog and digital, but perhaps two different levels of digital simulation, such as logic (discrete states) and timing (some sense of voltage).

The adder we have designed operates on both the current mode logic(CML) and the voltage mode logic(VML) simultaneously. The output sum function is based on current mode majority function while the rest of the circuit operates on voltage mode. In mixed mode designing the majority not function in voltage mode is the matching part of majority function in current mode. In the current mode, the current which is pulled from the Carry transistor must be twice as much as the current from input transistors to satisfy the following:

carry=Maj(A , B ,C ) ……… (eq. 1)

∑ ¿Maj (A ,B ,C , carry , carry) ……….(eq. 2)

Fig 4.0 schematic of full adder

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4.2 CREATING ADDER CIRCUIT SCHEMATIC

STEP 1 : open LTspice IV Software

Figure 4.1 LTspice IV software

STEP 2 : Choose new schematic from file menu

Figure 4.2 Select new schematic

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STEP 3 : Then select component

Figure 4.3 select component symbol

STEP 4 : Search for NMOS in the component symbol list

Figure 4.4 select NMOS symbol

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STEP 5 : Place NMOS symbols

Figure 4.5 place NMOS symbols

STEP 6 : select PMOS symbol from components

Figure 4.6 select PMOS symbol

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STEP 7 : Place PMOS symbols over schematic

Figure 4.7 place PMOS symbols

STEP 8 : select voltage components

Figure 4.8 Select voltage component

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STEP 9 : Select draw wire from edit menu to connect the components

Figure 4.9 select draw wire

STEP 10 : Wire all the components to obtain final schematic

Figure 4.10 wire all components

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CHAPTER 5

RESULT & ANALYSIS

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5.1 MIXED MODE FULL ADDER

5.1.1 PART 1: VOLTAGE MODE CIRCUIT

Fig 5.1

When B=0, A=C=1, then only A & C in pulldown & B in pullup network will ON.

We get, AC

When A=0, B=C=1, then only B & C in pulldown & A in pullup network will ON.

We get, BC+BCC = BC

When C=0, A=B=1, then only A & B in pulldown & C in pull up network will ON.

We get, ABB = AB

Combining these three results we get,

carry=AB+BC+AC

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5.1.2 PART 2: CURRENT MODE CIRCUIT

Fig 5.2

CASE 1

When A=0, B=1 & C=1

Only PMOS A will ON. Carry bar PMOS is also in ON Condition for these three inputs.

As W/L ratio of carry bar PMOS is double the other PMOS used. Sufficient voltage will be provided to turn on the NMOS of NOT gate.

We get, SUM=0

CASE 2

When A=1, B=0 & C=0

Both the PMOS B & C will ON. Carry bar PMOS is in OFF condition for these three inputs.

Sufficient voltage will not be provided to turn ON the NMOS of NOT gate & only PMOS of NOT gate will be in ON condition .

We get, SUM=1

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TABLE 5 RESULT FOR DIFFERENT INPUTS:

A B C CARRY BAR

SUM

0 0 0 1 2v

0 21mv

0 0 1 1 2v

1 42mv

0 1 0 1 2v

1 42mv

0 1 1 0 32nv

0 26mv

1 0 0 1 2v

1 42mv

1 0 1 0 0v 0 26mv

1 1 0 0 0v 0 26mv

1 1 1 0 10nv

1 60mv

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5.2 CARRY BAR & SUM OUPUT WAVEFORMS FOR DIFERENT INPUTS:

CASE 1

When A=0, B=0 & C=0

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CASE 2

When A=0, B=0 & C=1

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CASE 3

When A=0, B=1 & C=0

CASE 4

When A=0, B=1 & C=1

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CASE 5

When A=1, B=0 & C=0

CASE 6

When A=1, B=0 & C =1

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CASE 7

When A=1, B=1 & C=0

CASE 8

When A=1, B=1 & C=1

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CONCLUSION

A well-known problem in the field of VLSI designing is the chip area. Addition is one of the most fundamental arithmetic operations and adder is one of the most important component in designing of advanced technologies. In previous adder designs component count is very high and use of capacitors along with transistors will increase its size further. These adders occupy larger chip area and high component count will increase the complexity of the circuit.

The adder we designed has least component count and simple circuitry. It helps in reducing the chip area and its operation is based on mixed mode. The mix mode of operation provides the facility to use voltage mode and current mode of operation simultaneously. The simultaneous use of voltage mode and current mode provides the benefits of both and help to overcome the flaws occurred in both. Operation of this circuit is based on a simple majority function which eliminates the use of lengthy calculations and complex operations.

This adder design have application in designing of electronic devices such as calculators, central processing unit (CPU), Microprocessors and application specific DSP etc. In future it will help in reducing the power consumption and circuit delay due to its smaller size and lower component count

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REFERENCES[1] International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.2, June 2011

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[5] N. Weste and D. Harris, (2005) CMOS VLSI Design, Pearson Wesley.

[6] J. Uyemura, (1999) CMOS Logic Circuit Design, Kluwer.

[7] N. Jha and S. Gupta, (2003) Testing of Digital Systems. Cambridge, U.K.: Cambridge Univ. Press.

[8] J. M. Rabaey, A. Chandrakasan, B. Nikolic, (2002) “Digital Integrated Circuits, A designPerspective,” 2nd Prentice Hall, Englewood Cliffs, NJ.

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[10] A. P. Chandrakasan and R.W. Brodersen, (1995) Low Power Digital CMOS Design, KluwerAcademic Publishers.

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