Project Documentation Gsm Based Power Conservation System

CONTENTS

CHAPTER 1: INTRODUCTION………………………………………..…....... 5

CHAPTER 2: BLOCK DIAGRAM AND DESCRIPTION…………………... 7

CHAPTER 3: HARDWARE DESCRIPTION

3.1: MICROCONTROLLER 89C52

3.1.1: FEATURES………………………………………….... 11

3.1.2: PIN DIAGRAM AND ITS DESCRIPTION……….…. 12

3.1.3: ARCHITECTURE OF 89C52……………………….... 14

3.1.4: THE ON-CHIP OSCILLATORS……………….…..… 18

3.1.5: MEMORY ORGANISATION………………….…..… 20

3.1.6: SPECIAL FUNCTION REGISTERS……………….... 23

3.2: DTMF DECODER CM 8870………………………….….… 24

3.2.1: PIN DIAGRAM- CM8870……………………………. 25

3.2.2: FEATURES…………………………………………… 26

3.2.3: FUNCTIONAL DESCRIPTION……………………... 26

3.2.4: FILTER SECTION………………………………...…. 26

3.2.5: DECODER SECTION…………………………...…… 27

3.2.6: INPUT CONFIGURATION………………………….. 28

3.2.7: CLOCK CIRCUIT………………………..…………... 28

3.2.8: DTMF DETECTION…………………………………. 29

3.3: POWER SUPPLY…………………………………………… 30

3.4: VOLTAGE REGULATOR

3.4.1: LM 78XX SERIES VOLTAGE REGULATOR…….... 33

3.4.2: POSITIVE VOLTAGE REGULATOR………....……. 34

CHAPTER 4: GLOBAL SYSTEM FOR MOBILE COMMUNICATION

4.1: INTRODUCTION…………………………………………..… 36

4.2: GSM ARCHITECTURE……………..………………………. 37

4.3: SERVICES PROVIDED BY GSM………………….………. 39

CHAPTER 5: MAKING OF PCB

5.1: INTRODUCTION…………………………………………… 40

5.2: THE ART WORK………………….………………………… 43

5.3: THE ETCHING……………………………………….……… 43

5.4: DRILLING……………………………………………..…….. 44

5.5: ADVANTAGES OF PCB………………………….………… 44

CHAPTER 6: CONCLUSION AND FUTURESCOPE

6.1: ADVANTAGES AND APPLICATIONS …….…………….. 46

6.2: RESULT…………………….………………………………... 46

6.3: CONCLUSION…………………….………………………… 47

6.4: FUTURESCOPE………………….………………………….. 47

CHAPTER 7: ANNEXURE

7.1: FLOWCHART……………………………………….………. 49

7.2: PROGRAM CODE……………………………………..……. 52

7.3: KIT VIEW……………………………………………………. 59

7.4: BIBILOGRAPHY………………………............................... 60

2

FIGURE CONTENTS

FIGURE 2.1: Block Diagram of GSM BASED POWER

CONSERVATION SYSTEM…………………………………….. 7

FIGURE 2.2: Circuit Diagram……………………………………………………. 9

FIGURE 3.1: Pin Diagram-89C52 Microcontroller ………………………............ 12

FIGURE 3.2: Architecture-89C52 Microcontroller………………………………. 14

FIGURE 3.3: Reset Connection in 89C52…………………...…………………… 17

FIGURE 3.4: On-Chip Oscillators in 89C52……………….……………….......... 19

FIGURE 3.5: Pin Diagram-CM8870 DTMF Decoder……..…………….……….. 25

FIGURE 3.6: Functional Block Diagram of CM8870…….……………………… 29

FIGURE 3.7: DTMF Decoder-Truth Table……………………………………… 30

FIGURE 3.8: Block Diagram of Regulated Power Supply………………………. 31

FIGURE 3.9: Circuit Diagram of Regulated Power Supply.……………….. …... 32

FIGURE 4.1: GSM Architecture…………………………….…………………… 38

FIGURE 7.1: Flow Chart…………………………………………………………. 49

FIGURE 7.2: Kit View……………………………………………………………. 59

3

CHAPTER1

INTRODUCTION

4

INTRODUCTION

The “GSM BASED POWER CONSERVATION SYSTEM” in Railways is

an example of embedded system. An embedded system includes both hardware and

software. In its simplest form, these consist of a microcontroller with software written

in either high level language compilers/assembly language. Here we are written the

program code in TASM (assembly language) and then dumped it into the

controller/chip.

Our kit consists the microcontroller, 89C52 to which the input data is given from

DTMF decoder, CM8870.For the DTMF decoder, the input signal is coming from the

GSM module/Phone. Whenever the user makes a call to that particular SIM (Subscriber

Index Module) number present in the kit, then the phone/GSM module goes into

automatic answer mode and the signal send by the user will be decoded by decoder and

then finally fed to the microcontroller. The corresponding load/light will be ON/OFF

according to the program written in the controller.

Here we provide the acknowledgement a single beep sound for ON state and

two beeps for OFF state of the load. Authentication is also provided here by giving a

password(here ‘*’ key is the password) to the user .Therefore, every time whenever the

user switch on the kit ,first of all he has to press the password key(‘*’ key).

The detailed description of working and hardware components is explained in

the following chapters.

5

CHAPTER 2

BLOCK DIAGRAM AND

DESCRIPTION

6

GSM BASED POWER CONSERVATION SYSTEM -BLOCK DIAGRAM

The schematic of “GSM BASED POWER CONSERVATION SYSTEM”

can be as shown in the figure. Whenever the user made a call to the number in GSM

module/phone, then automatically it goes into auto answer mode and the signal

(frequency corresponding to key pressed on the phone keypad) send by the user is

decoded by the DTMF decoder. This decoded signal acts like a strobe signal at P1.4 pin

of the microcontroller. It senses the strobe signal and then the function corresponding to

the decoded value will be performed by the controller according to the program code

written in it. Then the corresponding load/light will be ON/OFF by means of the relay

connected between the controller and the load.

Fig 2.1: Block diagram

Note: PNL ON PF1,2,3,4 means Part Night Light Section On Platform1,2,3,4

respectively.

7

AT89C52Micro

Controller

Telephone (or)

GSM module

RLY2DTMF decoder CM8870

RLY4

RLY3

RLY1

PNL ON PF2

PNL ON PF3

PNL ON PF4

PNL ON PFI

RESET OSCILLATOR

Audio Transformer

Here we also provide the acknowledgement, a single beep sound for ON state

and two beeps for OFF state of the load/light. Authentication is also provided here by

giving a password(here ‘*’ key is the password) to the user .Therefore, every time

whenever the user switch on the kit ,first of all he has to press the password key(‘*’

key), if it matches then only the next given input will be taken otherwise the will be

terminated.

8

CIRCUIT DIAGRAM:

R 18 . 2 K

D 7

4 1 4 8

D 1 7

4 0 0 7

C 1 03 3 p

D 1 5

4 1 4 8

G n d

Q 1 3B C 5 4 7

+1 2 v

R 1 03 3 0 K

C 93 3 p

D 1 6

4 1 4 8

C 33 3 p

+1 2 v

PhoneLine

R L 2

35

412

R N 1 =1 0 3

1 2 3 4 5 6 7 8 9

D 1 4

4 0 0 7

Y 13 . 5 7 9

D 14 0 0 7 V C C

Q 1 1B C 5 4 7

Q 1 4B C 5 4 7

R 1 31 5 0 K

D 2 04 1 4 8

D 54 0 0 7

Q 1 5B C 5 4 7

-

D 1 1

4 0 0 7

D 1 8

4 1 4 8Q 1 5B C 5 4 7

S W 2

+

C 1 91 0 / 1 6 0 v

R L 5

35

412

D 1 2

4 1 4 8

D 64 0 0 7

D 44 0 0 7

Q 8B C 5 4 7

C 23 3 p

S W 1

D 1 8

4 1 4 8

U 2L 7 8 0 5

1

3

2V I N

GND

V O U T

R L 4

35

412

U 7

c m 8 8 7 0 1 8

1 6

1 7

1234

567

8

1 11 21 31 41 5

9 1 0

V c c

E S t

S t / G T

in +in _g sV -re f

in HP Do s c 1

o s c 2

Q 0Q 1Q 2Q 3

S t D

G n d TO E

C 1 03 3 p

S W 4

V C C

+1 2 v

D 1 0

4 1 4 8

V C C

+C 21 0 0 / 1 6

RN1=10

3

1 2 3 4 5 6

V C C

V C C

C 41 0 / 1 6 v

+

-

U 5 A

L M 3 9 3

12

3

+1 2 v

Y 11 1 . 0 5 9 2

C N 1P o w e r

1234

D 34 0 0 7

C O M

Q 9B C 5 4 7

U 5

A T8 9 C 5 1 / F P

9

1918

2 0

2 93 03 1

4 012345678

3 23 33 43 53 63 73 83 9

2 12 2

1 21 31 41 51 61 7

R S TXTA

L2XTA

L1

G N D

P S E NA L E / P R O G

E A / V P P

V C CP 1 . 0P 1 . 1P 1 . 2P 1 . 3P 1 . 4P 1 . 5P 1 . 6P 1 . 7

P 0 . 7P 0 . 6P 0 . 5P 0 . 4P 0 . 3P 0 . 2P 0 . 1

P 0 . 0

P 2 . 0P 2 . 1

P 3 . 2 / I N T0P 3 . 3 / I N T1P 3 . 4 / T0P 3 . 5 / T1P 3 . 6 / W RP 3 . 7 / R D

R 1 2

1 0 0 kD 9

4 1 4 8

T5

1 : 1 A u d io Tra n

1 5

6

4 8

P11 RESIST

OR VAR

R 1 11 0 k

D 8

4 0 0 7

C 1 5

1 0 4 j

S W 3

C 1 61 0 4 p

Q 1 6B C 5 4 7

P12 RESIST

OR VAR

Q 1 0B C 5 4 7

+C 11 0 0 0 / 2 5

L S 12 0 -2 0 5 1 -D P D T

68

7

34

512

R L 3

35

412

C 1 80 . 1

Q 1 4B C 5 4 7

+

D 24 0 0 7

D 1 3

4 1 4 8

Fig 2.2: Circuit Diagram

9

CHAPTER 3

HARDWARE DESCRIPTION

10

3.1: MICROCONTROLLER 89C52:

3.1.1: FEATURES:

Compatible with MCS-51 Products.

8K Bytes of In-System Reprogrammable Flash Memory.

Endurance: 1,000 Write/Erase Cycles.

Fully Static Operation: 0 Hz to 24 MHz.

Three-level Program Memory Lock.

256 x 8-Bit Internal RAM.

32 Programmable I/O Lines.

Three 16-bit Timer/Counters.

Eight Interrupt Sources.

Programmable Serial Channel.

Low Power Idle and Power Down Modes

3.1.2: PIN DIAGRAM AND ITS DESCRIPTION:

The microcontroller generic part number actually includes a whole family of

microcontrollers that have numbers ranging from 8031to 8751 and are available in N-

Channel Metal Oxide Silicon (NMOS) and Complementary Metal Oxide Silicon

(CMOS) construction in a variety of package types.

11

PIN DIAGRAM

Fig 3.1: Pin Diagram

with 4Kbytes of Flash Programmable and Erasable Read Only Memory

(PEROM). The device is manufactured using Atmel’s high density nonvolatile memory

technology and is compatible with the industry standard MCS-51 instruction set and

12

pinout. The on-chip Flash allows the program memory to be reprogrammed in-system

or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit

CPU with Flash on a monolithic chip, the Atmel AT89C52 is a powerful

microcomputer which provides a highly flexible and cost effective solution to many

embedded control applications.

The AT89C52 provides the following standard features: 4 Kbytes of Flash, 256

bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt

architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition,

the AT89C52 is designed with static logic for operation down to zero frequency and

supports two software selectable power saving modes. The Idle Mode stops the CPU

while allowing the RAM, timer/counters, serial port and interrupt system to continue

functioning. The Power Down Mode saves the RAM contents but freezes the oscillator

disabling all other chip functions until the next hardware reset.

13

3.1.3: ARCHITECTURE OF 89C52

Fig 3.2:Architecture of 89C52

Port 0:

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin

can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as

14

high-impedance inputs. Port 0 may also be configured to be the multiplexed low order

address/data bus during accesses to external program and data memory. In this mode P0

has internal pull-ups. Port 0 also receives the code bytes during Flash programming, and

outputs the code bytes during program verification. External pull-ups are required

during program verification

Port 1:

Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output

buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are

pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that

are externally being pulled low will source current (IIL) because of the internal pull-

ups. Port 1 also receives the low-order address bytes during Flash programming and

program verification.

Alternate functions of port 1

Port 2:

Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output

buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are

pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that

are externally being pulled low will source current (IIL) because of the internal

15

pullups.Port 2 emits the high-order address byte during fetches from external program

memory and during accesses to external data memory that use 16-bit addresses (MOVX

A,@DPTR). In this application it uses strong internal pull-ups when emitting 1s. During

accesses to external data memory that uses 8-bit addresses (MOVX A,@RI), Port 2

emits the contents of the P2 Special Function Register. Port 2 also receives the high-

order address bits and some control signals during Flash programming and verification.

Port 3:

Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output

buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are

pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that

are externally being pulled low will source current (IIL) because of the pullups. Port 3

also serves the functions of various special features of the AT89C52 as listed below:

Alternate functions of port 3

RST:

RST means RESET, 89C52 uses an active high reset pin. It must go high for two

machine cycles. The simple RC circuit used here will supply voltage (Vcc) to reset pin

until capacitance begins to charge. At a threshold of about 2.5V, reset input reaches a

low level and system begin to run.

16

Fig: 3.3: Reset Connection

ALE/PROG:

Address Latch Enable output pulse for latching the low byte of the address

during accesses to external memory. This pin is also the program pulse input (PROG)

during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6

the oscillator frequency, and may be used for external timing or clocking purposes.

Note, however, that one ALE pulse is skipped during each access to external Data

Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location

8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction.

Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the

microcontroller is in external execution mode.

PSEN:

Program Store Enable is the read strobe to external program memory. When the

AT89C52 is executing code from external program memory, PSEN is activated twice

each machine cycle, except that two PSEN activations are skipped during each access to

external data memory.

17

EA/VPP:

External Access Enable. EA must be strapped to GND in order to enable the

device to fetch code from external program memory locations starting at OOOOH up to

FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched

on reset. EA should be strapped to Vcc for internal program executions. This pin also

receives the 12-volt programming enable voltage (Vpp) during Flash programming, for

parts that require 12-volt Vpp.

XTAL1: Input to the inverting oscillator amplifier and input to the internal clock

operating circuit

XTAL2: Output from the inverting oscillator amplifier.

T2: External count input to Timer/Counter 2, Clock out.

T2EX: Counter 2 capture/reload trigger & direction control.

3.1.4: THE ON-CHIP OSCILLATORS

Pins XTAL1 and XTAL2 are provided for connecting a resonant network to

form an oscillator. The crystal frequency is basic internal clock frequency. The

maximum and minimum frequencies are specified from 1to 24MHZ.

Program instructions may require one, two or four machine cycles to be

executed depending on type of instructions. To calculate the time any particular

instructions will take to be executed, the number of cycles ‘C’,

T = C*12d / Crystal frequency

Here, we chose frequency as 11.0592MHZ. This is because,

baud= 2*clock frequency/(32d. 12d[256d-TH1]).The oscillator is chosen to help

generate both standard and nonstandard baud rates. If standard baud rates are desired,

18

an 11.0592MHZ crystal should be selected. From our desired standard rate, TH1 can be

calculated. The internally implemented value of capacitance is 33 pf.

Fig 3.4:On-Chip Oscillators

Program Memory Lock Bits:

On the chip there are three lock bits which can be left unprogrammed (U) or can

be programmed (P) to obtain the additional features .When lock bit 1 is programmed,

the logic level at the EA pin is sampled and latched during reset. If the device is

powered up without a reset, the latch initializes to a random value, and holds that value

until reset is activated. It is necessary that the latched value of EA be in agreement with

the current logic level at that pin in order for the device to function properly.

Program Counter and Data Pointer:

The 89C52 contains two 16-bit registers: the program counter (PC) and the data

pointer (DPTR), Each is used to hold the address of a byte in memory. The PC is the

only register that does not have an internal address. The DPTR is under the control of

program instructions and can be specified by its 16-bit name, DPTR, or by each

individual byte name, DPH and DPL. DPTR does not have a single internal address,

DPH and DPL are each assigned an address.

19

A & B Registers:

The 89C52 contains 34 general-purpose, working, registers. Two of these,

registers A and B, hold results of many instructions, particularly math and logical

operations, of the 89C52 CPU. The other 32 are arranged as part of internal RAM in

four banks, B0-B3, of eight registers. The A register is also used for all data transfers

between the 89C52 and any external memory. The B register is used for with the A

register for multiplication and division operations.

Flags and the Program Status Word (PSW):

Flags may be conveniently addressed, they are grouped inside the program

status word (PSW) and the power control (PCON) registers.

The 89C52 has four math flags that respond automatically to the outcomes of

math operations and three general-purpose user flags that can be set to 1 or cleared to 0

by the programmer as desired. The math flags include Carry (C), Auxiliary Carry (AC),

Overflow (OV), and Parity (P). User flags are named F0,GF0 and GF1, they are

general-purpose flags that may be used by the programmer to record some event in the

program.

3.1.5: MEMORY ORGANISATION

Internal Memory:

The 89C52 has internal RAM and ROM memory for the functions. Additional

memory can be added externally using suitable circuits. This has a Hardware

architecture, which uses the same address, in different memories, for code and data.

20

Internal RAM:

The 256-byte internal RAM. The upper 128 bytes occupy a parallel address

space to the Special Function Registers. Instructions that use indirect addressing access

the upper 128 bytes of RAM. Stack operations are examples of indirect addressing.

Internal Data Memory addresses are always one byte wide, which implies an

address space of only 256 bytes. However, the addressing modes for internal RAM can

in fact accommodate 384 bytes, using a simple trick. Direct addresses higher than 7FH

access one memory space, and indirect addresses higher than 7FH access a different

memory space. Thus Figure shows the Upper 128 and SFR space occupying the same

block of addresses, 80H through FFH, although they are physically separate entities.

The Lower 128 bytes of RAM are present in all 89C52 devices as mapped in

Figure. The lowest 32 bytes are grouped into 4 banks of 8 registers. Program

instructions call out these registers as R0 through R7.

Two bits in the Program Status Word (PSW) select which register bank is in use.

This allows more efficient use of code space, since register instructions are shorter than

instructions that use direct addressing. The next 16 bytes above the register banks form

a block of bit addressable memory space. The 89C52 instruction set includes a wide

selection of single-bit instructions, and the 128 bits in this area can be directly

addressed by these instructions. The bit addresses in this area are 00H through 7FH. All

of the bytes in the Lower 128 can be accessed by either direct or indirect addressing.

The Upper 128 can only be accessed by indirect addressing. SFRs include the

Port latches, timers, peripheral controls, etc. These registers can only be accessed by

direct addressing. Sixteen addresses in SFR space are both byte- and bit-addressable.

The bit-addressable SFRs are those whose address ends in OH or 80H.

21

The Stack and Stack Pointer:

The stack refers to an area of internal RAM that is used in conjunction with

certain opcodes to store and retrieve data quickly. The 8-bit stack pointer register is

used by the 89C52 to hold an internal RAM address that is called the top of the stack.

The address held in the SP register is the location in internal RAM where the last byte

of data was stored by a stack operation. When data is to be placed on the stack, the SP

22

increments before storing data on the stack so that the stack grows up as data is stored.

As data is retrieved from the stack, the byte is read from the stack, then the SP

decrements to point to the next available byte of stored data.

3.1.6: SPECIAL FUNCTION REGISTERS

The 89C52 operations that do not use the internal 128-byte RAM addresses from

00h to 7Fh are done by a group of specific internal registers, each called a Special

Function register, which may be addressed much like internal RAM, using addresses

from 80h to FFh. PC is not part of the SFR and has no internal RAM address

23

3.2 DTMF DECODER (CM8870)

DESCRIPTION

The CM8870/70C provides full DTMF receiver capability by integrating both

the band split filter and digital decoder functions into a single 18-pin DIP, SOIC, or 20-

pin PLCC package. The CM8870/70C is manufactured using state-of-the-art CMOS

process technology for low power consumption (35mW, max.) and precise data

24

handling. The filter section uses a switched capacitor technique for both high and low

group filters and dial tone rejection. TheCM8870/70C decoder uses digital counting

techniques for the detection and decoding of all 16 DTMF tone pairs into a 4-bit code.

This DTMF receiver minimizes external component count by providing an on-chip

differential input amplifier, clock generator, and a latched three-state interface bus. The

on-chip clock generator requires only a low cost TV crystal or ceramic resonator as an

external component.

3.2.1: PIN DIAGRAM- CM8870

Fig 3.5: Pin Diagram-CM8870

25

3.2.2: FEATURES

Full DTMF receiver

Less than 35mW power consumption

Industrial temperature range

Uses quartz crystal or ceramic resonators

Adjustable acquisition and release times

18-pin DIP, 18-pin DIP EIAJ, 18-pin SOIC, 20-pin

3.2.3: FUNCTIONAL DESCRIPTION

The CAMD CM8870/70C DTMF Integrated Receiver provides the design

engineer with not only low power consumption, but high performance in a small 18-pin

DIP, SOIC, or 20-pin PLCC package configuration. The CM8870/70C’s internal

architecture consists of a band split filter section which separates the high and low tones

of the received pair, followed by a digital decode (counting) section which verifies both

the frequency and duration of the received tones before passing the resultant 4-bit code

to the output bus.

3.2.4: FILTER SECTION

Separation of the low-group and high-group tones is achieved by applying the

dual-tone signal to the inputs of two 9th-order switched capacitor band pass filters. The

bandwidths of these filters correspond to the bands enclosing the low-group and high-

group tones . The filter section also incorporates notches at 350 Hz and 440 Hz, which

provide excellent dial tone rejection.

Each filter output is followed by a single order switched capacitor section which

smoothes the signals prior to limiting. High gain comparators perform signal limiting.

26

These comparators are provided with a hysteretic to prevent detection of unwanted low-

level signals and noise. The outputs of the comparators provide full-rail logic swings at

the frequencies of the incoming tones.

3.2.5: DECODER SECTION

The CM8870/70C decoder uses a digital counting technique to determine the

frequencies of the limited tones and to verify that these tones correspond to standard

DTMF frequencies. A complex averaging algorithm is used to protect against tone

simulation by extraneous signals (such as voice) while providing tolerance to small

frequency variations. The averaging algorithm has been developed to ensure an

optimum combination of immunity to “talk-off” and tolerance to the presence of

interfering signals (third tones) and noise. When the detector recognizes the

simultaneous presence of two valid tones (known as “signal condition”), Steering

Circuit.

Before the registration of a decoded tone pair , the receiver checks for a valid

signal duration (referred to as “character recognition condition”).This check is

performed by an external RC time constant driven by Est. A logic high on EStcauses

VC to rise as the capacitor discharges. Providing signal condition is maintained (Est.

remains high) for the validation period (tGTP), VC reaches the threshold (VTSt) of the

steering logic to register the tone pair, thus latching its corresponding 4-bit code into the

output latch.

At this point, the GT output is activated and a drive VC to DD.GT continues to

drive high as long as ESt remains high, signaling that a received tone pair has been

registered. The contents of the output latch are made available on the 4-bitoutput buses

by raising the three-state control input (TOE) to a logic high. The steering circuit works

27

in reverse to validate the inter digit pause between signals. Thus, as well as rejecting

signals too short to be considered valid, the receiver will tolerate signal interruptions

(drop outs) too short to be considered a valid pause.

This capability together with the capability of selecting the steering time

constants externally, allows the designer to tailor performance to meet a wide variety of

system requirements.

3.2.6: INPUT CONFIGURATION

The input arrangement of the CM8870/70C provides a differential input

operational amplifier as well as a bias source(Vref) which is used to bias the inputs at

mid-rail. Provision is made for connection of a feedback resistor to the op-amp output

(GS) for adjustment of gain. In a single-ended configuration, the input pins are

connected as shown in Figure, with the op-amp connected for unity gain and Vref

biasing the input at ½ VDD. Figure 6 shows the differential configuration, which

permits the adjustment of gain with the feedback resistor R5.

3.2.7: CLOCK CIRCUIT

The internal clock circuit is completed with the addition of a standard television

color burst crystal or ceramic resonator-having a resonant frequency of 3.579545 MHz.

TheCM8870C in a PLCC package has a buffered oscillator output (OSC3) that can be

used to drive clock inputs of other devices such as a microprocessor or other CM8870’s

as shown in Figure. Multiple CM8870/70Cs can be connected as shown in figure 8

such that only one crystal or resonator is required.

28

3.2.8: DTMF DETECTION

The CM8870 is a single chip DTMF receiver incorporating switched capacitor

filter technology and an advanced digital counting/averaging algorithm for period

measurement. The block diagram illustrates the internal working of this device shown

in the figure.

Fig 3.6: Functional Block Diagram of CM8870

The DTMF signal is first buffered by an input op-amp that allows adjustment of

gain and choice of input configuration. The input stage is followed by a continuous low

pass RC active filter which performs an anti aliasing function. Dial tone at 350 and 440

Hz is then rejected by a 3rd order switched capacitor filter. The signal is still in its

composite form and is split into its individual components by two 6th order and switched

capacitor and pass filters. Each component is smoothed by an output filter and squared

by a hard limiting comparator. The two resulting rectangular waveforms are then

applied to a

29

digital circuitry where a counting algorithm measures and averages their periods. An

accurate reference clock is derived from an inexpensive external 3.58 MHz crystal.

F low F high KEY TOE Q4 Q3 Q2 Q1 697 1209 1 1 0 0 0 1 697 1336 2 1 0 0 1 0 697 1477 3 1 0 0 1 1 770 1209 4 1 0 1 0 0 770 1336 5 1 0 1 0 1 770 1477 6 1 0 1 1 0 852 1209 7 1 0 1 1 1 852 1336 8 1 1 0 0 0 852 1477 9 1 1 0 0 1 941 1209 0 1 1 0 1 0 941 1336 * 1 1 0 1 1 941 1477 # 1 1 1 0 0 679 1633 A 1 1 1 0 1 770 1633 B 1 1 1 1 0 852 1633 C 1 1 1 1 1 941 1633 D 1 0 0 0 0 - ANY 0 Z Z Z Z

Fig 3.7: CM8870 output Truth table

3.3: POWER SUPPLY

The supply given is the +5V D.C. The incoming power is 230V A.C, there is a

need to convert it into +5V D.C.

The input a.c. supply is stepped down from 230V to 9-0-9V. The rectifier consists

of diodes D1 and D2 makes the supply D.C. that is, unidirectional waveform. The

output from rectifier is a URDC, whose value is 12.726V peak to peak. The voltage

regulator makes this URDC to RDC of +5V. The capacitor C1 is used to maintain

constant voltage between two consecutive positive cycles where as C2 is used to

remove the fluctuations caused by regulator. Here we are selecting 12.726V as a peak

value. Because of fluctuations, the peak voltage may decrease, then regulator cannot

30

step up to +5V. If we select peak value, a higher one, then the problem can be

overcome.

Fig 3.8: BLOCK DIAGRAM OF R.P.S

A regulated power supply which maintains the output voltage constant

irrespective of a.c. mains fluctuations or load variations is known as regulated power

supply. A regulated power supply consists of an ordinary power supply and voltage

regulating device.

The output of ordinary power supply is fed to the voltage regulator which

produces the final output. The output voltage remains constant whether the load current

changes or there are fluctuations in the input a.c. voltage.

The rectifier converts the transformer secondary a.c. voltage into pulsating

voltage. The pulsating d.c. voltage is applied to the capacitor filter. This filter reduces

the pulsations in the rectifier d.c. output voltage. Finally, it reduces the variations in the

filtered output voltage

Need of RPS: In an ordinary power supply, the voltage regulation is poor i.e.

d.c. output voltage changes with load current. Output voltage also changes due to

variations in the input a.c. voltage.

31

Fig 3.9: CIRCUIT DIAGRAM OF R.P.S

This is due to the following reasons:

1. There are considerable variations in a.c. line voltage caused by outside factors

beyond our control. This changes the d.c. output voltage. Most of the electronic

circuits will refuse to work satisfactorily on such output voltage fluctuations.

These necessities to use regulated d.c. power supply.

2. The internal resistance of ordinary power supply in relatively large. Therefore,

output voltage is markedly affected by the amount of load current drawn from

the supply.

These variations in d.c. voltage may cause erratic operation of electronic

circuits. Therefore, regulated d.c. power supply is the only solution in such

situations.

32

3.4.1: LM 78XX SERIES VOLTAGE REGULATOR

The LM 78XXX series of the three terminal regulations is available with several

fixed output voltages making them useful in a wide range of applications. One of these

is local on card regulation. The voltages available allow these regulators to be used in

logic systems, instrumentation and other solid state electronic equipment. Although

designed primarily as fixed voltage regulators, these devices can be used with external

components to obtain adjustable voltages and currents. The LM78XX series is

available in aluminum to 3 packages which will allow over 1.5A load current if

adequate heat sinking is provided. Current limiting is included to limit the peak output

current to a safe value. The LM 78XX is available in the metal 3 leads to 5 and the

plastic to 92. For this type, with adequate heat sinking. The regulator can deliver

100mA output current.

The advantage of this type of regulator is, it is easy to use and minimize the

number of external components.

The following are the features voltage regulators:

a) Output current in exces of 1.5A for 78 and 78L series

b) Internal thermal overload protection

c) No external components required

d) Output transistor sage area protection

e) Internal short circuit current limit.

f) Available in aluminum 3 package.

33

3.4.2: POSITIVE VOLTAGE REGULATOR

The positive voltage regulator has different features like

Output current up to 1.5A

No external components

Internal thermal overload protection

High power dissipation capability

Internal short-circuit current limiting

Output transistor safe area compensation

Direct replacements for Fairchild microA7800 series

Nominal

Output Voltage

Regulator

5V uA7805C

6V uA7806C

8V uA7808C

8.5V uA7885C

10V uA7810C

12V uA7812C

15V uA7815C

18V uA7818C

24V uA7824C

34

CHAPTER 4

GSM-

GLOBAL SYSTEM FOR MOBILE

COMMUNICATION

35

4.1: INTRODUCTION

GSM (Global System for Mobile communications) is the technology that

underpins most of the world's mobile phone networks. The GSM platform is a hugely

successful wireless technology and an unprecedented story of global achievement and

cooperation. GSM has become the world's fastest growing communications technology

of all time and the leading global mobile standard, spanning 214 countries.

Global System for Mobile communications (GSM) is the most popular

standard for mobile phones in the world.GSM differs from its predecessors in that both

signalling and speech channels are digital call quality, and thus is considered a second

generation (2G) mobile phone system. This has also meant that data communication

was easy to build into the system. The ubiquity of the GSM standard has been

advantageous to both consumers (who benefit from the ability to roam and switch

carriers without switching phones) and also to network operators (who can choose

equipment from any of the many vendors implementing GSM. GSM also pioneered a

low-cost alternative to voice calls, the Short message service (SMS, also called "text

messaging"), which is now supported on other mobile standards as well. One of the key

features of GSM is the Subscriber Identity Module (SIM), commonly known as a SIM

card. The SIM is a detachable smart card containing the user's subscription

information and phonebook. This allows the user to retain his or her information after

switching handsets. Alternatively, the user can also change operators while retaining the

handset simply by changing the SIM. Some operators will block this by allowing the

36

phone to use only a single SIM, or only a SIM issued by them.This practice is known as

SIM locking, and is illegal in some countries.

There are five different cell sizes in a GSM network— macro, micro, pico,

femto and umbrella cells. The coverage area of each cell varies according to

the implementation environment. Macro cells can be regarded as cells where the base

station antenna is installed on a mast or a build above average roof top level. Micro

cells are cells whose antenna height is under average roof top level, they are

typically used in urban areas. Picocells are small cells whose coverage diameter is a

few dozen meters, they are mainly used indoors. Femtocells are cells designed for

use in residential or s mall business environments and connect to the service

provider’s network via a broadband internet connection. Umbrella cells are used

to cover shadowed regions of smaller cells and fill in gaps in coverage between those

cells.

Indoor coverage is also supported by GSM and may be achieved by using an

indoor picocell base station, or an indoor repeater with distributed indoor antennas fed

through power splitters, to deliver the radio signals from an antenna outdoors to the

separate indoor distributed antenna system.These are typically deployed when a lot of

call capacity is needed indoors, for example in shopping centers or airports. However,

this is not a prerequisite, since indoor coverage is also provided by in-building

penetration of the radio signals from nearby cells.

4.2: GSM ARCHITECTURE

A GSM network is composed of several functional entities, whose functions and

interfaces are specified.The GSM network can be divided into three broad parts. The

Mobile Station is carried by the subscriber. The Base Station Subsystem controls the

37

radio link with the Mobile Station. The Network Subsystem, the main part of which

is the Mobile services Switching Center (MSC), performs the switching of calls

between the mobile users, and between mobile and fixed network users. The MSC

also handles the mobility management operations. Not shown is the Operations and

Maintenance Center, which oversees the proper operation and setup of the network.

The Mobile Station and the Base Station Subsystem communicate across the Um

interface, also known as the air interface or radio link. The Base Station Subsystem

communicates with the Mobile services Switching Center across the A interface.

Figure 4.1 General architecture of a GSM network

4.2.1: Mobile Station

The mobile station (MS) consists of the mobile equipment (the terminal) and a

smart card called the Subscriber Identity Module (SIM). The SIM provides personal

mobility, so that the user can have access to subscribed services irrespective of a

specific terminal. By inserting the SIM card into another GSM terminal, the user is

38

able to receive calls at that terminal, make calls from that terminal, and receive other

subscribed services.

4.2.2: Base Station Subsystem

The Base Station Subsystem is composed of two parts, the Base Transceiver

Station (BTS) and the Base Station Controller (BSC). The Base Transceiver Station

houses the radio transceivers that define a cell and handles the radio-link protocols with

the Mobile Station. The Base Station Controller manages the radio resources for one or

more BTSs. It handles radio-channel setup, frequency hopping, and handovers.

4.2.3: Network Subsystem

The central component of the Network Subsystem is the Mobile services

Switching Center (MSC). It acts like a normal switching node of the PSTN or ISDN,

and additionally provides all the functionality needed to handle a mobile subscriber,

such as registration, authentication, location updating, handovers, and call routing to a

roaming subscriber. These services are provided in conjuction with several functional

entities, which together form the Network Subsystem

4.3: SERVICES PROVIDED BY GSM

From the beginning, the planners of GSM wanted ISDN compatibility in terms

of the services offered and the control signaling used. However, radio transmission

limitations, in terms of bandwidth and cost, do not allow the standard ISDN B-channel

bit rate of 64 kbps to be practically achieved. The most basic teleservice supported by

GSM is telephony. As with all other communications, speech is digitally encoded and

transmitted through the GSM network as a digital stream. There is also an emergency

service, where the nearest emergency-service provider is notified by dialing three digits.

39

A variety of data services is offered. GSM users can send and receive data, at

rates up to 9600 bps, to users on POTS (Plain Old Telephone Service), ISDN, Packet

Switched Public Data Networks, and Circuit Switched Public Data Networks using a

variety of access methods and protocols, such as X.25 or X.32. Since GSM is a digital

network, a modem is not required between the user and GSM network, although an

audio modem is required inside the GSM network to interwork with POTS.

A unique feature of GSM, not found in older analog systems, is the Short

Message Service (SMS). SMS is a bidirectional service for short alphanumeric (up to

160 bytes) messages. Messages are transported in a store-and-forward fashion. For

point-to-point SMS, a message can be sent to another subscriber to the service, and an

acknowledgement of receipt is provided to the sender. SMS can also be used in a cell-

broadcast mode, for sending messages such as traffic updates or news updates.

Messages can also be stored in the SIM card for later retrieval.

Supplementary services are provided on top of teleservices or bearer services. In

the current (Phase I) specifications, they include several forms of call forward (such as

call forwarding when the mobile subscriber is unreachable by the network), and call

barring of outgoing or incoming calls, for example when roaming in another country.

Many additional supplementary services will be provided in the Phase 2 specifications,

such as caller identification, call waiting, multi-party conversations.

40

CHAPTER 5

MAKING OF PCB

41

5.1: INTRODUCTION

One of the most discouraging things about making a hardware project is

building the printed circuit board-PCB.it is sometimes possible to use strip board or

some other pre-fabricated board but more often than not the circuit complexity and

performance requires a proper PCB to be made .The good news is that due to

improvements in printing and processing technologies it is now relatively easy to make

inexpensive high quality PCB’s at home.

WARNING-Making PCB’s requires the use of Ferric Chloride(FeCi3) which is

corrosive so avoid skin and eye contact .Remember safety-first so, use glasses, gloves

and protective overalls .Ferric Chloride is also very good at distorting cloths weeks after

you think you have washed it off. If you do get any on your skin then wash it off

immediately with lots of water and soap.

The Shopping List:

These are the minimum things needed:

Access to a PC with a Laser printer.

Water.

A one-liter glass jar.

PCB hand drill with 0.8mm drill bits.

Copper-Clad fiber glass board.

Ferric Chloride Copper etching fluid 250ml.

PCB cleaning rubber.

Safety glasses, gloves, cloths/overalls.

42

5.2: THE ARTWORK

The first stage is to transfer the circuit layout from the PC to the special Press-n-

Peel film. Put the film in the laser printer so that the print will appear on it. This will

produce a contact print where the black image will end up as copper on the final PCB.

Now to transfer the artwork to the Copper board by following the instructions with the

Press-n-Peel film:

Clean the copper board very well with the PCB cleaning rubber.

Heat the cloths iron to 300 deg F.

Hole the film with the print in contact to the copper and smoothly iron the film

down until the print appears black through the film (about 1min).

Allow 5min to cool down (or speed up this with water) then peel the film off.

This should produce a clean black print on to the copper. If you let the film

move or overheat then you will find that the tracks and writing will be smeared and out

of focus also the film may be wrinkled up. If you don’t use enough heat or heat

unevenly then the film may not stick or to be dark enough. In either case clean off the

PCB and try again, you should get it right after a couple of goes.

5.3: THE ETCHING

Etching the PCB is to remove the unwanted copper.

Dilute the concentrated Ferric Chloride fluid with water (1:1) and pour into the

one liter glass jar.

Put the PCB copper side up on the top tray and pour all Ferric Chloride on top.

Gently rock the top tray to keep the etch fluid moving avoiding spillage.

After about 15min all of the unwanted copper disappears.

43

Remove the board and drop it into a bucket of cold water to clean off.

5.4: DRILLING

Drilling with 0.8mm drill bits can be bit tricky as it is easy to break the drill bits.

Always hold the drill straight and do not bend it when the hole has started .Using a

0.8mm PCB drill bit, drill out all of the component holes that are required. So, now the

PCB is finished and it is ready to solder.

5.5: ADVANTAGES OF PCB

Reducing wiring errors.

Decreases assembly cost.

Typically consume less space than traditionally build circuits.

44

CHAPTER 6

CONCLUSION AND

FUTURESCOPE

45

6.1: ADVANTAGES AND APPLICATIONS

ADVANTAGES:

Small in size.

Easy to operate from a remote place.

Cost of manufacture is very less.

Flexibility of using in various applications.

APPLICATIONS:

After some small modifications made, the same kit can find many

applications.

Automation in industries ,house hold appliances etc

Also used in a remote areas where the facility of Cell network is provided.

6.2: RESULT

When the operator presses the buttons on the key pad of cell phone while

continuing a call the following operations are performed:

*- CALL CONNECTED (PASS WORD)

1-LOAD1 is ON

2- LOAD1 is OFF

3- LOAD2 is ON

4- LOAD2 is OFF

5- LOAD3 is ON

6- LOAD3 is OFF

7- LOAD4 is ON

46

8- LOAD4 is OFF

9-CALL DISCONNECTED

6.3: CONCLUSION

This project is aimed to conserve the energy/power in various sectors

such as in railways, home appliances etc and it was successfully completed and

implemented. By using this system at Vijayawada Railway station we can save around

Rs.5,00,000/- per annum.

Therefore by implementing this technique we can save large amount of

power and money.

FUTURE SCOPE:

This technique can be extended in the future by interfacing the controller

with PIC (Peripheral Interrupt Controller) to control/operate many more devices.

47

CHAPTER 7

ANNEXURE

48

7.1: FLOW CHART

49

50

51

------***------***-----***-----

52

7.2: PROGRAM CODE (ASSEMBLY LANGUAGE)

;P1.0=DATA

;P1.1=DATA

;P1.2=DATA

;P1.3=DATA

;P1.4=STB

;P1.5=

;P1.6=RLY

;P1.7

;P2.1=SW1

;P2.3=SW2

;P2.5=SW3

;P2.7=SW4

ORG 0 ;originating at 0 location

53

LJMP SAA ;jump to label saa

ORG 0050H

SAA: MOV P2,#00H ;all rly off

SA: MOV P1,#FFH

CLR P1.6 ;SET RLY TO PH LINE

CLR P1.7

MOV R0,#00H

LCALL DEL

RR: LCALL RINGCNT

CJNE R4,#01H, SA

XX:

JB P1.5,$

LCALL DEL1

JB P1.5,XX

INC R0

54

YY: JNB P1.5,$

LCALL DEL1

JNB P1.5,YY

CJNE R0,#05H,RR

SETB P1.6

LCALL WDSUBR

CJNE R4,#01H,DISC

LCALL DTD

CJNE R2,#0AH,DISC

FDF: LCALL WDSUBR

CJNE R4,#01H,DISC

LCALL DTD

CJNE R2,#01H,N1

55

SETB P2.1

LCALL BP

N1: CJNE R2,#02H,N2

CLR P2.1

LCALL BP

LCALL SEC

LCALL BP

N2: CJNE R2,#03H,N3

SETB P2.3

LCALL BP

N3: CJNE R2,#04H,N4

CLR P2.3

LCALL BP

LCALL SEC

LCALL BP

56

N4: CJNE R2,#05H,N5

SETB P2.5

LCALL BP

N5: CJNE R2,#06H,N6

CLR P2.5

LCALL BP

LCALL SEC

LCALL BP

N6: CJNE R2,#07H,N7

SETB P2.7

LCALL BP

N7: CJNE R2,#08H,N8

CLR P2.7

LCALL BP

57

LCALL SEC

LCALL BP

N8: CJNE R2,#09H,FDF

LCALL BP

LCALL BP

LCALL BP

WT: LJMP SA

DISC: CLR P1.6

LCALL DEL

LJMP SA

DTD:

PP:

58

MOV R7,#4FH

AEE: MOV R6,#FFH

ADE: MOV R5,#FFH

ABE:

JNB P1.4,ACE

LCALL DEL1

JNB P1.4,ABE

EDR: MOV R2,P1

CLR A

MOV A,R2

ANL A,#0FH

MOV R2,A

MOV P0,A

RET

ACE: DJNZ R5,ABE

DJNZ R6,ADE

DJNZ R7,AEE

MOV R4,#02H

RET

59

WDSUBR: MOV R7,#4FH

AE: MOV R6,#FFH

AD: MOV R5,#FFH

AB: JNB P1.4,AC

LCALL DEL1

JNB P1.4,AB

MOV R4,#01H ;STATUS CHK #01 OK,#02 NOT OK

RET

AC: DJNZ R5,AB

DJNZ R6,AD

DJNZ R7,AE

MOV R4,#02H

RET

DEL1: MOV PSW,#08H

60

MOV R6,#0FH

L1: MOV R7,#FFH

DJNZ R7,$

DJNZ R6,L1

MOV PSW,#00H

RET

DEL: MOV PSW,#08H

MOV R5,#03H

M1: MOV R6,#FFH

M2: MOV R7,#FFH

DJNZ R7,$

DJNZ R6,M2

DJNZ R5,M1

MOV PSW,#00H

RET

61

RINGCNT: MOV R7,#0AH

AE1: MOV R6,#FFH

AD1: MOV R5,#FFH

AB1: JB P1.5,AC1

LCALL DEL1

JB P1.5,AB1

MOV R4,#01H

RET

AC1: DJNZ R5,AB1

DJNZ R6,AD1

DJNZ R7,AE1

MOV R4,#02H

RET

SEC:

MOV R7,#03H

SXE1: MOV R6,#FFH

62

SXD1: MOV R5,#FFH

SXB1: DJNZ R5,SXB1

DJNZ R6,SXD1

DJNZ R7,SXE1

RET

;--------------------------------

BP:

MOV R7,#03H

SXAE1: MOV R6,#FFH

SXAD1: MOV R5,#FFH

SXAB1: DJNZ R5,SXAB1

CPL P1.7

DJNZ R6,SXAD1

DJNZ R7,SXAE1

CLR P1.7

RET

63

7.3: KIT VIEW

64

7.4: BIBILOGRAPHY.

Muhammad Ali Mazidi, Janice Gillispie Mazidi-THE 8051 MICRO

CONTROLLER AND EMBEDDED SYSTEMS-PHI-2000.

Douglas V-Hall - MICROPROCESSORS AND INTERFACING - Tata Mc Graw

Hill publishing company limited - 1999 ,2nd Edition.

A.K.Ray and Burichand - ADVANCED MICROPROCESSOR AND

PERIPHERALS - Tata Mc Graw Hill publishing company limited-2000.

William C.Y.LEE - “MOBILE CELLULAR COMMUNICATIONS” –

McGraw Hill – 1989,2nd edition.

References on the Web:

www.atmel.com

www.alldatasheets.com

www.datasheetarchive.com

www.projectguidance.com

www.wikipedia.com

65