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Programmable Logic Programmable Logic Architecture Verilog HDL Architecture Verilog HDL FPGA Design FPGA Design Jason Tseng Week 4
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Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 4.

Jan 02, 2016

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Page 1: Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 4.

Programmable Logic Architecture Programmable Logic Architecture Verilog HDL FPGA DesignVerilog HDL FPGA Design

Jason Tseng

Week 4

Page 2: Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 4.

Abstract Abstract

Today’s class:Gate level modelingExamples

Page 3: Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 4.

Gate-Level ModellingGate-Level Modelling Primitive logic gates (基本邏輯閘 ) are part of the Verilog

language. Build-in logic models (gate stands for one of the keywords): – Basic gates: and, nand, or, nor, xor, xnor (not xor) (see Fig.4-1)– Buffers and inverter gates: buf, not (see Fig. 4-2)– Three-state gates: bufif1 (buf if 1), bufif0 (buf if 0), notif1 (not

bufif1), notif0 (not bufif0) (see Fig.4-3)

• User-defined primitives (UDP) is defined as module instantiations Syntax: gate (drive_strength) #(delays) instance_name1(output,input_1,…,input_N), instance_name2(output,input_1,…,input_N);

– Instance name can be ignored.– Drive strength::=(pull-up,pull-down) defaults ::= (strong1,strong0) (see Table 3-1 for details)– Delay ::= #(rise,fall) or #rise and fall or #(rise and fall)

Page 4: Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 4.

AND3

and_out in1 in2 in3

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

1 1 1 1

Page 5: Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 4.

Or3

or_out in1 in2 in3

0 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Page 6: Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 4.

NAND2

nand_out in1 in2

1 0 0

1 0 1

1 1 0

0 1 1

Page 7: Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 4.

nor_out in1 in2

1 0 0

0 0 1

0 1 0

0 1 1

NOR2

Page 8: Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 4.

XOR

xor_out in1 in2

0 0 0

1 0 1

1 1 0

0 1 1

Page 9: Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 4.

XNOR2

XOR2

xnor_out in1 in2

1 0 0

0 0 1

0 1 0

1 1 1

Page 10: Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 4.

BUFIF1

bufif1_out in ctrl

z 0 0

0 0 1

z 1 0

1 1 1

Page 11: Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 4.

BUFIF0

bufif0_out in ctrl

0 0 0

z 0 1

1 1 0

z 1 1

Page 12: Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 4.

NOTIF1

notif1_out in ctrl

z 0 0

1 0 1

z 1 0

0 1 1

p.s.: inverse of bufif1

Page 13: Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 4.

NOTIF0

notif0_out in ctrl

1 0 0

z 0 1

0 1 0

z 1 1

p.s.: inverse of bufif0

Page 14: Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 4.

deco2_4

Page 15: Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 4.

Com1_g

1-bit Comparator

Page 16: Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 4.

Method 1: gate instantiation Method 2: bit-wise operator

2-bit Comparator (comp2_g)

Page 17: Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 4.

mux2_1g

1-bit 2-1 multiplexer

Page 18: Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 4.

Data Output from D-type Flip Flop using 2-1 Multiplexer

dff_sel

Page 19: Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 4.

mux4_1gLogic Gates

1-bit 4-1 multiplexer (method 1)

Page 20: Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 4.

mux4_1b_gbufif0 & bufif1

1-bit 4-1 multiplexer (method 2)


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