Professur für Technische Informatik A Self Distributing Virtual Machine for FPGA Multicores Klaus Waldschmidt J. W. Goethe-University Technische Informatik.

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Professur für Technische Informatik

A Self Distributing Virtual Machine for FPGA Multicores

Klaus Waldschmidt

J. W. Goethe-UniversityTechnische Informatik

Frankfurt/Main, [email protected]

Dagstuhl April 2008

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Slide 2 Klaus Waldschmidt – Dagstuhl April ’08

• One or more processors support the intelligence which is necessary for the smart behaviour.

• Things that thinkThings that think, a definition originally presented by MIT.

• Embedded systems are more a or less networked systems. In consequence an Internet of thingsInternet of things exists additionally to the wellknow Internet of information

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Embedded systems and System-on-chips

• Modern System-on-chips become more and more complex

• Time to market becomes more and more a necessity

• Robustness and trust in electronic systems is a big challenge in future

• Power reduction for mobile applicationsbecome more and more important

A parallel, flexible,

scalable, and generic

architecture will be

required in future.

A parallel, flexible,

scalable, and generic

architecture will be

required in future.

System-specification

Hardwaresynthesis

Communicationsynthesis

Software-compilation

Hardware/Software-partitioning

Environment

Reconfigurablesystem

Input Output

Observer Controller

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FPGA

Observer Controller

FPGA software model

Environment

In OutEnvironment

Reconfigurablesystem

Input Output

Observer Controller

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Multi-core FPGA (MP-SoC)Multi-core FPGAs create a new kind of system realization…

…but there are still a lot of problems to solve:

PowerManage-

ment

Reliability

Perform-ance

Flexibility

Reliability,Flexibility

and Power-Management

• Performance:Algorithms and programming (software) model

• Reliability:Increase of lifespan and robustness

• Flexibility for adaptivity and self-organization

• Power management:Energy reduction for mobility

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Autonomous and organic behaviour of multi-core computing systems

parallelcomputing

reconfigurable(dynamic)computing

adaptivecomputing

self-organization

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Multi-core Systems based on FPGA

fx

f1

f2

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Processing element (PE)

Custom HWfunction

FPGA • unite several PEs to form a parallel system

• increase number of PEs if needed

• use available space on the FPGA

• implement special functionality on the FPGA

• reconfigure at runtime

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What we need is a software model for FPGAs

to make these features manageable.

FPGA

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f3

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FP

GA

layer

The Self Distributing Virtual Machine (SDVM)

application

Core type A Core type B

The SDVM as a middleware between application and hardware

? applicationSDVMlayer

SDVM layer

Application runs transparently distributed on several sites

application

site

Application to be run on heterogeneous, distributed hardware

Network on chip (NoC) (bus, mesh, crossbar, Clos Net, …)

The SDVM is a virtualization of a parallel, adaptive, and heterogeneous cluster.

??

Sites can join and leave the cluster without disturbing the execution

SDVM

Sites can join …

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HW type X

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FP

GA

SDVM uses the dataflow principle to automatically distribute applications and datacode is needed at execution time only and thus the params are moved separatelySDVM features (virtual) global shared memory using COMA principleSDVM features distributed dynamic scheduling (work stealing principle)sites may vanish (data is pushed out before) or join (new sites automatically ask for work) at runtime

NoC (bus, mesh, crossbar, Clos Net, …)

Working principle of the SDVM

code fragments can be dynamically subsituted by configware

memory

processor reconfhardware

site

memory


site

memory


site

code

paramsparamsparamsparams

execute …

execute …

params

code

params

code

paramsparams execute …

execute …configware

shutdown!

code

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System-Virtualization using the SDVM

1. FPGAs allow for parallel systems:

• multiple hardcores

• multiple softcores

• multiple custom function units

2. FPGAs allow for heterogeneous systems:

• PowerPC hardcore

• MicroBlaze softcore

• custom function units

3. Runtime-reconfigurable FPGAs make

dynamic systems possible.

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The adapted SDVMR will act as a virtual layerfor dynamic reconfigurable Multi-Core FPGAs.

FPGA

Application

NoC

Core type AM

P R

Core type BM

P R

SDVMSDVMR

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SDVMR Objectives

1. Combine all PEs on the FPGA to create a parallel system.

2. Provide task mobility between all PEs even if they are heterogeneous.

3. Virtualize the I/O-system to enable the execution of a task on an arbitrary PE.

4. Combine the distributed memory of each PE to form a virtually shared memory.

5. Manage the reconfiguration of the FPGA.

6. Adjust the number of active PEs at runtime.

7. Hide the actual number of PEs from the application to ease programming.

8. Provide dynamic scheduling as well as code and data distribution.

These features will be providedby the SDVMR software layer.

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FPGA

Implementation architecture

SDVMR

site

NoC

SDVMR

site

• The SDVMR is implemented as software running on each core.• Each core forms an independent site of the SDVMR cluster.• Custom function units will get attached to a core.• Custom function units as independent sites are planned.

(bus, mesh, crossbar, Clos Net, …)

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P R

PowerPCHardcore

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P R

MicroBlazeSoftcore

SDVMR

site

M

P R

MicroBlazeSoftcore

fy

customfunction

unit

SDVMR

site

fy

customfunction

unit

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Partial reconfiguration

FPGA

SDVMR

site

NoC (bus, mesh, crossbar, Clos Net, …)

SDVMR

siteSDVMR

siteSDVMR

site

Custom function units can be reconfigured without changing the number of sitesReconfiguring a site:• The site to reconfigure drops out of the cluster• Some other site controls the partial reconfiguration of the FPGA• The SDVMR layer is started on the new softcore• The new site joins the cluster

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PowerPCHardcore

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customfunction

unitM

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MicroBlazeSoftcore

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MicroBlazeSoftcore

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customfunction

unitM

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Softcoretype A

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Softcoretype B

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SDVM

Test bench

Site 1

Site 3

Site 2

Site 4

Ethernet

• Each site simulates one core of the multi-core chip

• Cluster consisting of four equal Intel PCs

core 1 core 2

core 4core 3

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Another application: Energy Management – cont‘d

1. The parallelism of most applications

changes dynamically.

2. The SDVM features:

• Autonomous scaling

• Dynamic workload

distribution

• Distributed dynamic

scheduling

The dynamic scheduling and workload distribution offers newdegrees of freedom when choosing an energy management policy.

HFM OFF

OFFOFF

possible EM-state transitions due to workload variation

?HFM LFM

OFFLFM

LFM LFM

LFMLFM

HFM HFM

SLEEPOFF

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Conclusion

The SDVMR…

• is a virtualization layer for dynamic reconfigurable FPGAs

• separates the application from the number and type of cores

• exploits the parallelism and dynamic features of todays FPGAs

For further information visit the SDVM´s homepage athttp://sdvm.ti.cs.uni-frankfurt.de

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Thank you

for your attention!

Professur für Technische Informatik A Self Distributing Virtual Machine for FPGA Multicores Klaus Waldschmidt J. W. Goethe-University Technische Informatik.

Documents

pr slide

pr f3f3

pr sdvmsdvm r slide

pr f1f1 f2f2

code slide

pr core type b

fpga sdvm

pr hw type x