Compiling by hand Build Process Files: main.c foo1.c foo2.c 1) gcc main.c foo1.c foo2.c –o main 2) gcc main.c foo1.c foo2.c –c gcc main.o foo1.o foo2.o –o main With make and makefile, you only need to type make
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Makefile Tutorial CIS5027Makefile Tutorial CIS5027
What’s make?
A utility that automatically builds executable
programs and libraries from source code by reading files
called makefile which specify how to derive the target
program.
Make allows you to manage large programs and keep track of which
portion of the entire program have been changed.
Makefile tells make how to generate an execution file
make
make –f MyMakefile
make executes commands in the makefile to update one
or more target names, where name is typically a
program. If no -f option is present, make will
look for the makefiles GNUmakefile,makefile,
and Makefile, in that order.
The purpose of the make utility is to determine
automatically which pieces of a large program need to be
recompiled, and issue the commands to recompile them. The manual
describes the GNU implementation of make, which was written by
Richard Stallman and Roland McGrath. Our examples show C programs,
since they are most common, but you can use make with any
programming language whose compiler can be run with a shell
command. In fact, make is not limited to programs. You
can use it to describe any task where some files must be updated
automatically from others whenever the others change.
To prepare to use make, you must write a file called
the makefile that describes the relationships among files
in your program, and the states the commands for updating each
file. In a program, typically the executable file is updated from
object files, which are in turn made by compiling source
files.
Once a suitable makefile exists, each time you change some source
files, this simple shell command:
make
When there is more than one file to handle.
If the code is expected to be built on different machines.
There are special handling steps.
If you consider your time to be valuable.
If you expect to rebuild your executable at some later point -
the Makefile retains the memory of the needed
steps.
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gcc main.c foo1.c foo2.c –c
gcc main.o foo1.o foo2.o –o main
With make and makefile, you only need to type
make
-o <file> Place the output into <file>
GCC: GNU Compiler Collection
Referrers to all the different languages that are supported by the
GNU compiler.
gcc: GNU C Compiler g++: GNU C++
Compiler
The main differences:
gcc will compile: *.c/*.cpp files as C and C++ respectively.
g++ will compile: *.c/*.cpp files but they will all be treated as
C++ files.
Also if you use g++ to link the object files it automatically links
in the std C++ libraries (gcc does not do this).
gcc compiling C files has less predefined macros.
gcc compiling *.cpp and g++ compiling *.c/*.cpp files has a few
extra macros.
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Commands: Consider as shell script.
Please note: you need to put a tab character at the beginning
of every recipe line!
Target : dependencies(or prerequisites )
<Tab> system commands(or recipe )
If there are no dependencies for target, make will safely
executes the system commands specified.
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Dependency graph
Four entries appear in the file. Each contains a dependency
line that shows how a file is built. Thus the first line says
that project1 (the name before the colon) is built from
the three object files main.o and io.o,
data.o (the names after the colon). What this line
tells make is that it should execute the
following gcc line whenever one of those object files
change. The lines containing commands have to begin with tabs (not
spaces).
It doesn't matter what order the three entries are within the
makefile. make figures out which files depend on which
and executes all the commands in the right order.
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Change one source file
gcc main.o fool.o –o main
Changes the date/time stamp of the file filename to the current
time.
Touch”. Marks targets as up to date without actually changing them.
In other words, make pretends to update the targets but
does not really change their contents; instead only their modified
times are updated
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Variables
gcc –o foo foo.c
You can also use variables when writing Makefiles. It comes in
handy in situations where you want to change the compiler, or the
compiler options.
When people use a filename or other string more than once in a
makefile, they tend to assign it to a macro. That's simply a string
that make expands to another string.
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insert.o search.o files.o utils.o
insert.o search.o files.o utils.o
insert.o search.o files.o utils.o
Difference between :=, = and +=
x = foo y = $(x) bar x = xyz # The value of y would be xyz
bar
x := foo y := $(x) bar x := xyz # The value of y would be foo
bar
CFLAGS= -c
CFLAGS+= -Wall
In short, variables defined with := are expanded once,
but variables defined with = are expanded whenever they
are used.
+= adds the option –Wall to CFLAGS
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# bar is now ‘a,b,c’.
Functions allow you to do text processing in the makefile to
compute the files to operate on or the commands to use in recipes.
You use a function in a function call, where you give the name
of the function and some text (the arguments) for the function
to operate on. The result of the function's processing is
substituted into the makefile at the point of the call, just as a
variable might be substituted.
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