Prof. Dr. Akash Kumar - TU Dresden · Modern Computing Systems Prof. Dr. Akash Kumar Chair for Processor Design (Ack: my past and current students/PostDocs) (Some slides adapted from

Modern Computing Systems

Prof. Dr. Akash KumarChair for Processor Design

(Ack: my past and current students/PostDocs)(Some slides adapted from Koren, Krishna, Anand)

© Akash Kumar

Singapore2

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Eindhoven University of Technology3

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Gliding4

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Finished PhD!5

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Life in Singapore6

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Faculty of Engineering, NUS7

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Outreach8

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…9

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Topics to be Covered

1. Real-time Embedded Systems2. Fault-Tolerance3. Approximate computing 14. Approximate computing 25. Machine learning embedded architectures 16. Machine learning embedded architectures 27. Going beyond CMOS

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Outline

¨ Characteristics of real-time embedded systems¨ Hardware architecture for real-time embedded

systems

¨ Design flow and considerations¨ Modern challenges and solutions

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What is a real-time system?

A system which responds to events within a finite and specifiable delay in order to change its environment

y(t+Δ)

RT system x(t)Environment

Δ is finite and specifiablePredictability!!

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Why is real-time important?

*Courtesy – Rajesh Panicker

Original

Corrupt – 5%

Corrupt – 20%

Corrupt – 40%

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What is an embedded system?

¨ Small device, like a cell phone¨ Small processor installed in some other device, like

a car¨ Software that controls a consumer device¨ Real-time response

My favorite:

Any system where the user doesn’t want to know that it includes a processor

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Examples of Real time/ Embedded Systems

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¨ Mars pathfinder

¨ Car engine

¨ Mobile phone

¨ Set-top box

¨ Car navigation

¨ Industrial control

¨ Telecom switch

¨ Global Positioning System

¨ Air Traffic Management

¨ Satellite flight manager

¨ Satellite Ground Control

¨ TV receiver

¨ Flight control system

¨ Electric shaver

¨ Toaster

¨ Washing Machine

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Hardware Architectures for Embedded Systems

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History of Hardware / VLSI

¨ Vacuum tube

(Lee De Forest, 1906)

¨ ENIAC

(1946, UPenn)

¨ Transistor

(1947, Bardeen, Brattain,

Shockley)

¨ Integrated circuit

(1958, Jack Kilby)

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History of Hardware / VLSI

¨ Intel 4004

(1971, 1400 transistors)

n Intel Core i7 - Ivy Bridge (2012, >1.4 Billion transistors)

n Very Large Scale Integration (VLSI) – originally defined for chips having transistors in the order of 100,000. Other terms such as ULSI came along, but the usage VLSI remains dominant

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© Akash Kumarhttp://cpudb.stanford.edu/

Moore’s Law

n In 1965, Intel’s Gordon Moore predicted that the number of transistors that can be integrated on single chip would double about every two years

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40 Years of microprocessor trend data20

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Design Productivity Gap

¨ Increasing number of transistors makes it harder to design the system¤ Late launch of products directly hurts profits

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System Design Considerations

¨ System : sensor -> processor -> actuator¨ Considerations

¤ Technology¤ Performance¤ Power consumption¤ Volume of production¤ Upgradability / ease of maintenance¤ Reliability¤ Testability¤ Availability of CAD and software tools, IP's, hardware and

software libraries¤ Cost, chip area¤ Legal and certification requirements, client specifications¤ …..

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Digital Hardware Market Segments

n Processor, GPU

n DRAM, Flash memories

n (Co-)Processor alternativesn ASIC (application specific integrated circuit)n ASSP (application specific standard product) n FPGA (field programmable gate array)

n Convergence as System on Chip (SoC), which may also contain analog, mixed-signal, and radio-frequency functions

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Embedded systems architecture

¨ Trend towards Multi-Processor Systems-on-chip (MPSoC)

¨ Homogeneous vs heterogeneous systems¨ Different memory models¨ Different network architectures

¤ Network-on-chip¤ Buses

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Processor 4 Processor 5

Interconnection network

Processor 1 Processor 2 Processor 3

Memory Memory Memory

Memory Memory

Homogeneous vs heterogeneous25

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Homogeneous vs heterogeneous

¨ Heterogeneity is increasing¤ Different levels of parallelism in application¤ uProc – better for control-flow¤ DSP – better for signal processing¤ Dedicated hardware blocks needed for certain parts¤ Improves efficiency and saves power

¨ Homogeneous systems ¤ Better for fault-tolerance¤ Only one compiled version of any application needed¤ Easier to design and replicate¤ Easy to support task migration

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Memory usage27

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Memory Memory

Embedded systems – local memory28

Local memory is better for more predictability Network/ bus delay may be unpredictable

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Embedded systems – global memory

Processor 4 Processor 5 Memory



Arbiter

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Global memory may be better for shared data

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Memory Memory

Embedded systems – combination

Memory

Arbiter

Can also be off-chip!

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Communication pattern also determines which architecture is betterMessage passing OR Shared memory

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Embedded systems – network

Processor 4 Input/ Output Memory



Arbiter

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Interconnection network-on-chip



Arbiter

NININI

NI NI

NI

RouterRouter Router

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Interconnection network – bus


High speed bus


Arbiter

Arbiter

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Point-to-point networks



Arbiter

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System Design – Hw/Sw Codesign

¨ Take decisions on whether to implement in hardware or software¤ Consider the advantages vs costs

¨ If hardware, whether to use commercial off the shelf (COTS) components or custom components

System Level Specification

SoftwareModel

Hardware/Software

Partitioning

HardwareModel

Co-simulation

Compilation Synthesis

Integrationand Testing

Resources

Performance-1

Pareto Curve

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A

BC

D

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Modern Challenges

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Modern Multimedia Embedded Systems

Large number of use-cases

Guarantee performance

Minimize power consumption

Run-time addition of appl

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Issues and Modern Trends

¨ The communication bottleneck¤ 3D Chips¤ Optical interconnects

¨ Leakage current limiting size reduction¤ Multi-gate or gate-all-around transistors (Intel 22nm

uses 3D/tri-gate transistors)¤ Channel strain engineering, silicon-on-insulator-based

technologies, and high-k/metal gate materials

¨ One may not fit all¤ Hardware/Software Co-design¤ Fault-tolerant / reconfigurable computing

¨ Power issues¤ Multi-core and heterogeneous architectures

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¨ Dennard scaling principles [1]

Technology Scaling

[1] R. Dennard et al. “Design of Ion-Implanted MOSFET’s with Very Small Physical Dimensions,” IEEE Journal of Solid-State Circuits, 1974.

Device Parameters Scaling Factor

Device dimension 1/k

Doping concentration 1/k

Voltage 1/k

Current 1/k

Capacitance 1/k

Delay time per circuit 1/k

Power dissipation 1/k2

Area 1/k2

Power density 1

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¨ Digression from Dennard’s scaling beyond 65nm¤ Non-ideal voltage scaling: limit on threshold voltage scaling¤ Non-ideal gate oxide scaling

¤ Sub-threshold leakage power

¨ Power dissipation increases with technology scaling¤ Heat localization (hot spots)

¤ Higher temperature => device wear-out

Technology Scaling40

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Technology Scaling and Power Density

Hot Plate

Nuclear Reactor

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Technology Scaling and Power Density

Manufacturing defects(e.g. Imperfect Lithographic

patterning)

Transistor Scaling

Increased Variability(e.g. Random Dopant

Fluctuation)

Increasing Power Density

Increase T

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Approximate Computing

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20 W20 W

~200000 W

The Computational Efficiency Gap

IBM Watson playing Jeopardy, 2011

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Humans Approximate

923 = - - .- -?21

is 923 >1.75?21

is 923 > 45?21

Task:Division

Application context dictates required accuracy of results

Accuracy

21) 923 (43848363

Effort expended increases with required accuracy

~1Petaflop/W

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But Computers DO NOT

float x = 923;float y = 21;cout << (x/y > 45.0) ?“YES”:”NO”;

NO92321 >45

923> 1.7521

float x = 923;float y = 21;cout << (x/y > 1.75) ?“YES”:”NO”;

YES

But, I workedharder than needed

} Overkill (for many applications)

} Leads to inefficiency} Can computers be more efficient by producing “just good enough” results?

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Intrinsic Application Resilience: Sources

IntrinsicApplicationResilience

‘Noisy’ RealWorld Inputs

Redundant Input Data

Perceptual Limitations

Statistical Probabilistic

Computations

Self-Healing

Compute distances& assign points to clusters

Update clustermeans

Repeat until convergence

} Intrinsic application resilience:Ability to produce acceptable outputs despite underlying computations being performed in an approximate manner

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Machine Learning

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What's Deep Learning/ Deep Neural Network?

¨ Self learning algorithms¨ Using huge data sets to learn¨ Deep: many "learning layers"¨ Brain inspired, based on neurons and synapses

(connections)¨ High classification accuracy¨ Many applications; let's look at ImageNet

classification and Tesla Autopilot

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ImageNet Winners (top-5 classification error)

¨ ImageNet dataset: 10M images, 10000 classes

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0%

5%

10%

15%

20%

25%

30%

2010 2011 2012 2013 2014 2015 2016 2017

top-

5 er

ror

Traditional methods Deep Learning Human

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AI: Tesla Autopilot

¨ Tesla Model S demonstration of autonomous driving¨ Computing system monitors radar and several

cameras¤ Detect objects like cars, and pedestrians¤ Monitor traffic signs¤ Lane tracking and possible lane changing¤ Auto parking

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Tesla web page: www.tesla.com/videos/ November 2016

http://www.tesla.com/videos/

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Deep Learning and High-performance HW Architectures

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Beyond CMOS

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Classical CMOS Transistors54

PMOS on topNMOS at bottom

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Reconfigurable Transistors:Silicon Nanowires Based Reconfigurable FETs

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SiNW Dual-gate RFETs: Combines p-type and n-type functionality

Runtimereconfigurability

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Conclusions

¨ Characteristics of real-time embedded systems

¨ Hardware architectures and considerations

¨ Modern trends and challenges

¨ Fault-tolerance a major problem in modern systems

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Ongoing Research Activities

Reliability/Energy Optimization• Reconfigurable approximate computing at run-time• Optimize energy and reliability• Minimize thermal cycling and peak temperature• Task remapping and scheduling for dealing with faults

Processing Architecture Design• Determine and design appropriate system architecture• Design predictable components – network and communication assist• Partially reconfigurable tile-based heterogeneous multiprocessor systems• Task-migration module in hardware for predictable delay

Low-Power and Fault-Tolerant FPGA Designs• Improving fault-tolerance of FPGA through LUT content manipulation• Novel error-correction mechanisms for FPGAs• Leakage-aware resource management techniques• Electronic Design Automation – Place and Route for FPGAs

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Chair for Processor Design59

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Questions and Answers

Email: [email protected]

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Prof. Dr. Akash Kumar - TU Dresden · Modern Computing Systems Prof. Dr. Akash Kumar Chair for Processor Design (Ack: my past and current students/PostDocs) (Some slides adapted from

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