Process Technological Analysis for Dynamic Characteristic ...

Abstract— In this work, we study dynamic characteristic of

digital CMOS circuits of 16-nm HKMG bulk FinFET devices by optimizing fabrication windows of inline parameters. Key process parameters are ranked according to integrated circuit quiescent current (IDDQ) and delay of ring oscillators. IDDQ and delay are affected by the dual gate-spacer, the source/drain (S/D) proximity, the S/D depth, and the S/D implant. Dependencies of operational frequency and IDDQ on the on-state current ratio of N/P FinFET devices are examined. By replacing dual spacers with single ones will improve the uniformity of implantation; consequently, the variation of IDDQ can be reduced from 252 to 37 nA significantly.

Index Terms— Inline process parameters, Bulk FinFETs, Ring

oscillators, Frequency, Integrated circuit quiescent current.

I. INTRODUCTION

Three-dimensional structure of bulk Fin-typed field effect transistor (FinFET) has been of a key device for 16-nm nodes. Scaled feature size leads to serious characteristic degradation and fluctuation of devices [1-6]. There are many sources of variation that govern uncertainty of devices and circuits. To master major reasons of variability, it has been necessary for device and process engineers to explore various process parameters [7-9]. Bulk FinFET processes are coupled because of the current process will impact next ones; however, interactions of inline processes have not been explored yet.

It will be urgent to explore FinFET, inline process, and characteristic fluctuation for sub-16-nm technological nodes.

II. DEVICE AND PROCESS DEPENDENCY ANALYSIS Based on various cross-sectional views of TEM, Fig. 1

shows a constructed 3D FinFET. Figures 1(a) and (b) are the two cross-sectional TEM images of fabricated HKMG bulk FinFET with the selective epitaxial growth (SEG) connected by the contact. Figure 1(c) is the generated 3D structure illustrating key physical parameters of HKMG bulk FinFETs; it is corresponding to the TEM image of Fig. 1(a). Figure 1(d) is the associated structure for the TEM image in Fig. 1(b); furthermore, the related 2D structure of Fig. 1(e) clearly shows the existence of key physical parameters of HKMG bulk FinFET with SEG. The entire 3D structure of Fig. 1(f) displays key parameters of the overlap area of gate-to-S/D of HKMG

This work was supported in part by Ministry of Science and Technology, Taiwan under Contracts No. MOST-103-2221-E-009-180 and No. MOST-104- 2221-E-009-114 and by tsmc, Hsinchu, Taiwan under a grant.

P.-H. Su and Y. Li are with Parallel and Scientific Computing Laboratory, Institute of Communications Engineering, Department of Electrical and Computer Engineering, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan. (e-mail: [email protected])

bulk FinFET with SEG. Figure 1(g) plots the effective capacitance (Ceff) and effective resistance (Reff) of the explored ring oscillator (RO) fluctuated by key inline process parameters. Figure 1(h) lists key inline process parameters by the sequence of the process flow, corresponding to Figs. 1(c)-(e). We explore key inline process parameters, as shown in Fig. 1, through a 101-stage RO using 16-nm HKMG bulk FinFET devices [10-12]. Key inline process parameters are sensitive to the variability of RO’s IDDQ and delay. We examine the on-state current (Id,sat) ratio of N-type FinFET (abbreviated as NFET) to PFET devices (denoted as N/P ratio). Fluctuations of RO’s IDDQ and delay versus the N/P ratio are examined.

To find out the common source of variations, we perform data mining for inline process parameters of NFET and PFET. By tuning the common process, we can minimize the variation of on-state current for all devices; thus, the fluctuation of RO can be suppressed. To measure the speed of a process, RO consisting of an odd number of inverters connected in series to form a closed loop with positive feedback is examined. Various studies adopted RO for device modeling and process variability control [11-13]. We perform a reduction for the characteristic fluctuation of RO with inline process variation control. We design a 101-stage RO with 100 identical inverters and a NAND2 with fan out of one at each stage. For a RO, the integrated circuit active current (IDDA) is the on-state AC current and IDDQ is the off-state leakage current. When the enable is assigned to “1”, the RO is turned on and both IDDA and frequency are measured. When the enable is assigned to “0”, RO is off and IDDQ is measured. The current drive per stage Idrive = IDDA-IDDQ, which means no on-state AC current, except DC leakage. Reff = Vdd/2Idrive is the effective switching resistance per stage, where Vdd is the supply voltage of RO. By expressing delay as a time constant of RC, the effective switching capacitance per stage is Ceff = d/Reff = 2d(IDDA- IDDQ)/Vdd. The ring delay (d) per stage is the inverse of the frequency of oscillation f.

III. RESULTS AND DISCUSSION Figures 2(a)-(h) shows the IDDQ is significantly fluctuated

by inline process parameters. As shown in Fig. 2(a), IDDQ is positive nonlinear function of the effective-gate width because of the leakage passed through drain area to source area. Larger effective gate width means larger S/D area and more leakage. As shown in Fig. 2(b), IDDQ is positive nonlinear function of the top fin angle due to the doping density in a high-κ metal gate. After fin substrate implant, random dopant fluctuation exists in the trapezoidal bulk FinFET. When the fin top angle becomes small, more dopants accumulate in the surface of fin top. It causes the less leakage due to the higher doping density.

Process Technological Analysis for Dynamic Characteristic Improvement of 16-nm HKMG Bulk FinFET CMOS Circuits

Ping-Hsun Su, Student Member, IEEE and Yiming Li, Member IEEE

Proceedings of the 16th International Conference on NanotechnologySendai, Japan, August 22-25, 2016

978-1-5090-3914-2/16/$31.00 ©2016 IEEE 812

θa

bc

dFin

Gate

k

Channel

Fin

SiGe SiP

Fin

Contact ContactGate

HKMGSpacer

i

(a)

(b)

(c)

(d) (e)

(g) (h)

Ceff

Fin

Reff

(f)

Process Flow:1.Fin formation2.Dummy gate

3.S/D Implantation4.S/D EPI growth5.Gate replacement

6.Hi-K/Metal Gate7.S/D Contact8.BEOL

Process Step Physical Dimension Code1. Fin formation Top-Fin Width a

Bottom-Fin Width bFin Height cTop-Fin Corner Angle q

2. Gate spacer, SD implant, and SD etching

Gate Length dGate-Spacer-1 Thickness e1Gate-Spacer-2 Thickness e2Single Gate-Spacer Thickness e3

3. S/D SEG S/D Proximity fS/D Depth gS/D Epi-Overgrowth Height hLateral S/D SEG Width i

4. HKMG HK/IL Thickness jGate Height k

kj

e1e2

gh

f f

Fin

LDDEpi

e3

Figure 1. TEM of (a) fin and contact and (b) SEG, HKMG, and contact. (c) 3D FinFET structure for the lateral NFET/PFET SEG in S/D regions, contact, and HKMG. (d) 3D FinFET structure for HKMG. (e) 2D FinFET structure for gate-spacer, SEG in S/D regions and HKMG. (f) FinFET structure for the overlap area of gate to S/D region. (g) FinFET structure for RO’s effective capacitance (Ceff) and effective resistance (Reff). (h) List of key inline process parameters.

As an etch stop layer, nitride spacers are popular ways in modern FinFET process flow. The spacer is demanded for blocking implants at the gate edge and preventing silicide shorts to the gate. As the spacer becomes thicker, the implant becomes farther to channel. Since the raised S/D is highly doped, the leakage becomes less when the raised S/D proximity become large for NFETs. The other reason is that more oxidation goes through the interface of IL/HK when the gate space becomes thicker. More oxidation in the interface of IL/HK induces the less leakage. Figures 2(c) and 2(e) show IDDQ is negative nonlinear function of the S/D proximity and the thickness of gate-spacer-2. IDDQ increases when the S/D depth increases, as shown in Fig. 2(d). Figure 2(f) shows IDDQ is negative nonlinear function of the gate length due to short channel effect. As shown in Fig. 2(g), IDDQ is negative nonlinear function of the thickness of IL/HK due to leakage. Fig. 2(h) shows IDDQ is positive nonlinear function of the gate height because the resistance of metal gate is lower than the resistance of the contact.

Figures 3(a)-(h) shows the delay is significantly fluctuated by inline process parameters. Figure 3(a) shows delay is negatively proportional to the effective gate because the larger effective width has more current. Figure 3(b) shows delay is negatively proportional to the top fin angle because the doping appears in a high-κ metal gate. Figure 3(c) shows delay is positively proportional to the SD proximity due to the distance from drain to source. Figure 3(d) shows delay is negatively proportional to SD depth because the deeper SD has more current. Figure 3(e) shows delay is positively proportional to

the thickness of gate-space-1 because the gate-spacer-1 impacts on SD proximity and SD depth. Figure 3(f) shows delay is positively proportional to the gate length according to the expression of Id,sat. Figure 3(g) shows delay is positively proportional to the thickness of IL/HK due to leakage from metal-gate to channel. Figure 3(h) shows delay is negatively proportional to the gate height because the resistance of metal gate is lower than the resistance of the contact.

Furthermore, the N/P ratio plays an important role to reduce characteristic fluctuation of RO. Figure 4(a) shows IDDQ increases nonlinearly as the frequency increases. IDDQ is 7-times higher than its per-specific designing target in the regime of fast-fast. Figure 4(b) shows IDDQ nonlinearly increases in the regime of fast-fast when the N/P ratio increases. It can be explained by Figs. Figure 5(a) shows NFET has higher Id,sat for most center dies; however, PFET has higher Id,sat for few center dies. Thus, it results in higher N/P ratio for most center dies; especially, for the regime of fast-fast. Figure 5(b) shows Id,sat of NFET and PFET in the center-zone is higher than that in the middle-zone, and in the middle-zone is higher than that in the edge-zone. Figure 6(a) shows that when the N/P ratio is smaller than 1, IDDQ linearly increases as the N/P ratio increases; however, when the N/P ratio is equal or larger than 1, IDDQ quickly increases as N/P ratio increases. Figure 6(b) shows when the N/P ratio is smaller than 1, the frequency linearly increases as the N/P ratio increases; however, when the N/P ratio is equal or larger than 1, the frequency becomes flat as the N/P ratio increases. Consequently, the unbalance of N/P ratio governs IDDQ and frequency, as discussed in Fig. 4.

813

Effctive Gate Width (nm)76 78 80 82 84 86 88

IDD

Q (n

A/st

age)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Gate Height (nm)28 29 30 31 32 33

IDD

Q (n

A/st

age)

02468

1012141618

High-K IL Thickness (nm)25.2 25.4 25.6 25.8 26.0 26.2

IDD

Q (n

A/st

age)

0.0

0.5

1.0

1.5

2.0

2.5

3.0Gate Length (nm)

24.0 24.2 24.4 24.6 24.8 25.0 25.2 25.4 25.6 25.8

IDD

Q (n

A/st

age)

0

2

4

6

8

10

12

Gate-Spacer-1 Thickness (nm)11.5 11.6 11.7 11.8 11.9 12.0 12.1 12.2

IDD

Q (n

A/st

age)

0.0

0.5

1.0

1.5

2.0

2.5

3.0SD Depth (nm)

39.5 40.0 40.5 41.0 41.5 42.0 42.5 43.0 43.5

IDD

Q (n

A/st

age)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

SD Proximity (nm)8.4 8.6 8.8 9.0 9.2 9.4 9.6 9.8 10.0 10.2

IDD

Q (n

A/st

age)

0.0

0.5

1.0

1.5

2.0

2.5

3.0Top Fin angle (degree)

94.70 94.75 94.80 94.85 94.90 94.95 95.00 95.05

IDD

Q (n

A/st

age)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

(f)

(g)(h)

(e)

(b)(a)

(c) (d)

Figure 2. Plots of IDDQ versus (a) the effective gate width; (b) the top-fin angle; (c) the S/D proximity; (d) the S/D depth; (e) the gate-space-1 thickness; (f) the gate length; (g) IL High-k thickness; (h) the gate height.

High-K IL Thickness (nm)25.2 25.4 25.6 25.8 26.0 26.2

Del

ay (p

s/st

age)

13

14

15

16

17

18

Gate Height (nm)28 29 30 31 32 33

Del

ay (p

s/st

age)

13

14

15

16

17

18Gate-Spacer-1 Thickness (nm)

11.5 11.6 11.7 11.8 11.9 12.0 12.1 12.2

Del

ay (p

s/st

age)

12

13

14

15

16

17

18

Gate Length (nm)24.0 24.2 24.4 24.6 24.8 25.0 25.2 25.4 25.6 25.8

Del

ay (p

s/st

age)

13

14

15

16

17

18SD Proximity (nm)

8.4 8.6 8.8 9.0 9.2 9.4 9.6 9.8 10.0 10.2

Del

ay (p

s/st

age)

13

14

15

16

17

18

SD Depth (nm)39.5 40.0 40.5 41.0 41.5 42.0 42.5 43.0 43.5

Del

ay (p

s/st

age)

13

14

15

16

17

18Effctive Gate Width (nm)

76 78 80 82 84 86 88

Del

ay (p

s/st

age)

12

13

14

15

16

17

18

Top Fin angle (degree)94.70 94.75 94.80 94.85 94.90 94.95 95.00 95.05

Del

ay (p

s/st

age)

13

14

15

16

17

18

(f)

(g) (h)

(e)

(b)(a)

(c) (d)

Figure 3. Plots of the delay versus (a) the effective gate width; (b) the top-fin angle; (c) the S/D proximity; (d) the S/D depth; (e) the gate-space-1 thickness; (f) the gate length; (g) IL High-k thickness; (h) the gate height.

Frequency (MHz)

IDD

Q (n

A)

IDD

Q (n

A)

Frequency (MHz)

N/P RatioMax (1.2)Min (0.67)

(a)

(b)

Nominal- Nominal Fast-Fast

Nominal- Nominal Fast-Fast

7 times

ZoneCenterEdgeMiddleNew Process Scheme

CornerFF (Target)NN (Target)

IDDQ = 252 nA

IDDQ = 37 nA

CornerFFNN

Figure 4. (a) Scatter plot of IDDQ vs. frequency. IDDQ exponentially increases as the frequency increases; especially, in Fast-Fast corner. Zones in the center, middle, and edge are quite different. (b) Scatter plot of IDDQ vs. frequency. N/P Id,sat ratio is marked by colors. Extremely high IDDQ and high frequency are relative to N/P Id,sat ratio.

Hence, inline process parameters should be optimized for both N/P FETs to reduce the variation of Id,sat. The gate-spacer is a variation source for both N/P FETs. It is one of their common processes, so the gate-spacer thickness is a key in-line process parameter to affect the N/P ratio. Changing the dual-spacer to a single one, the uniformity of implantation can be improved and the fluctuation of IDDQ is thus reduced. The examined circuit finally reaches its designing target.

IV. CONCLUSIONS In summary, we have studied and ranked key inline process

parameters for digital CMOS circuits using 16-nm HKMG FinFET devices. Dual gate-spacer is relevant to S/D proximity, depth, and implant, which plays a significant variation source of process parameters. The N/P Id,sat ratio is not a inline process parameter, but it affects frequency and IDDQ of the explored digital circuit. By replacing dual spacers with single spacers, we can obtain better control of S/D implant and can achieve about 7-times fluctuation reduction of IDDQ.

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814

I d,sa

t(P

FET)

Id,sat (NFET)

(a)

(b)

(I) (II) (III)

Id,sat (Fast-Fast)

(I’) (II’) (III’)

Id,sat (Nominal-Nominal)

NFET(mA/um)

NFET/PFET

NFET/PFET

Max: 990 Min: 582

ZoneCenterEdgeMiddle

CornerFF (Target)NN (Target)

NFET(mA/um)

PFET (mA/um)

PFET (mA/um)

Figure 5. (a) Plot of Fast-Fast wafer map for (i) Higher NFET Id,sat is in the wafer center. (ii) Higher PFET Id,sat is in few dies of wafer center. (iii) Higher N/P Id,sat ratio is in the wafer center. Nominal-Nominal wafer map for (i’) Higher NFET Id,sat is in the wafer center. (ii’) PFET Id,sat has no special wafer pattern. (iii’) Higher N/P Id,sat ratio is in the wafer center. (b) Variations are very different in zones of the center, middle, and edge, respecticely.

N/P Ratio

IDD

Q (n

A)

Freq

uenc

y (M

Hz)

N/P Ratio

(a)

(b)

N/P Ratio < 1

N/P Ratio > 1

N/P Ratio < 1

N/P Ratio > 1Corner

FFNN

CornerFFNN

ZoneCenterEdgeMiddle

ZoneCenterEdgeMiddle

Figure 6. (a) Plot of IDDQ vs. N/P ratio. IDDQ increases exponentially as N/P Id,sat ratio > 1. When the N/P ratio < 1, IDDQ linearly increases as the N/P ratio increases (b) Frequency vs. N/P ratio. When the N/P ratio < 1, frequency linearly increases as the N/P ratio increases; however, when the N/P ratio is equal or larger than 1, frequency becomes flat as the N/P ratio increases.

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