Software Engineering Software Engineering Methodology for Methodology for Reconfigurable Reconfigurable Platforms Platforms Damien Picard and Loic Lagadec Architectures et Systèmes, Lab-STICC Université de Bretagne Occidentale, France ESUG’09 Brest, France, 2009
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
Software Engineering Software Engineering Methodology for Methodology for Reconfigurable PlatformsReconfigurable Platforms
Damien Picard and Loic Lagadec Architectures et Systèmes, Lab-STICC
Université de Bretagne Occidentale, France
ESUG’09Brest, France, 2009
2D. Picard, L. Lagadec ESUG’09 - Brest
IntroductionIntroduction Increasing complexity of modern System-on-Chip
Difficulty to program and to validate applications Shrinking time-to-market
Common techniques for hardware validation Testing/debugging at a very low abstraction level
Time-consuming and burdensome
Need for productive methodologies with an higher level approach Software development benefits from very efficient
Aim of this talkAim of this talk This talk focuses on a key issue: validation of
hardware application targeting RA
An HL synthesis flow for reconfigurable architectures based on MADEO [ESUG 08]
Multi-level simulation: from behavioral to hardware Interfacing with third-party tools through code generation Software-like debugging features embedded in hardware
Advocates for the use of software engineering techniques Short development cycles, use of OO models, code
generation, etc.
4D. Picard, L. Lagadec ESUG’09 - Brest
OutlineOutline1. Overview of Reconfigurable Architectures
2. OO methodology for synthesis on RA
3. Simulation and testing methodology
4. Software-like debugging for RA
5. Conclusion
5D. Picard, L. Lagadec ESUG’09 - Brest
OutlineOutline1. Overview of Reconfigurable Architectures
2. OO methodology for synthesis on RA
3. Simulation and testing methodology
4. Software-like debugging for RA
5. Conclusion
6D. Picard, L. Lagadec ESUG’09 - Brest
Reconfigurable ArchitecturesReconfigurable Architectures A reconfigurable architecture is a run-time programmable
architecture based on the hardware reconfiguration
Used as flexible hardware accelerators for intensive computations Based on Look-Up-Table (LUT) = memory General-purpose and high parallelism Slow and area/power-inefficient (routing overhead)
Several reconfigurable platforms FPGAs (vendors, e.g. Xilinx, Altera) eFPGAs (e.g. M2000, Menta) RSoCs (e.g. Morpheus project): RA IP composition
QuickTime™ et undécompresseur TIFF (non compressé)
sont requis pour visionner cette image.
7D. Picard, L. Lagadec ESUG’09 - Brest
Reconfigurable Architectures
Trade-off between flexibility/performance Functionality of the circuit determined by a
configuration
Flexibility Performance
Processor Reconfigurable Architecture ASIC
Results
DataProgram Configuration Data Data
Results Results
8D. Picard, L. Lagadec ESUG’09 - Brest
Reconfigurable Architectures FPGA: a general overview
Organized as a mesh of look-up-tables Possibly heterogeneous
Computingresource
Programmableinterconnection
I1+i2i1
i2
LUT LUT
LUT
LUTLUTLUT
LUT
+
-
i1
i2I1-i2
LUT
LUT IO
µP
I1*i2i1
i2
*
9D. Picard, L. Lagadec ESUG’09 - Brest
OutlineOutline1. Overview of Reconfigurable Architectures
2. OO methodology for synthesis on RA
3. Simulation and testing methodology
4. Software-like debugging for RA
5. Conclusion
10D. Picard, L. Lagadec ESUG’09 - Brest
The MADEO frameworkThe MADEO framework Loic Lagadec’s talk: “MADEO: A CAD Tool for
Reconfigurable Hardware” [ESUG 08]
MADEO is a generic synthesis framework for RA Set of open tools designed with OO principles for fast
evolution Enables design-space exploration
Application of OO methodology for synthesizing circuits Flexibility through generic OO model with a common API Adapt to new RA “retargetable compiler” Produce circuits from HL pure OO code: Smalltalk
A complete implementationA complete implementation
QuickTime™ et undécompresseur TIFF (non compressé)
sont requis pour visionner cette image.
13D. Picard, L. Lagadec ESUG’09 - Brest
The MADEO frameworkThe MADEO framework Software-engineering concepts applied to logic
synthesis on reconfigurable architectures
MADEO: extensive use of OO methodology Modeling, generic tools through polymorphism
An HL synthesis flow for RSoC based on the MADEO approach with validation methodology Multi-level simulation: from behavioral to hardware Target modeling Interfacing with third-party tools through code generation Software-like debugging features embedded in hardware
14D. Picard, L. Lagadec ESUG’09 - Brest
OutlineOutline1. Overview of Reconfigurable Architectures
2. OO methodology for synthesis on RA
3. Simulation and testing methodology
4. Software-like debugging for RA
5. Conclusion
15D. Picard, L. Lagadec ESUG’09 - Brest
Global FlowGlobal FlowSmalltalkMethod
High-levelCDFG
Low-levelCDFG
SoC Model
Multi-LevelSimulator
ExportTesting
Netlist
Back-endTools
SystemSimulator
Global Simulation
System BehaviorGantt Diagram
Interaction Diagram
Application BehaviorWaveform
ComponentsFramework
Debugging
Iterations
SynthesisCDFG
16D. Picard, L. Lagadec ESUG’09 - Brest
Platypus tool
CDFG designCDFG design
CDFG EXPRESS
model
Tool X
Tool YHLL CDFG API (Java)
CDFG instances(STEP files)
CDFG Checker
Madeo+ synthesis tool
CDFG UseCDFG Use
Target 3
Specific Assembly code
Target 2
C like code
Target 1
EDIF
Target architecture description
HLL CDFG API (Smalltalk)
ENTITY HierarchicalNode SUBTYPE OF (Node);localVariables : LIST OF AbstractData;subOperators : LIST [1 : ?] OF Node;
END_ENTITY;
ENTITY AccumulatorNode SUBTYPE OF (HierarchicalNode);init : AbstractData; --”AccumulatorNode.init” the initial value we start accumulating from.toBeAccumulated: AbstractData;
DERIVEcumulatedArguments : LIST OF AbstractData := subOperators [ SIZEOF (subOperators)].outputs;
Stimuli on LL-CDFG signal interface defined in a method of the accelerator component
Interface between the system and accelerated function
Tracing values for LL-CDFG simulation Simulator defines an API to set probes on the LL-CDFG
signal interface Tracing of the signal values Graph generation
28D. Picard, L. Lagadec ESUG’09 - Brest
Tracing signalsTracing signals Traced signals and stimuli set through a GUI
29D. Picard, L. Lagadec ESUG’09 - Brest
LL-CDFG simulationLL-CDFG simulation Traces produced from signals
Values tested against expected results: SUnit testing
30D. Picard, L. Lagadec ESUG’09 - Brest
Testing methodology: SUnitTesting methodology: SUnit Unit test for synthesis result
Characterization test between two simulations test2 CDFGSynthesisAPI new example: 'example.step' family: 'F4' primitives: true. res := self readResult. CDFGSynthesisAPI new example: 'example.step' family: 'F4' primitives: false. res2 := self readResult. self assert: res = res2
Generated HDL (Verilog)Generated HDL (Verilog) Stopping the simulation
Triggering a signal on change
Looks shorter but is missing: signal declarations, module declarations, interconnections and other LL details ST coding + generation enable to save 50% of the designer’s coding effort
initial begin @(posedge done); - - HALT $stopend
always @(posedge dma_ack_read) begin #(PERIOD * 10) dma_ack_read = 0;end
37D. Picard, L. Lagadec ESUG’09 - Brest
Simulation by third party toolsSimulation by third party tools Link: signal/LUT names LL-CDFG HL-CDFG
Enables to go back to the highest abstraction level
Modelsim (Mentor Graphics)
38D. Picard, L. Lagadec ESUG’09 - Brest
OutlineOutline1. Overview of Reconfigurable Architectures
2. OO methodology for synthesis on RA
3. Simulation and testing methodology
4. Software-like debugging for RA
5. Conclusion
39D. Picard, L. Lagadec ESUG’09 - Brest
After Testing FailedAfter Testing Failed Multi-level simulation enables to test the application
at any flow stage
Use software engineering techniques Testing at all level with SUnit Modeling approach with generic models
Platform , application, interactions
Interfacing with third-party tools Automated code generation
If validation failed… …Time for debugging
Testing
Debugging
40D. Picard, L. Lagadec ESUG’09 - Brest
Debugging and exploration facilitiesDebugging and exploration facilities Example: Visualworks’ debugger
41D. Picard, L. Lagadec ESUG’09 - Brest
Methods and Tools for Software DebuggingMethods and Tools for Software Debugging
Debugging facilities in Smalltalk environment Conditional breakpoint and watchpoint inserted/modified
dynamically Hot-code replacement Deep exploration of the execution context Message stack control
Short iterative cycles: edit-compile-run-debug Fast development
These software features do not exist in hardware No symbolic debugging, no execution stack, etc.
QuickTime™ et undécompresseur TIFF (non compressé)
sont requis pour visionner cette image.
42D. Picard, L. Lagadec ESUG’09 - Brest
Debugging HardwareDebugging Hardware Common hardware debugging methodology for RA
Hardware simulation, embedded logic analyzer… Powerful tools but debugging is performed at hardware level
Trade-off performance/complexity exposed to the designer
Complexity
SystemC
ModelSimHDL
ELA
Software
Trade-off
Hardware
Performance
43D. Picard, L. Lagadec ESUG’09 - Brest
From Software to Hardware DebuggingFrom Software to Hardware Debugging Reconfigurable circuits can support the main
advantages of software engineering methodology A bridge between software and hardware world
Reconfigurability enables to re-used the circuit Possibility to iterate on a design edit-compile-run ~ edit-synthesize/configure-run Synthesis is time-consuming
Debugging the application in-situ with a specific interface
Gain in performance
44D. Picard, L. Lagadec ESUG’09 - Brest
Global FlowGlobal FlowSmalltalkMethod
High-levelCDFG
Low-levelCDFG
Multi-LevelSimulatorExport
Probed Netlist
Synthesis
ProbeInsertion
ReconfigurableArchitecture
45D. Picard, L. Lagadec ESUG’09 - Brest
Probing Hardware : PrinciplesProbing Hardware : Principles From software to hardware probes
Watchpoints and breakpoints concepts
Controllability over hardware execution Software debugger features added to hardware application
Benefit from reconfigurability Debugging support automatically inserted by the design
framework (probes + controller) All debugging features removed once design is validated
46D. Picard, L. Lagadec ESUG’09 - Brest
Probing signalsProbing signals Breakpoints set through a GUI
47D. Picard, L. Lagadec ESUG’09 - Brest
Embedding software debugger featuresEmbedding software debugger features Execution is controlled by the debugger
Breakpoints interfaced with a debug controller
OpOp
Op
Op
Op
Op
Op
Op
Synthesis
Debugctrler
Simulator
Schedulecontroller
Control interface
Control interface
48D. Picard, L. Lagadec ESUG’09 - Brest
Hardwired BreakpointHardwired Breakpoint Freeze the execution when triggered
Limit on conditional operators Hierarchical low-level CDFG
Pool of probed signals is static Breakpoint condition are configurable and can be enabled/disabled Possibility to speculate and to backtrack execution No-need for re-synthesis
Configuration structure 2-D vector Configuration word: contains operator selection, activation status and
arguments
Extraction of the debug information: two execution modes Running mode Debug mode
Execution control: step-by-step, resume Read back of the debugging information
50D. Picard, L. Lagadec ESUG’09 - Brest
Hardwired WatchpointHardwired Watchpoint Probed signals are wired to the top interface
Automatically crosses the hierarchies Possibly conditional Trace analysis
Hierarchical low-level CDFG
TopHier1
Hier2
Op
Probed signal
51D. Picard, L. Lagadec ESUG’09 - Brest
ExampleExample
Execution Frozen
52D. Picard, L. Lagadec ESUG’09 - Brest
OutlineOutline1. Overview of Reconfigurable Architectures
2. OO methodology for synthesis on RA
3. Simulation and testing methodology
4. Software-like debugging for RA
5. Conclusion
53D. Picard, L. Lagadec ESUG’09 - Brest
ConclusionConclusion Methodology for validating an application running on a
RSoC Multi-level simulation of the application specified as CDFG High-level modeling of platform by a component-based approach
Benefit from software expertise for hardware design Taking advantage of the Smalltalk dynamic language and
environment Debugging techniques from software to hardware Short cycle and iterative developments
Future workFuture work Dynamic insertion of HW breakpoints into the
application Synthesizing probes on demand / partial reconfiguration
SUnit embedded in hardware Synthesizing assertions in the netlist
Interfacing the synthesized application with high-level software tools Inspector utility on the circuit Collecting state values of the HW application at high-level
55D. Picard, L. Lagadec ESUG’09 - Brest
Thank you !Thank you !
QuickTime™ et undécompresseur TIFF (non compressé)sont requis pour visionner cette image.