PrimaryDroopCurrent-SharingControloftheParallelDC/DC ...2010/12/07 · Io is the total load current, and, thus, the equivalent load resistance of each DC/DC converter is Rn =Vo/Ioi

Hindawi Publishing CorporationAdvances in Power ElectronicsVolume 2011, Article ID 713250, 13 pagesdoi:10.1155/2011/713250

Research Article

Primary Droop Current-Sharing Control of the Parallel DC/DCConverters System considering Output Cable Resistance

J. B. Wang

Department of Electrical Engineering, Ching Yun University of Technology, 229, Chien-Hsin Road, Jung-Li 320, Taiwan

Correspondence should be addressed to J. B. Wang, [email protected]

Received 7 December 2010; Accepted 9 February 2011

Academic Editor: Francesco Profumo

Copyright © 2011 J. B. Wang. This is an open access article distributed under the Creative Commons Attribution License, whichpermits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

This paper presents a primary droop current-sharing controller that can integrate into voltage feedback controller and, thus,provides a low-cost and simple solution for parallel DC/DC converters system. From the equivalent small-signal model, a two-port network was adapted to describe the output and control variables for designing voltage and droop current-sharing loops.From the analysis results, the designed primary droop current-sharing controller will not affect the original voltage loop gainprofile to let the DC/DC converter preserve desire control performance. After designing a stable DC/DC converter with primarydroop current-sharing control, the stability of the interconnected parallel DC/DC converters system was studied. When the cableresistance is reduced, when the cable resistance is reduced, the interconnected system might be unstable. Finally, some simulationand experimental results demonstrated the effectiveness of the proposed controller in a prototype parallel DC/DC converterssystem.

1. Introduction

In general, the server power system infrastructure consists offrond end AC/DC converters to build up high DC voltageand DC/DC converters to provide power to downstreamload. The AC/DC converter uses power factor correctioncontrol to let the input line current meet the current har-monic specification; furthermore, the second-stage DC/DCconverters and the interconnected cables construct a DC-distributed power system. A DC power system consists ofmany standard DC/DC converters through interconnectedcables or copper buses in series or parallel to obtain desireoutput voltage, current, and power [1–4]. The structures ofthe interconnected DC power system have four topologies,that is, input series output series, input series output parallel,input parallel output series, and input parallel output series[2, 4]. The series structure can obtain high output voltageor withstand high input voltage; the kernel of the controlstrategy is to achieve voltage balance operation among theDC/DC converters. As to the parallel operation, high outputcurrent is the major advantage. However, the equal current-sharing control among each of DC/DC converters is the key

performance index. In the server power system infrastruc-ture, the parallel DC/DC converters system plays the key roleto provide low voltage and high output current capabilitythrough the delicate designed interconnected system.

In order to obtain equal current-sharing control inthe parallel DC/DC converters system, the current-sharingcontrol should be designed. The most prevailing current-sharing control scheme is the active current-sharing controlscheme, especially, the master slave and average current-sharing controls [5–10]. The literature [6, 7] provides thekey theoretical study in the master slave and average current-sharing controls. However, the control system analysis ofthe droop current-sharing control seems to have little study.Most of the investigations focused on the steady-state droopvoltage characteristics [11–18]. In addition, the intercon-nection of the DC/DC converters to form the parallel DCpower system requires extra cable wires or copper buses.The study depicted suitable cable resistance can improvethe stability of the parallel DC/DC converters system [19].Furthermore, the common mode stability problem causedby the interconnected and system impedances was foundin the paper [7]. The results showed the analysis and

2 Advances in Power Electronics

design method to obtain a stable interconnected system isto design a stable DC/DC converter and then to analysis thestability of the interconnected subsystem [20]. Finally, if theaforementioned analysis is stable, then the whole DC powersystem is also stable.

The major purposes of this paper are to design acontroller that integrates the voltage and droop current-sharing controllers and to investigate the effects of the outputcable resistance to the stability of the interconnected system.Firstly, the small signal model of the buck derived converterwas derived in term of the two-port network. From themodel reveals the cross-coupling effect was caused from theprimary droop current-sharing control path. In order to pre-serve the voltage loop gain profile, the droop controller wasproposed to reduce the parameter uncertainty of the DC/DCconverter. After designing a stable DC/DC converter primarywith droop current-sharing control, the final interconnectedsystem was analyzed. This system consists of many cablewires to parallel connect the output voltages of the DC/DCconverters to the system load. Using the circuit theory toanalyze this interconnected system found the cable resistancemight affect system stability. Through the investigationof a simple interconnected system, the phase margin willreduce when the cable resistance was reduced. In addition,the Spice-based circuit simulation further confirmed thisphenomenon. Finally, the design methods of the droopvoltage characteristics and controllers are provided in theappendix. Furthermore, some simulations and experimentalresults are used to demonstrate the aforementioned findings.

2. Modeling of a Parallel DC/DCConverters System with PrimaryDroop Current-Sharing Control

Figure 1(a) shows a parallel DC/DC converters system withprimary droop current-sharing control which consists of NDC/DC converters, and the symbol i denotes the ith DC/DCconverter for i = 1 to N . The interconnection of the DC/DCconverters system to load zL is modeled as a resistor rwi fori = 1 to N . In addition, the notations Voi and Vo denote theoutput voltage of the ith DC/DC converter and actual loadvoltage. In order to clarify the voltage and primary droopcurrent-sharing controllers, Figure 1(b) details the actualcircuits implementation of the ith DC/DC converter, whichis an interleaved dual switch forward converter (IDSFC)with one output inductor. Furthermore, the symbols Vrefi,Vi, n, Ioi, and Iii denote reference command setting, inputvoltage, transformer turn ratio, output current, and primaryinput current, respectively. The voltage controller integratesGc1(s) and Gc2(s) controllers with the Gdr(s) droop controllerusing a simple analog controller and thus provides a low-costsolution. The meanings of the controllers parameters can becomprehended by their notations. The low-pass filter Gf (s)senses the primary input current and generates the designeddroop voltage command Vdr with respect to different loadcurrents.

Figure 2(a) shows the equivalent small signal circuitsof the ith DC/DC converter, where the nominal duty

ratio, equivalent secondary voltage, and equivalent seriesresistances of output capacitor and inductor are D, Vg , rc,and rL, respectively, and Vg = Vi/n [21]. Furthermore,the lower case symbols vi, di, vg , igi, iii, and ioi denotethe small signal variables of the aforementioned uppercasenotations. For a N parallel DC/DC converters system, theoutput current of the ith DC/DC converter Ioi equals toIo/N in an equal current-sharing operating condition, whereIo is the total load current, and, thus, the equivalent loadresistance of each DC/DC converter is Rn = Vo/Ioi for smallsignal analysis. The small signal model of the converter inFigure 2(b) shows that droop current-sharing control viasensing primary input current contains an extra currentsource, that is, Ioidi. This current source shows an extracoupling effect between input current iii and duty ratio di.Neglecting the perturbation of the input voltage, the smallsignal model of the ith DC/DC converter is similar to a two-port network as shown in Figure 2(b) to be

⎡⎣voiiii

⎤⎦ =

⎡⎣Hi −zoiFdi Aii

⎤⎦⎡⎣diioi

⎤⎦,

Hi = voidi

∣∣∣∣ioi

= 0, zoi = voiioi

∣∣∣∣di

= 0,

Fdi = iiidi

∣∣∣∣ioi

= 0, Aii = iiiioi

∣∣∣∣di

= 0,

(1)

where input variables are di and ioi, and output variables aredenoted as voi and iii, respectively. The key transfer functionsused for analysis latterly list in the appendix. The detaileddesign and analysis are introduced as follow.

3. Parallel DC/DC Converters SystemAnalysis and Design

3.1. Voltage and Droop Current-Sharing Loops Design. FromFigure 2(b), the ith DC/DC converter includes the voltagefeedback, and primary droop current-sharing controllersare shown in Figure 3(a); furthermore, Figure 3(b) is itsequivalent control block diagram and suitable for controlsystem analysis via signal flow method. As a result, the totalloop gain of the ith DC/DC converter is

Tloop = Tv + Tdr, (2)

Tv = Gc1Gc2KHi, (3)

Tdr = KFdiG f GdrGc1, (4)

where Tv and Tdr denote voltage and droop current-sharingloop gains, respectively. Let the droop current-sharingcontroller design as

Gdr = kdGc2. (5)

The gain constant kd can deduce from Figure 1(b) to beR2/R3. Substituting (5) into (4), the total loop gain can beexpressed as

Tloop = Tv(1 + ΔW), ΔW = kdG f FdiHi

. (6)

Advances in Power Electronics 3

Vo1 Io1

Ii1

Vo2 Io2 Io Vo

Vi

zL

...

VoN rwN IoN

IiN

DC/DCconverter

1

DC/DCconverter

2

DC/DCconverter

N

rw1

Ii2

rw2

+−

(a)

Ioi

+

++

−

n : 1

ith DC/DC converter

L iLGc2(s) R Voi

C

R2R4

C1

Gc1(s)

C3 C2

R5

R3

R6 C4

R1

Iii G f (s)

n : 1

Vi

+

−

+

−

Vrefi

Two-phase PWMsignals generator

Gdr(s)

Vdr

(b)

Figure 1: (a) The parallel DC/DC converters system; (b) the interleaved dual switch forward converter with primary droop current-sharingcontrol.

In order to preserve the original voltage loop gain profileand not to be affected by the droop current-sharing loop, thetransfer function ΔW must meet the following criterion:

‖ΔW‖∞ � 1. (7)

After manipulating the transfer function ΔW , the denomi-nators of the transfer functions Hi and Fdi can cancel so theresonant peak of the transfer function ΔW will not occur.Furthermore, the droop gain constant kd and transformerturn ratio also contribute to let ‖ΔW‖∞ less than 1. Properlydesign the low-pass filter Gf to let ΔW be proper, andthe effect of the transfer function ΔW to voltage loop gaincould be small. As a result, the transfer function ΔW canbe regarded as parameter uncertainty of the plant. To reduce

parameter uncertainty of the plant, the simple approach isto increase the gain margin of the DC/DC converter. If thegain margin is greater than 10 dB, the effect of the parametervariations in modeling error can reduce [6]. The great benefitof using the design droop controller depicted in (5) is that thevoltage and droop current-sharing controllers can integrateand implement in a single operational amplifier as shownin Figure 1(b). The voltage controller shown in Figure 1(b)is a simple lead-lag controller Gc(s) which consists of thecontrollers Gc1(s) and Gc2(s), and can be expressed as

Gc(s) = Gc1(s)Gc2(s)

= (s/ωz1 + 1)(s/ωz2 + 1)

(s/ωo1)(s/ωp1 + 1

)(s/ωp2 + 1

) ,(8)


iiin : 1

igi = niiVgdi rL

L

iL− +

−+

−

+

voi

ioirc

Rn

C

Ioidi

vgvi

ith DC/DC converter

1 : D

(a)

di

ioi

voi

iii

iii

Aiiioi

voi

zoi

Rn

Hidi

ioi−+Two-port

networkFdidi

(b)

Figure 2: (a) The small signal model of the IDSFC; (b) the equivalent two port network.

ith DC/DC converter

iii

G f (s)

vrefi

−

−

−

+

+

+

Gc1(s)vc

Kdi

Gc2(s)

Voltage loop

Aiiioi Hidi

voi

zoi ioirw1

vo1

vo

vokrwk

vo jrw jrwi

zL io

...

Gdr(s)

vdr

Fdidi

Droop current-sharing loop

(a)

iiiG f (s)

vrefi

−+

+

+

Gc1(s)di

Gc2(s)

voi

zoi

ioiAii

Fdi(s)

Hi(s)K−

−+

+ vc

Gdr(s) = kdGc2(s)

Gdr(s)

vdr

(b)

Figure 3: (a) The control block diagram of the ith DC/DC converter in parallel DC/DC converters system; (b) the corresponding blockdiagram of the ith DC/DC converter.


DC/DCconverter

1 F1vref1

vo1 io1

DC/DCconverter

2

vo2

io2

io vo

zL

DC/DCconverter

N

voN

ioN

rwN

−+

−+

−+

rw1

rw2

FNvrefN

F2vref2

zof1

zof2

zofN

Figure 4: The Thevenin equivalent parallel DC/DC converterssystem.

where the poles and zeros of the voltage controller areωo1, ωp1, ωp2, ωz1, and ωz2, respectively, and might becomprehended from (8). A simple pole placement methodsuggested in the literature [22], and the desired total loopgain can be approximated as

Tloop = Tv(1 + ΔW) ≈ 1

(s/ωo)(s/ωp2 + 1

) , (9)

where the pole ωo designs to obtain desired bandwidth andphase margin; furthermore, the ωp2 filters out the switchingnoise. The detail parameters of the integrated controller arelisted in the appendix.

3.2. Interconnected System Analysis. In general, the stableDC/DC converter can be designed by aforementioned poleplacement scheme shown in (8). When a lot of stableDC/DC converters are paralleling operation, the intercon-nection of the DC/DC converters to actual load formsan interconnected system. In the following analysis, theThevenin theorem and signal flow method were used. FromFigure 3(b), the feedback output impedance of the DC/DCconverter is

zofi =AiiG f GdrGc1KHi + zoi

(1 + Gf GdrGc1KFdi

)

1 + Tv + Tdr

∼= kdG f AiiTv + zoiTdr

1 + Tv + Tdr.

(10)

Obviously, the feedback output impedance of the DC/DCconverter with primary droop current-sharing control isdiscrepant to original feedback output impedance. In fact,the primary droop current-sharing loop affects the feedback

output impedance. Furthermore, the transfer function fromreference command setting vrefi to output voltage voi can bededuced as

Fi(s) = voivrefi

= Gc1KHi

1 + Tloop. (11)

Then, the equivalent Thevenin small signal model of theparallel DC/DC converters system is showed in Figure 4.Using node analysis at output node, the relations of theoutput current ioi to reference command vrefi of each DC/DCconverter for i = 1, . . . ,N are⎡⎢⎢⎢⎢⎢⎢⎢⎣

F1vref1

F2vref2

...

FNvrefN

⎤⎥⎥⎥⎥⎥⎥⎥⎦

=

⎡⎢⎢⎢⎢⎢⎢⎢⎣

zL + rw1 + zof1 zL · · · zL

zL zL + rw2 + zof2 · · · zL

......

...

zL zL · · · zL + rwN + zofN

⎤⎥⎥⎥⎥⎥⎥⎥⎦

×

⎡⎢⎢⎢⎢⎢⎢⎢⎣

io1

io2

...

ioN

⎤⎥⎥⎥⎥⎥⎥⎥⎦.

(12)

The aforementioned matrix in (12) is nonsingular soits inverse matrix exists. Using matrix inversion formula((D − CE)−1 = D−1+D−1C(I − ED−1C)−1

ED−1), the outputcurrent ioi is⎡⎢⎢⎢⎢⎢⎢⎢⎣

io1

io2

...

ioN

⎤⎥⎥⎥⎥⎥⎥⎥⎦

=

⎧⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎨⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎩

⎡⎢⎢⎢⎢⎢⎢⎢⎣

z−11 0 · · · 0

0 z−12 · · · 0

......

...

0 0 · · · z−1N

⎤⎥⎥⎥⎥⎥⎥⎥⎦− 1

Δh

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

zLz2

1

zLz1z2

· · · zLz1zN

zLz1z2

zLz2

2· · · zL

z2zN...

......

zLz1zN

zLz2zN

· · · zLz2N

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

⎫⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎬⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎭

×

⎡⎢⎢⎢⎢⎢⎢⎢⎣

F1vref1

F2vref2

...

FNvrefN

⎤⎥⎥⎥⎥⎥⎥⎥⎦

,

(13)


where

zi = rwi + zofi, Δh = 1 +N∑

j=1

zLzj. (14)

If the parameters of the DC/DC converters are identicaland symmetric layout interconnected system is designed,that is, the cable resistance is identical. In this condition,The reference command setting vrefi of the ith DC/DCconverter is perturbed by vrefi, and the resulted outputcurrent perturbation io j for j = 1, . . . ,N is

io j =

⎧⎪⎪⎪⎪⎨⎪⎪⎪⎪⎩

z + (N − 1)zLz(z + NzL)

vrefi, j = i,

− zLz(z + NzL)

vrefi, j /= i, j = 1, . . . ,N ,

(15)

where zj = z, j = 1, . . . ,N . In general, the transfer functionFi is stable, and if the zeros of the denominator of (14)locate at on left half plane, then the parallel DC/DC con-verters system is stable. The aforementioned method can beapplied to other DC/DC converters like boost converter forexample.

4. Simulation and Experiment

Obviously, from (12) to (15), it is very difficult to find theeffect of the output cable resistance to system stability. Inorder to clarify this, an interconnected system equips withtwo DC/DC converters is analyzed in detail. From Figure 3,one can construct the control system block diagram of theinterconnected system as shown in Figure 5(a). Using (9) to(13), the cross coupling effects of the interconnected systemdepicts in Figure 5(b). The loop gain of the interconnectedsystem is

Tzloop = zofi y11 + zof j y22 − zofi y12zof j y21 + zofi y11zof j y22,(16)

where

y11 =zL + rw j

Δk, y22 = zL + rwi

Δk,

y12 = y21 = − zLΔk

, Δk = zLrwi + zLrw j + rwirw j .

(17)

If the parameters of the DC/DC converters are identical andsymmetric layout of the interconnected system is designed,(16) can be deuced as

Tzloop = zof(zof + 2zL + 2rw)Δk

. (18)

Substituting the parameters of the IDSFC into the transferfunctions Fdi and Aii, the resulted frequency responsesare demonstrated in Figure 6. It shows the magnitude ofthe transfer function Fdi is always above 0 dB due tothe extra current source in the small signal model. Inaddition, the profile of the transfer function Aii is similar

to the transfer function Hi with lower gain. Figure 7 depictsthe voltage, droop current sharing, and total loop gains andthe parameter uncertainty ΔW . One may find ‖ΔW‖∞ is–9.91 dB at 40.9 KHz and meets the criterion (7) so theeffect of the parameter uncertainty is minimized. Therefore,the profiles of the three loop gains are quite similar withdifferent offset. Using the proposed design droop controllerin (5), the total loop gain is not affected by the primarydroop current-sharing control significantly. The gain andphase margins of the DC/DC converter can be preserved andgained a stable operation. Figure 8 shows the discrepancyof the open-loop and feedback output impedances. It isinteresting to find that the feedback output impedance zofi

is greater than output impedance zoi in low frequency range.However, the feedback output impedance zofi is rolled offas frequency increased and does not have resonant peakphenomenon. In order to clarify the effects of the outputcable resistance to stability, two different cable resistanceswere simulated in the interconnected system loop gain asshown in Figure 9. When the cable resistance is reducedfrom 1 mΩ to 0.1 mΩ, the magnitude of the interconnectedsystem loop gain Tzloop is shifted up and leads to reducingphase margin of the system. From the simulation results,the magnitude and phase were not affected either resistanceload or paralleling extra 10000 μF capacitance load. In thissimulation case, the phase margin is 70◦ with rwi = 1 mΩ,but when the cable resistance was reduced to 0.1 mΩ, thephase margin is almost vanishing. In order to further findthe effects of the output cable resistance, a Spice-basedsimulation was carried out via Simetrix/Simplis. Figure 10shows the output current response of the step referentcommand disturbance in the 1 mΩ and 0.1 mΩ cases.Figure 9(a) depicts the output currents can subside back intoequal current-sharing control in 1 mΩ cable resistance case;unfortunately, Figure 10(b) shows the unstable operationvia 0.1 mΩ cable resistance. This conforms the previouscomments that a large cable resistance can improve thesystem stability [19].

After the simulations have demonstrated the perfor-mance of the proposed integrated controller for voltageand droop current-sharing control, the paralleled DC/DCconverter system with N = 2 was implemented. Further-more, The PWM IC UC3525 was used to generate two-phasePWM pulses to control IDSFC as shown in Figure 1(b).Figure 11(a) shows the measured primary currents andMOSFET drain to source voltage waveforms for referent. Itshows the primary currents of the two forward convertersare in balance operation. Owing to one output inductorscheme, two power trains of the IDFSC have the sameprimary side current, which reflects from the secondary sideinductor current as shown in Figure 11(b). Furthermore,the hot swap operation is also depicted in Figure 11(c),the parallel IDFSCs can achieve equal sharing control.Figure 12 shows the loop gain profiles of the IDFSC,which are similar to the simulation results. It shows thedesigned IDFSC has at least 45◦ phase margin, 10 dB gainmargin, and 10 KHz bandwidth; therefore, the effects ofthe parameter uncertainty can reduce significantly. Becausethe cable length of the prototype IDFSC is 30 cm with


ith DC/DC converter

iiiG f (s)

Gf (s)

vrefi

−

−

−+

+

+

+

+

+

+

Gc1(s)

Gc1(s)

vcK

di

Gc2(s)

Gc2(s)

voi

zoi

ioi

zL

io

Aii

Fdi(s)

Fdi(s)

Hi(s)

Hi(s)K

−+

+

+

Aij

y11

y12

y21

y22

Interconnected systemjth DC/DC converter

vo

−−

− −

+

+ +

+

zo j

vo jd j

vc

ii j io j

Gdr(s) = kdGc2(s)vdr j

vref j

vdri

Gdr(s)

Gdr(s) = kdGc2(s)

Gdr(s)

(a)

voi

ioi

zLio

vo j

io j

Interconnected system

Fj(s)

vrefi

vo

y11

y12

y21

y22

−+

−+

+

+

−+ −

+

Fi(s)

vref j

zofi

zof j

(b)

Figure 5: The parallel DC/DC converters system with N = 2 interconnected system: (a) detail control block diagram and (b) simplifieddiagram.

2 mΩ resistance as shown in Figure 13(a), the resultedinterconnection system is stable. The physical size of theIDFSC and interconnected system can let the cable lengthbe shorted to 15 cm, and the resulted cable resistanceis 1 mΩ as depicted in Figure 13(b). However, it is verydifficult to obtain 0.1 mΩ cable resistance in this labora-tory prototype interconnected system to demonstrate theunstable operation. Fortunately, from the theory study andsimulation verification, the cable resistance will affect systemstability.

5. Conclusions

An interconnected DC power system consists of DC/DCconverters with primary droop current-sharing control waspresented in this paper. Using the proposed droop controllerwill not affect the original design voltage loop gain profile butalso can integrate into voltage controller and thus providesa low-cost solution. Furthermore, after a stable DC/DCconverter design was achieved, the effect of the cable wireresistances of the interconnected system to stability was also


101 102 103 104 105 106

(Hz)

−100

−50

0

50

(dB

) Aii

Fdi

(a)

−150

100

(deg

)

101 102 103 104 105 106

(Hz)

−100

−50

0

50

Aii

Fdi

(b)

Figure 6: The frequency responses of the Fdi and Aii transfer functions at half load current operation: (a) magnitude; (b) phase.

(dB

)

ΔW

Tv

101 102 103 104 105 106

(Hz)

−60

−40

−20

0

20

40

60

Tdr

Tv + Tdr

(a)

−250

−200

−150

−100

−50

0

50

100

(deg

)

ΔW

Tv

101 102 103 104 105 106

(Hz)

Tv + Tdr

Tdr

(b)

Figure 7: The frequency responses of the transfer functions Tv , Tdr, Tv +Tdr, and ΔW at half load current operation: (a) magnitude and (b)phase.

investigated. The results demonstrated that the reductionof the cable resistance will decrease the phase margin ofthe interconnected system and lead to instability. Properlyincreasing the cable resistance can improve system stability,but the operating efficiency will reduce. This paper provides amethod to evaluate the stability of the interconnected system.Using this method, the engineer can make a tradeoff betweensystem stability and efficiency.

Appendix

(1) The Designed Parameters of the Interleaved Dual-SwitchForward Converter Are as Follows.

(i) Primary side DC bus voltage Vi = 385 V.

(ii) Primary switching frequency fs = 125 kHz.

(iii) Nominal output voltage Vo = 12 V.

(iv) Nominal output current Io = 66 A.

(v) Transformer PQ32/30 NP = 20 turns, Ns = 1 turn,and n = 20.

(vi) Output inductor MS10675 with inductance L =2μH.

(vii) Output capacitance C = 5400μF and esr = 4 mΩ.

(viii) Nominal duty ratio D = 0.62 in the secondary side ofthe IDSFC with an output inductor.

(ix) The gain of the PWM comparator K = 0.25.


101 102 103 104 105 106

(Hz)

(dB

)

zoi

zofi

−110

−100

−90

−80

−70

−60

−50

−40

−30

−20

(a)

101 102 103 104 105 106

(Hz)

−250

−200

−150

−100

−50

0

50

100

(deg

)

zoi

zofi

(b)

Figure 8: The frequency responses of the opened- and closed-loop output impedances of the DC/DC converter at half load currentoperation: (a) magnitude and (b) phase.

101 102 103 104 105 106

(Hz)

(dB

)

rwi = 0.1 mΩ

rwi = 1 mΩ

Tzloop−50

−40

−30

−20

−10

0

10

20

30

40System capacitors= 10000µF

(a)

101 102 103 104 105 106

(Hz)

−250

−200

−150

−100

−50

0

Tzloop

(deg

)

rwi = 0.1 mΩ

rwi = 1 mΩ

rwi = 0.1 mΩ

rwi = 1 mΩ System capacitors= 10000µF

System capacitors= 10000µF

(b)

Figure 9: The frequency responses of the parallel DC/DC converters system with output cable resistances 1 mΩ and 0.1 μΩ at half loadcurrent operation: (a) magnitude and (b) phase.

Ioi

Io j

0 2 4 6 8

1 mΩ output cable resistance

2426283032343638404244

V

1 A/V

(a)

Ioi

Io j

V

−40

0

40

80

I o(A

)

6767.5

6868.5

69

0 2 4 6 8

1 A/V

100µΩ output cable resistance

Io

(b)

Figure 10: The step reference command disturbance of the parallel DC/DC converters system with different output cable resistances atfull-load current operation: (a) 1 mΩ and (b) 0.1 μΩ.


200 V

Iii

Vds,QD1

3.3 A

Ch1 5 V Ch2 Ch2500 mV M 2µs A 1.79 V

(a)

10 V

IL

25 A

Vg

Ch1 Ch110 V Ch2 25 AΩ M 2µs A 9 V

(b)

60 A

Ioi

Io j

30 A

12.5 A 10 ms

(c)

Figure 11: The key waveforms of the parallel DC/DC converters system at full-load current operation: (a) primary current and primaryMOSFET drain to source voltage of the IDSFC; (b) the current and the input voltage of the output inductor; (c) hot swap operation.

(dB

)

−60

−40

−20

0

20

40

60

80Magnitude

Tv-simulation

Tv-measurement

101 102 103 104 105

(Hz)

66 A load current

Tv + Tdr-measurement

(a)

(deg

)

Tv-simulationTv-measurement

Phase

−100

−50

0

50

100

150

200

66 A load current

101 102 103 104 105

(Hz)

Tv + Tdr-measurement

(b)

Figure 12: The measured Tv and Tv + Tdr frequency responses of the IDSFC at full-load current operation: (a) magnitude and (b) phase.


DC/DC converter 1output wires

(a)

To load

Current sensors30 cm ruler



Oring diode

(b)

Figure 13: (a) The photograph of the IDSFC with 2 mΩ output cable resistance; (b) the back plane system withN = 2 and the correspondingconnected output cables.

(2) The Key Transfer Functions of the IDFSC

voidi= Hi(s) =

VgRn(sCrc + 1)

Δ,

iiidi= Fdi(s) =

Ioi +(DVg(SC(Rn + rc) + 1)/Δ

)

n,

iLidi= FdiLi(s) =

Vg(SC(R + rc) + 1)

Δ,

ioidi= Fdioi(s) =

Vg(SCrc + 1)

Δ,

zoi = voiioi= Rn(sCrc + 1)(sL + rL)

Δ,

Aii = iiiioi= DRn(sCrc + 1)

Δ,

(A.1)

where

Δ = s2LC(Rn + rc) + s(L + C(RnrL + Rnrc + rLrc)) + Rn + rL

∼= (Rn + rL)

((sωn

)2

+ 2ξsωn

+ 1

), Rn � rL, rc,

ωn = 1√LC

,

ξ = Z + (RnrL + Rnrc + rLrc)/Z2(Rn + rL)

,

Z =√

L

C.

(A.2)

(3) Design Procedure of the Steady-State Output VoltageDroop Characteristic. In general, the output voltage droopcharacteristic of a DC/DC converter depends on output

voltage regulation specification with a predetermined designmargin. If the maximum, nominal, and minimum outputvoltages of the regulation range are denoted as Voi,max,V∗oi , and Voi,min, respectively. From Figure 1(b), the output

voltage variation of the ith DC/DC converter with respect todroop current-sharing control is

Voi,max = V∗oi + ΔVoi = Vrefi

Kd, Ioi = 0, (A.3)

where

Voi,min = V∗oi −ΔVoi = Vrefi

Kd−Vdr

Kcs

Kd, (A.4)

Kd = R1R3

R1R2 + R1R3 + R2R3, Kcs = R1R2

R1R2 + R1R3 + R2R3.

(A.5)

Furthermore, the droop voltage Vdr synthesizes from pri-mary current through a low-pass filter, which is proportionto output current, that is, Iii = DIoi/n. From (A.3) and (A.4),the output voltage deviation ΔVoi can be expressed in termsof droop voltage as

ΔVoi = VdrKcs

2Kd= kdVdr

2. (A.6)

For a given output voltage deviation ΔVoi, the designprocedure of the output voltage droop characteristics issuggested as follows.

(i) Let R′1 = kVrefi and k > 0.

(ii) The resistance R2 can subsequently be determinedfrom the maximum output voltage listed in (A.3),Kd ,and R′1.

(iii) For a given specification of the output voltage devia-tion and droop voltage, the resistances R1 and R3 canbe found from (A.6) and resistance R′1.


Table 1

R1 R2 R3 R4 R5 R6 C1 C2 C3 C4

2.57 kΩ 10 kΩ 100 kΩ 1 kΩ 33 kΩ 10 kΩ 4700 pF 6800 pF 680 pF 220 pFx2

Table 2

Rf 1 Rf 2 Cf 1 Cf 2 k f

1 kΩ 100Ω 0.1 μF 0.01 μF 2.4

(4) Voltage and Primary Droop Current-Sharing Controller.The feedback controllers in Figure 1(b) are

Gc1(s) = (s/ωz1 + 1)

α2s(s/ωp1 + 1

) , Gc2(s) = (s/ωz2 + 1)

K2

(s/ωp2 + 1

) ,

(A.7)

where

ωp1 = 1C23R5

, ωp2 = 1C1R4

,

ωz1 = 1C2R5

, ωz2 = 1C1(R2 + R4)

,

α2 = C2 + C3, C23 = C2C3

C2 + C3,

K2 = R2, ωo1 = 1K2α2

.

(A.8)

(i) The design poles and zeros of the controller Gc1(s),Gc2(s), and Gdr(s) can let the DC/DC converter haveat least 45◦ phase margin, 10 dB gain margin, and10 KHz bandwidth

ω0 = 66845 rad/sec, ωp1 = 49019.6 rad/sec,

ωp2 = 212765.95 rad/sec, ωz1 = 4456.33 rad/sec,

ωz2 = 20263.24 rad/sec.(A.9)

(ii) Circuit parameters of the controller Gc1(s), Gc2(s),and Gdr(s); (see Table 1).

Note. (1) Using the nearest commercial parts instead of theestimated parameters.

(5) Low-Pass Filter Gf (s)

Gf (s)

= k f

s2Rf 1Rf 2Cf 1Cf 2 + s(Rf 1

(Cf 1 + Cf 2

)+ Rf 2Cf 2

)+ 1

.

(A.10)

(see Table 2).

Acknowledgment

The authors thank the National Science Council of Taiwanfor supporting the research project: NSC99-2221-E231-036.

References

[1] V. Vorperian, “Synthesis of medium voltage dc-to-dc con-verters from low-voltage, high-frequency PWM switchingconverters,” IEEE Transactions on Power Electronics, vol. 22,no. 5, pp. 1619–1635, 2007.

[2] R. Ayyanar, R. Giri, and N. Mohan, “Active input-voltageand load-current sharing in input-series and output-parallelconnected modular dc-dc converters using dynamic input-voltage reference scheme,” IEEE Transactions on Power Elec-tronics, vol. 19, no. 6, pp. 1462–1473, 2004.

[3] R. Giri, V. Choudhary, R. Ayyanar, and N. Mohan, “Common-duty-ratio control of input-series connected modular DC-DCconverters with active input voltage and load-current sharing,”IEEE Transactions on Industry Applications, vol. 42, no. 4,pp. 1101–1111, 2006.

[4] W. U. Chen, X. Ruan, H. Yan, and C. K. Tse, “DC/DCconversion systems consisting of multiple converter modules:stability, control, and experimental verifications,” IEEE Trans-actions on Power Electronics, vol. 24, no. 6, pp. 1463–1474,2009.

[5] S. Luo, Z. Ye, R. L. Lin, and F. C. Lee, “Classification andevaluation of paralleling methods for power supply modules,”in Proceedings of the 30th Annual IEEE Power ElectronicsSpecialists Conference (PESC ’99), vol. 2, pp. 901–908, July1999.

[6] D. S. Garabandic and T. B. Petrovic, “Modeling paralleloperating PWM DC/DC power supplies,” IEEE Transactionson Industrial Electronics, vol. 42, no. 5, pp. 545–551, 1995.

[7] V. J. Thottuvelil and G. C. Verghese, “Analysis and controldesign of paralleled DC/DC converters with current sharing,”IEEE Transactions on Power Electronics, vol. 13, no. 4, pp. 635–644, 1998.

[8] J. Rajagopalan, K. Xing, Y. Guo, F. C. Lee, and Manners,“Modeling and dynamic analysis of paralleled dc/dc converterswith master-slave current sharing control,” in Proceedingsof the 11th IEEE Applied Power Electronics Conference andExposition (APEC ’96), vol. 2, pp. 678–684, 1996.

[9] Y. Panov, J. Rajagopalan, and F. C. Lee, “Analysis and designof N paralleled DC-DC converters with master-slave current-sharing control,” in Proceedings of the 12th IEEE AppliedPower Electronics Conference and Exposition (APEC ’97), vol. 1,pp. 436–442, 1997.

[10] Y. Huang and C. K. Tse, “Circuit theoretic classification ofparallel connected dc-dc converters,” IEEE Transactions onCircuits and Systems I: Regular Papers, vol. 54, no. 5, pp. 1099–1108, 2007.

[11] Y. Panov and M. M. Jovanovic, “Loop gain measurementof paralleled dc-dc converters with average-current-sharingcontrol,” in Proceedings of the 23rd Annual IEEE Applied PowerElectronics Conference and Exposition (APEC ’08), pp. 1048–1053, February 2008.


[12] I. Batarseh, K. Siri, and H. Lee, “Investigation of the outputdroop characteristics of parallel-connected DC-DC convert-ers,” in Proceedings of the 25th Annual IEEE Power ElectronicsSpecialists Conference (PESC ’94), vol. 2, pp. 1342–1351, June1994.

[13] J. Perkinson, “Current sharing of redundant DC-DC con-verters in high availability systems—a simple approach,” inProceedings of the IEEE 10th Annual Applied Power ElectronicsConference (APEC ’95), vol. 2, pp. 952–956, March 1995.

[14] Brian T. Irving and Milan M. Jovanovic, “Analysis, design, andperformance evaluation of droop current-sharing method,” inProceedings of the IEEE Applied Power Electronics Conferenceand Exposition (APEC ’00), vol. 1, pp. 235–241, 2000.

[15] J. W. Kim, H. S. Choi, and B. O. H. Cho, “A novel droopmethod for converter parallel operation,” IEEE Transactions onPower Electronics, vol. 17, no. 1, pp. 25–32, 2002.

[16] X. Zhou, P. Xu, and F. C. Lee, “A novel current-sharing con-trol technique for low-voltage high-current voltage regulatormodule applications,” IEEE Transactions on Power Electronics,vol. 15, no. 6, pp. 1153–1162, 2000.

[17] J. A. Abu Qahouq, L. Huang, and D. Huard, “Sensorlesscurrent sharing analysis and scheme for multiphase convert-ers,” in Proceedings of the IEEE 38th Annual Power ElectronicsSpecialists Conference (PESC ’07), pp. 2029–2036, June 2007.

[18] H. Mao, L. Yao, C. Wang, and I. Batarseh, “Analysis of inductorcurrent sharing in nonisolated and isolated multiphase DC-DC converters,” IEEE Transactions on Industrial Electronics,vol. 54, no. 6, pp. 3379–3388, 2007.

[19] T. F. Wu, K. Siri, and J. Banda, “Central-limit controland impact of cable resistance in current distribution forparallel-connected DC-DC converters,” in Proceedings of the25th Annual IEEE Power Electronics Specialists Conference(PESC ’94), vol. 1, pp. 694–702, June 1994.

[20] J. Lunze, Feedback Control of Large-Scale Systems, PrenticeHall, New York, NY, USA, 1992.

[21] R. W. Erickson and D. Maksimovic, Fundamentals of PowerElectronics, Kluwer Academic, Boston, Mass, USA, 2nd edi-tion, 2001.

[22] M. Brown, Power Supply Cookbook, Butterworth-Heineman,Oxford, UK, 1994.

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PrimaryDroopCurrent-SharingControloftheParallelDC/DC ...2010/12/07 · Io is the total load current, and, thus, the equivalent load resistance of each DC/DC converter is Rn =Vo/Ioi

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