President & CEO Director, Engineering Mixel, Inc. Qualcomm ......Mixel, Inc. Qualcomm Technologies, Inc. Standard Version Adopted DataRate (Per Trio) PHYInterface (Per Trio) MIPI C-PHY

Ashraf Takla C.K. Lee President & CEO Director, Engineering

Mixel, Inc. Qualcomm Technologies, Inc.

MIPI C-PHYSM/D-PHYSM Dual Mode Subsystem Performance & Use Cases

©2017MIPIAlliance,Inc.

Agenda• MIPID-PHYspec

– Overview– Blockdiagram

• MIPIC-PHYspec– Overview– Blockdiagram– C-PHYadditionalblock

• Comparison:D-PHYvs.C-PHY– Advantage– Disadvantages

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• DualmodeMIPID-PHY/MIPIC-PHY• SiliconResults

– TX– RX

• UseCases– Camera– Display

• Adoption• Challenges• Conclusion• Q&A

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MIPID-PHYSpecifications&Performance• Specversionversusdatarate

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Standard Version Adopted Data Rate(PerLane)

PHY Interface(PerLane)

MIPID-PHY 1.0 Sep2009 1.0 Gbps 8bit1.1 Dec2011 1.5 Gbps 8bit1.2 Sep 2014 2.5Gbps 8bit2.0 Mar2016 4.5 Gbps 8/16/32 bit2.1 March2017 4.5Gbps 8/16/32bit

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MIPID-PHYBlockDiagram

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MIPID-PHYHS&LPOperation

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MIPIC-PHYBlockSpecifications&Performance• Specversionversusdatarate

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Standard Version Adopted Data Rate(PerTrio)

PHY Interface(PerTrio)

MIPIC-PHY 1.0 Oct2014 2.5Gsps 16bit1.1 Feb2016 2.8Gsps 16/32bit1.2 March2017 3.5 Gsps 16/32bit

Note: AMIPIC-PHYlaneisknown asa Trio. 1Sym =2.28bits

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MIPIC-PHYBlockDiagram

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MIPIC-PHYandMIPID-PHYHS&LPOperation

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MIPIC-PHYUniqueFeatures• Performance(bitrate2.28xthesignalingrate,e.g.1Gsps=2.28Gbps)

– HigherthanD-PHYonanominal10-wireportby1.7X• Pins

– Fewerpins&balls(duetohigherperformanceperpin)– Flexibility,duetotheindependenceofeachlane,clockisembedded,youcanborrowonelanefromonelinktoanother– CoexistsonsamepinswithMIPID-PHY

• LowerPowerathigherdatarateapplications• Flexibility

– EmbeddedclockenablesassignmentofanylaneontheAPtoanylink– FreeofMIPID-PHY‘sneedtoassociatedatalaneswithaclocklane

• Interference(Lowemissions)– Embeddedclockeliminatesclockspuremissions,particularlyimportantinmulti-bandwirelessdevices

• Embeddedcontrolcodesenableefficientemergingfeatures:– AlternateLowPowermode(ALP),enableslongerreachbyeliminatingsingle-endedLPmode, whichresultsinareareduction– FastBTAoperations– Lowerlatency(LRTE)fortime-sensitivelinks

• Lowertogglerateoftensimplifiesmanufacturingandlowerscosts– Moreapplicabletolowcostproducts,suchaslow-endcameras

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MIPIC-PHYBriefOverview

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MIPID-PHYandMIPIC-PHYComparisonParameter MIPID-PHYv1.2 MIPIC-PHYv1.0Design Simple,

source synchronousclockEmbeddedclock,edgedetectionCDR

Power/Gbps Larger Smaller

Area(min.configuration) SmallerArea Larger,Additional blocks

Area/Gbps(1) Larger Smaller

Bandwidth(D-PHY1.2vs.C-PHY1.0) Max10Gfor4lanes(10pins) Max17.1Gfor3lanes(9pins)(2)

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(1)FourdataD-PHYlanesvs.threeMIPIC-PHYtrios(2)HigherbandwidthduetoEncoding

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MIPID-PHYandMIPIC-PHYComparison

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Parameter MIPID-PHYv1.2 MIPIC-PHYv1.0Minimum #ofpins 4 3

Flexibility Alllanesoperatetogether EachLane worksindependently.Highflexibility

TransmissionEfficiency 1Bit/UI 2.28Bit/UI

Testing ChallengeduetoLPandHSmodes Additional complexitydueto3wires

Adoption Longhistoryofuse,wideradoption Acceleratedadoption,co-existswithMIPID-PHY

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MIPID-PHYandMIPIC-PHYComparison

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• AttheSameLinkRate,C-PHYhas:– Fewer wires(upto 40%less)– LowerToggleRate/Lane(12.5%

lower)– LowerPowerConsumption(~20-

50%lower)– Smallernumberoflanes,thus

smallerareaforsameGbps– NoEmissionsfromaClockLane

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MixelDualModeMIPID-PHY/MIPIC-PHYAdvantages• Sharingoftheserialinterfacepins• Sharingofcommonblocks,resulting inareareduction• Power/Gbpsreduction• SmoothtransitionbetweenMIPID-PHYandMIPIC-PHY• Has thebenefitoftheMIPIC-PHYPPAimprovements,while

maintaining compatibilitywithMIPID-PHY,usingsamepins

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Mixel MIPIC-PHY/MIPID-PHYComboIP

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• ComboIPBlocks– SharedbetweenMIPIC-PHY

andMIPID-PHY:• HS-TX,HS-RX,SER,DESER,LP-TX,

LP-RXandLP-CD

– AddedforMIPIC-PHY:• Encoder,Decoder,CDR,Mapper

andDe-Mapper

– AllMIPID-PHYfunctionalblocksarereusedfortheMIPIC-PHY

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Foundriesandnodes

S: Silicon-provenP:Pre-siliconMixel andQualcomm

Foundry 65nm 55nm 40nm 28nm 14nm 10nm 7nmF1 S S P PF2 SF3 S S P

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SiliconresultsTX

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MIPIC-PHYTransmitterTestingSet-up

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SiliconResultsTXMIPIC-PHY– EyeDiagrams

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1.5GSPS 2.5GSPS

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SiliconResultsTXMIPIC-PHY– EyeDiagrams

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2.5GSPS@short channel

QualcommTechnologies,Inc.

2.5GSPS@ std channel1.05 GSPS@std channel

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SiliconResultsTXMIPIC-PHY– EyeDiagrams

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Sony

6.5GSPS@ short channel3.5GSPS@ standard channel

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SiliconresultsTXMIPID-PHY– EyeDiagrams

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1.5GBPS 2.5GBPS

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SiliconResultsTXMIPID-PHY– EyeDiagrams

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2.5GSPS@short channel

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4.5GSPS@ short channel

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SiliconResultsRX - Electrical

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SiliconResultsRX- Link

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Exampleusecase:camerabringup

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Exampleusecase:Displaybringup

QualcommTechnologies,Inc.1440x2560

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MIPIC-PHY/MIPID-PHYPPA - Qualcomm

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• ComboPHYareaincrement < 10%• ComboPHYcan coverwiderangeof Resolutions : 80Mpbs - 10Gbps - 17.1Gbps- 18Gbps - 23.94Gbps• MIPIC-PHY mode : ~10-30% lowerpowerthanDPHYmode becauseof lowfreq/smallerbias/lesser#oflanes

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MIPIC-PHYAdoption• Camera&Display

– [Cam]Sony /OVT/andothers– [Display]CompletedIOTtestwithmostMajorDDICcompanies

• IP– Mixel

• AP(SOC)– SnapDragon,andothers

• Tester– Keysight,Tektronix,Introspect,TheMovingPixelCompany

• Common-modefilters– Murata,Panasonic,TDK

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MIPIC-PHYChallenges• UniqueCDRthatneedstobeprogrammedfordifferentdata

rateranges• Multi-levelsignaltransmission

– Introducesencodingjitter,butnoneedformulti-leveldetectionontheRXside

• UniqueTrio-basedsignaling– PCBdesign

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Conclusion• MIPIC-PHYisa morecomplex,powerfulandefficientPHY.TheMIPID-PHY/MIPIC-PHY

comboisevenmoresoonallaccounts• MIPIC-PHYprovidesPPAimprovementattheexpenseofadditionalcomplexity• ComboPHYprovidestheflexibilitytosupportbothPHY’susingsamepinswithminimal

overhead,whileenhancingPPA• MostblocksarecommonbetweenMIPID-PHYandMIPIC-PHY,andthusareshared,

resultinginsmalloverhead forthecomboIP• ThereisgoodtractionforMIPIC-PHY/MIPID-PHYcomboinMIPICSI℠ applicationsand

MIPIDSI℠ iscomingonline• TheMIPIC-PHY/MIPID-PHYcombo issilicon-proveninmultiplenodesandfoundries

andhasbeenintegratedintoseveralendproductsbymanytier-oneSOC,sensor,anddisplayvendors

Mixel,Inc. QualcommTechnologies,Inc.

Ashraf Takla C.K. Lee President & CEO Director, Engineering

Mixel, Inc. Qualcomm Technologies, Inc.

MIPI C-PHYSM/D-PHYSM Dual Mode Subsystem Performance & Use Cases