Presented by: Sergio Ospina Qing Gao. Contents ♦ 12.1 Processor Organization ♦ 12.2 Register Organization ♦ 12.3 Instruction Cycle ♦ 12.4 Instruction.

Presented by:Sergio OspinaQing Gao

ContentsContents

♦ 12.1 Processor Organization♦ 12.2 Register Organization♦ 12.3 Instruction Cycle♦ 12.4 Instruction Pipelining

12.1 Processor Organization

♦ Fetch Instruction♦ Interpret Instruction♦ Fetch Data♦ Process Data♦ Write Data

Remember….

♦ The processor needs to store some data temporally.

♦ It must remember the location of the last instruction so that it can know where to get the next instruction.

♦ It needs to store instructions and data temporally while an instruction is being executed.

CPU with System Bus

CPU Internal Structure

12.2 Register Organization

♦ User-visible registers

♦ Control and status registers

User Visible Registers

♦ General Purpose♦ Data♦ Address♦ Condition Codes

Control & Status Registers

♦ Program Counter

Contains the address of an instruction to be fetched.

♦ Instruction Decoding Register

Contains the instruction most recently fetched.

♦ Memory Address Register

Contains the address of a location in memory.

♦ Memory Buffer Register

Contains a word of data to be written to memory or the word most recently read.

Program Status Word

♦ Sign ♦ Zero♦ Carry♦ Equal♦ Overflow♦ Interrupt enable/disable♦ Supervisor

Example Register Organization

12.3 Instruction Cycle

♦ It is the time in which a single instruction is fetched from memory, decoded, and executed.

♦ An Instruction Cycle requires the following sub cycle:

Instruction Cycle♦ Fetch Reads the next instruction from memory into the

processor.

♦ Indirect Cycle (Decode Cycle) May require memory access to fetch operands,

therefore more memory accesses.♦ Interrupt

Save current instruction and service the interrupt.

♦ Execute

Interpret the opcode and perform the indicated operation.

Instruction Cycle

Fetch

Interrupt

IndirectExecute

Data Flow (Fetch Diagram)

PC

ControlUnit

PC MARMAR

MemoryMemory

ControlUnit

MBR

Memory

IR MBR

Data Flow (Indirect Diagram)

MBR

MARMAR

Memory

ControlUnit

Memory

MBR

Memory

Data Flow (Interrupt Diagram)

ControlUnit

PC

MBR

PC

ControlUnit

MARMAR

Memory

MBR

MemoryMemory

ControlUnit

ControlUnit

PC

Data Flow (Execute)♦ May take many forms♦ Depends on instruction being executed♦ May include

Memory read/writeInput/OutputRegister transfersALU operations

12.4 Instruction Pipelining

♦ Instruction processing is subdivided: Fetch/ Execute instruction

♦ Pipeline has two independent stages: 1st Stage – Fetch an instruction and buffers it.

2nd Stage – Temporarily free until first stage passes it the buffered instruction.

While the second stage is executing the instruction, the first stage fetches and buffers the next instruction.

♦ Instruction prefetch or fetch overlap. - Purpose? To speed up instruction execution.

Two-Stage Instruction Pipeline

Instruction Processing♦ Fetch instruction (FI)♦ Decode instruction (DI)♦ Calculate operands (CO)♦ Fetch operands (FO)♦ Execute instruction (EI)♦ Write operand (WO)

♦ Successive instructions in a program sequence will overlap in execution.

Timing Diagram for Instruction Pipeline

Operation

Six-Stage CPU Instruction PipelineThe logic needed for pipelining to account for branches, interrupts, and arising problems.

Alternative Pipeline Depiction

Branches

♦ Branch- group of instructions

♦ Branch Instructions – (Jump Instruction) One of it’s operands is the address of the next instruction to be executed.

Branches

♦ Two Types of Branch Instructions• Unconditional – Branch always happens• Conditional – Branch only happens if

certain condition is met.- The PC is updated to the address specified in the operand of the conditional branch instruction.

- A conditional branch instruction is similar to an if statement.

Conditional Branch Instructions

♦ Condition CodesBRP X

○ Branch to location X if result is positiveBRZ X

○ Branch to location X if result is zeroBRE R1,R2,X

○ Branch to location X if contents of R1 = R2

Conditional Branch Instructions

Dealing with Branches

♦ A major problem in designing an instruction pipeline is assuring a steady flow of instructions to the initial stages of the pipeline.

♦ Since conditional branches alter the steady flow of instructions, we must come up with ways to execute them efficiently.

Dealing with Branches

♦ 5 Approaches to Dealing with Conditional BranchesMultiple StreamsDelayed BranchPrefetch Branch targetLoop BufferBranch Prediction

Dealing with Branches

♦ Multiple Streams (IBM 370/168 and IBM 3033)○ Pipeline fetches both instructions.

Leads to contention delays, and branches can lead to too many streams.

♦ Delayed Brancho Branch Instruction occurs later than desired.

♦ Prefetch Branch Target (360/91 IBM)o The target of the branch is prefetched, along with the

instruction following the branch, so if the branch is taken this will speed up performance.

Dealing with Branches

♦ Loop buffer ( Motorola 68010)Memory containing the n most recently

fetched instructions.Useful with if-then and if-then-else

statements, as well as loops♦ Branch Prediction

Different techniques are used to predict whether the branch will be taken or not

If the prediction is correct this will speed up performance

Dealing with Branches

Review Questions1. What are the major components of a processor? Arithmetic and Logic Unit (ALU) and the Control Unit (CU).

2. What is the function of the ALU? The ALU does the actual computation or processing of data.

3. What is the function of the control unit? The control unit controls the movement of data and instructions into and out of

the processor and controls the operations of the ALU.

4. What are the two roles that registers in the processor perform?

User-visible registers, and control and status registers.

5. What are bits set by the processor hardware as a result of operations?

Condition codes.

Review Questions (Continued)

6. What is an instruction cycle? It is the time in which a single instruction is fetched from memory, decoded, and

executed.

7. What are the four sub cycle of an instruction cycle? Fetch, Indirect (if any) , execute, and interrupt (if any).

8. Is the fetch or execute cycle the same for all CPU? No, it depends on the CPU’s design.

9. What is the sequence of an interrupt cycle? PC MBR

Address of Stack MAR

MAR Memory

PC Memory

Control Unit request memory write via Control Bus

PC is loaded with address of Interrupt handler.

Review Questions (Continued)

10. What is the main purpose for instruction pipelining? To speed up the instruction execution rate.

11. How can you make the pipelining more efficient? To gain further speedup, the pipeline must have more stages for

decomposition.

12. What is a condition code? A statement that if true will allow the branch to be executed.

13. What is another name for a branch instruction? A jump instruction.

Research

♦ http://www.it.jcu.edu.au/Subjects/cp1300/resources/lectnotes/system/fde.html

♦ http://dr-pisit.com/csc331/Lec10-CPU&Pipeline.pdf ♦ http://en.wikipedia.org/wiki/Instruction_pipelining♦ http://www.itreviews.co.uk/hardware/h738.htm