Presented by: Presented by: Reshef Schreiber Reshef Schreiber Itay Leibovitz Itay Leibovitz Instructed by: Instructed by: Eran Segev Eran Segev
Presented by:Presented by:
Reshef SchreiberReshef SchreiberItay LeibovitzItay Leibovitz
Instructed by:Instructed by:
Eran SegevEran Segev
Board ObjectivesBoard Objectives
The Serial Communication Board (SCB) enables The Serial Communication Board (SCB) enables the DSP developer to interface to the commercial the DSP developer to interface to the commercial DSP evaluation board using common serial DSP evaluation board using common serial channels:channels: RS 232 RS 232 USB USB McBSP channelsMcBSP channels
The SCB expand the I/O capabilities of the The SCB expand the I/O capabilities of the evaluation boardevaluation board
The SCB interfaces mechanically and electrically to The SCB interfaces mechanically and electrically to the External Memory Interface (EMIF) connectors the External Memory Interface (EMIF) connectors of the evaluation boardof the evaluation board
DSP Evaluation BoardDSP Evaluation Board
SCB InterfacesSCB Interfaces
SCB
Channel A
Channel B RS-232
USB
Channel A
Channel B
Channel B
McBSP
External Memory Interface (EMIF)
Power
3.3 V
McBSP Signals
Interrupts
Channel A
Part ListPart List
FPGA:FPGA: ALTERA FLEX10k: EPF10K30ATC 144-pinALTERA FLEX10k: EPF10K30ATC 144-pin ALTERA EPC2ALTERA EPC2
RS232:RS232: DUART: EXAR ST16C2552CJ44 DUART: EXAR ST16C2552CJ44 Transceivers: 2 MAXIM-IC MAX3241Transceivers: 2 MAXIM-IC MAX3241 1.8432 MHz Crystal1.8432 MHz Crystal 2 RS232 9-pin male connectors 2 RS232 9-pin male connectors
USB: USB: 2 cypress SL811HS2 cypress SL811HS 2 USB Connectors Type A2 USB Connectors Type A 2 48MHz Crystals 2 48MHz Crystals
ImplementationImplementation
The DSP will approach the USB and RS232 The DSP will approach the USB and RS232 according to specific external address.according to specific external address.
All signals (address, data, control) will go All signals (address, data, control) will go through the FPGA.through the FPGA.
The FPGA will produce read/write cycles for The FPGA will produce read/write cycles for each block, and handle interrupts.each block, and handle interrupts.
SCB block diagramSCB block diagram
Evaluation Board
Interface(FPGA)
McBSP
USB
RS232
Channel A
Channel B
Channel B
Channel B
Channel A
Local Bus
External Memory Interface (EMIF)
Interrupts
Channel A
FPGA block diagramFPGA block diagram
EMIF to LocalBridge
InterruptController
ResetFunction
Reset
Local BusEMIFEMIF
DUART ResetDUART Reset
USB1 ResetUSB1 Reset
USB2 ResetUSB2 Reset
DUART Interrupt 1DUART Interrupt 1
DUART Interrupt 2DUART Interrupt 2
USB1 Interrupt USB1 Interrupt
USB2 Interrupt USB2 Interrupt
Interrupt 1Interrupt 1
Interrupt 2Interrupt 2
Interrupt 3Interrupt 3
Interrupt 4Interrupt 4
RS - 232RS - 232
DUART
BusTransceiver
BusTransceiver
Local Bus
USB InterfaceUSB Interface
Local Bus
Power ConsumptionPower Consumption
The DSP can supply 1A to the daughtercardThe DSP can supply 1A to the daughtercard The SCB power consumption:The SCB power consumption:
USB: 25mA (Max)USB: 25mA (Max) DUART: 1.2mA (Max)DUART: 1.2mA (Max) MAX3241: 1mA (Max)MAX3241: 1mA (Max) ALTERA: 100mA (at 20MHz)ALTERA: 100mA (at 20MHz)
Total: ~250mA (with 50% overhead)Total: ~250mA (with 50% overhead)
ScheduleSchedule
Next 2 weeks: Final schematicsNext 2 weeks: Final schematics Till mid February: Editing card + VHDLTill mid February: Editing card + VHDL Start debuggingStart debugging
Top Level SchematicsTop Level Schematics
RS-232 SchematicsRS-232 Schematics
USB SchematicsUSB Schematics