Presentazione standard di PowerPoint · Modelling and Simulation for lock-in amplifiers TYPICAL APPLICATION DIAGRAM LOCK-IN In this configuration the PLL section is not required because

Modelling and Simulation for Lock-In Amplifiers

Slow is accurate, accurate is fast.

Pripyat, 1996

Simone Mannori

November 22, h. 10:00 AM

Room: B.Brunelli – ENEA Frascati

Magnetic grid sensor – Brasimone 2014-15

Modelling and Simulation for lock-in amplifiers

LOCK-IN AMPLIFIER (LIA):: DEFINITION

An amplifier that can extract a signal with a known carrier wave (Fm) from an extremely noisy environment.

Depending on the dynamic reserve (“headroom”) of the instrument, signals up to 1 million times smaller (-120 dB) than noise components, potentially fairly close by in frequency, can still be reliably detected and measured (absolute amplitude and phase respect a reference).

The LIA is a homodyne detector (synchronous demodulator) followed by low pass filter adjustable in cut off frequency (time constant) and filter order (frequency slope).

Source: Wikipedia.


TYPICAL APPLICATION DIAGRAM

LOCK-IN

In this configuration the PLL section is not required because the carrier signal is directly modulated by the internal SINE reference (Ref-In).

SR-844 Block

Diagram

Stanford Research

PLL


FLOATING POINT REPRESENTATION INSIDE NUMERICAL SIMULATIONS

Critical operations:

Multiplication: GOOD

Division: potentially EXPLOSIVE!

Addition / Subtraction: EVIL, Extremely Dangerous!

-->20*log10(1/1E-6) = 120 dB – Typical lock-in dy.r.

-->20*log10(2^52) = 313.07 dB – IEEE 754 double p. dy.r.

-->20*log10(2^23) = 138.47 dB – IEEE 754 single p. dy.r.

Single Precision = Patriot Bug

http://www.math.umn.edu/~arnold/disasters/patriot.html:

The Scud struck an American Army barracks, killing 28 soldiers and injuring around 100 other people (First Gulf War, February 25, 1991).

http://www.math.umn.edu/~arnold/disasters/patriot.html

http://www.math.umn.edu/~arnold/disasters/patriot.html

Modelling and Simulation for lock-in amplifiers design

FLOATING POINT REPRESENTATION DYNAMIC RANGE

-->20*log10(1/1E-6) = 120 dB – Typical lock-in

Double precision (IEEE 754 - 64 bit) floating point representation is mandatory for accurate simulations.

Similar considerations about dynamic range and precision of numerical representation and signal processing operations must be applied also for DSP and FPGA realizations of lock-in amplifiers.

Reduced precision/dynamic range must be applied wisely and with extreme caution


TYPICAL APPLICATION DIAGRAM

LOCK-IN

In this configuration the PLL section is not required because the carrier signal is directly modulated by the internal SINE reference (Ref-In).


Reference generator.


Reference generator (180 MHz).

Signal generator, 2-ports power splitter, 90° 4-ports hybrid shifter.


Synchronous Demodulator


Demodulator = Fourier Transform at single frequency

𝑅𝑒 = 1

𝑇 𝐼𝑛 𝑡 ∗ 𝑠𝑖𝑛 2𝜋𝑓𝑚𝑡 𝑑𝑡𝑇/2

−𝑇/2

𝐼𝑚 = 1

𝑇 𝐼𝑛 𝑡 ∗ 𝑐𝑜𝑠 2𝜋𝑓𝑚𝑡 𝑑𝑡𝑇/2

−𝑇/2


NORMALIZED DESIGN SPECIFICATIONS / RULES OF THUMB

• Input signal: 1 MHz, sinusoidal, no harmonics, derived from sine reference signal.

• Input signal/lock-in bandwidth: 1 Hz, single pole, tau = 1/(2*%pi*1.0) = 0.159 s

• Signal amplitude: sqrt(2)=1.41 Volt (peak). This value produce 1 Watt of normalized power over R = 1 Ohm; P = 1/2 (Vi^2)/R = 1 Watt

• Noise: additive to input signal, white, Gaussian with normalized sigma/variance = 1.0 and average_value = 0; P(noise)=(sigma)^2/R = 1Watt. The reference noise signal is multiplied by a constant factor “NPF” in order to obtain the desired signal to noise ratio, therefore

SNR = 10*log10(Signal_Power/Noise_Power) = 10*log10(1/NPF^2) =

- 20*log10(NPF); (e.g. NPF=100, SNR= -40dB)

• Signal plus Noise Channel: flat response/unitary gain.

• Reference Signals: sine/cosine signals, 1MHz, 1.41 Volt normalized amplitude.

• Transient lock-in response: the input signal is AM modulated by a slow square wave of 10 seconds period and unitary amplitude (100% modulation). This auxiliary AM modulations allows the study of the transient response of the real/imaginary output channels.


Normalized simulation of an Analog Lock-In Amplifier


Normalized simulation results

With SNR_In = - 20dB the signal is no longer visible (e.g. not trigger on oscilloscope). The lock-in is perfectly able to recover the signal (red), measuring real (black) and imaginary (green) components.

Play the video: “InputSignal_raw.mp4”


A Lock-in Amplifier improve the Noise Figure (1/2)

DEFINITIONS:

• SNR = Signal_Power/Noise_Power

• Noise Figure = N.F. = SNR_Input/SNR_Output

• N.F.(dB) = SNR_Input(dB) - SNR_Output(dB)

Usually, (in decibel) the noise figure of a standard amplifier is a positive number: the SNR at the input is better that the SNR at the output because the amplifier add some of its internal noise to the signal during the amplification process (Bill Hewlett, 1940).

In a lock-in amplifier, the N.F. is a negative number (in dB), because (i) the input SNR is negative and (ii) the SNR at the output is positive.

The signal to noise improvement of the lock-in amplifier is understandable if we consider the bandwidth of signal and noise. The power of the noise is spread over a very large bandwidth, instead the signal is concentrated over a very small bandwidth. The lock-in amplifier suppress (almost) all the noise far from the phase/quadrature reference signals frequency, leaving only the narrow bandwidth ( 1Hz in the example) of the output filters.


A Lock-in Amplifier improve the Noise Figure (2/2)

Rule-of-thumb estimate:

N.F.(dB) = 10*log10(BW/Fm) = 10*log10(1Hz/1MHz) = -60 dB

In a perfect (ideal) lock-in, if the disturbing signal is Gaussian white noise, the N.F. decrease with Fm and increase with the output filter bandwidth BW. Be aware that negative N.F. is good (recover and measure the signal is possible) and positive N.F. is bad (signal cannot be recovered).

For RGB-ITR the hypothesis about the noise can be considered valid. Unfortunately, the frequency Fm cannot be pushed too far (200 MHz is a good compromise) and the BW cannot be reduced too much because low BW means low scanning speed/high total scanning time.


Normalized simulation of an DIGITAL Lock-In Amplifier


NORMALIZED DESIGN SPECIFICATIONS (DIGITAL LOCK-IN)

The sampling time Ts=50 ns (Fs=20 MHz) satisfy the Nyquist/Shannon criteria (Fs>2Fo) by a large factor (10 times, 20 sampling points in the 1MHz/1 us period).

Using 8 bit quantization/accuracy everywhere, the simulation of the digital lock-in is not very different from the analog one (fig. 7-8). This effect is justified by the very low SNR_input respect the dynamic range/accuracy of the quantizers (8 bits, 48 dB) used. Only the output noise (SNR_Output) is increased by a 1.5 factor (not so much).

In a perfect (ideal), fully digital lock-in, if the disturbing signal is Gaussian white noise and the input SNR is low, an high accuracy/high dynamic range/lot-of-bits ADC, is a waste of resource. Lot-of-bits ADC is required when a relatively noiseless (clean) input signal must polished up to “crystal clear” because we need high accuracy measures.


Conclusions

The analog simulations have shown the consistency of the numerical results with the theoretical previsions. Models and algorithms can be considered reasonably faithfully.

Analog simulations have been modified to take in account the sampling of signals with finite numbers of bit. These simulations have produced interesting results that can be used to optimize the design of digital lock-in amplifiers using ADC/DAC and FPGA.

System level simulation software like Scicos or Simulink can be effectively used to test ideas _before_ start to build a – very resource intensive - physical prototype. They can be used to validate the theory on models that take in account the limits of the physical systems.

The model-based approach has shown its effectiveness also in the field of lock-in design.

Finally, numerical simulations can be used to optimize the performance of physical prototypes, allowing the access to internal variables not easily accessible using physical diagnostic instruments. This is particularly important at frequencies above 100 MHz where direct access probes cannot be used on analog circuits without perturb its.


Simulation Software All the simulations have been performed using SCICOS, the dynamic systems simulator developed in INRIA and available (free) here: www.scicos.org. This Scicos distribution (ScicosLab 4.4.2, http://www.scicoslab.org) is not completely Open Source/Free Software because still pending intellectual propriety issues.

A new, improved version of SCICOS is available inside NSP (New Scilab Project) here (https://cermics.enpc.fr/~jpc/nsp-tiddly/). This new version of Scilab and Scicos is x2/x10 times faster than the previous one and the complete source code is available under GLP-2 (and-up) license.

A professional version of Scicos is available from Altair (http://www.altair.com ). Trial licenses are available on request.

Similar simulations can be performed also with MATLAB and Simulink (still “work in progress” at this date).

http://www.scicos.org/





http://www.scicoslab.org/








https://cermics.enpc.fr/~jpc/nsp-tiddly/










http://www.altair.com/

http://www.altair.com/


Low frequency (0.1-5 MHz) prototype (September 2016)


High frequency (180-200 MHz) prototype (November 2016)

Presentazione standard di PowerPoint · Modelling and Simulation for lock-in amplifiers TYPICAL APPLICATION DIAGRAM LOCK-IN In this configuration the PLL section is not required because

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