The World Leader in High Performance Signal Processing Solutions Proprietary Information Proprietary Information “Predicting Circuit ESD Performance Through SPICE-type Simulations” Yuanzhong (Paul) Zhou, Thorsten Weyl & Jean-Jacques (J-J) Hajjar Analog Devices Inc. IEEE Electron Device Colloquium University of Central Florida February 21-22, 2008
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The World Leader in High Performance Signal Processing Solutions
Proprietary InformationProprietary Information
“Predicting Circuit ESD Performance Through SPICE-type Simulations”
Yuanzhong (Paul) Zhou,Thorsten Weyl &
Jean-Jacques (J-J) Hajjar
Analog Devices Inc.
IEEE Electron Device ColloquiumUniversity of Central Florida
February 21-22, 2008
2 —Analog Devices Proprietary Information—
ESD high on Pareto chart of reliability product returns from customers
Predicting ESD performance is very compelling:1) Design tool prior to manufacturing
2) Design verification
3) Post-mortem failure troubleshooting tool
MOTIVATION
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What is ESD?
Circuit Simulation Consideration
Compact Modeling Approaches and Modeling Verification
ESD Circuit Simulation Examples
Concluding Remarks
OUTLINE
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ESD: Electrostatic Discharge
Cause: Tribo-electric charge transfer
Characteristics
High energy resulting
Large currents
High voltages
Short in duration (typically <1 to over 100 nano-seconds)
Modeling Strategy1) Modify standard Compact models2) Customized Model
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Snapback in ESD Devices
Operating I-V Regions of MOS Devices1) Linear Region2) Saturation Region3) Avalanche Region 4) Snapback Region5) Failure Region
Vt1 represents the “snapback effect”trigger voltage
Devices (MOS) operating in “snapback” mode carries more current per unit width
VDRAIN
I DR
AIN
DEVICE
REGION-1
0
REGION-2
REGION-3
REGION-4
GATE BIAS
Vt1
REGION-5
FAILS
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Snapback Effect in MOS is due to the Parasitic BJT, triggered by the substrate current (ISUB).
Snapback in MOS Devices
N+N+P+
POLY
VS
VG
VD
PSUB
STI STISTI
ISUB
N+N+P+
POLY
VS
VG
VD
PSUB
STI STISTI
RSUB
LNPN
IC
ISD
ISUB
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Substrate current as function of VDS, VGS
and VBS
Due to impact ionization in Drain/Backgatedepletion layer.
Avalanche current multiplication factor is different before and after snapback
Displacement current (dV/dt) through Drain/Backgate junction
Gate induced drain leakage (GIDL)
Critical Effects in Snapback Modeling
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Standard MOS and BJT models.
An explicit current source which is a function of VGSand VDS
(dV/dt) effect, GIDL and separate M for MOS and BJT are included in some models by adding equations.
The implementation of the models includes C code and behavioral languages (Verilog-A)
Previous Snapback Models
G
DS
B
RdRs
Rsub
Igen
Ic
Ids
Id=Ids+Ic+Igen
Isub
Ib
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Model for MOS under ESD Stress
New approach eliminates the current source of previous models.
Model constructed of standard BJT (Mextram) and MOS (BSIM4) devices.
Models intrinsically includes all major physical phenomenon presented.
Source/Backgate and Drain/Backgate Junction Diodes for completeness.
G
BSIM4Mextram
Ib
BiIsub_total
Rsub
Isub+Igidl
Id=Id'+Ic
Ic
Ids
Id'
S
D
B
S/B diode
D/B diode
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Model Verification
Transmission Line Pulse measurement:
Quasi-static
Transient
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Transmission Line Pulse (TLP)Measurement Setup
+-
High voltage supply
Transmission Line; Z0 = 50
DUT
Termination
VDUT (t)
IDUT (t)
Current Probe
100 ns
t rise
VTLP
ITLP
VTLP
ITLP
ZT1
ZT2 ZATT
.......
time
I
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Why Transmission Line Pulse?
0
1
2
0 100 200TIME (nsec)
CURRENT (A)
2,000V HBM
TLP
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Model Verification Snapback effect was simulated with transient simulation. Voltage Pulse Sequence (100ns) were used as the Input. The stabilized VD and ID were measured as the simulation
results (~80ns).
Schematic of Snapback Simulation(R=0 for ggNMOS)Voltage
source
50
R
TLP DUT
ID
VD
VHD
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Simulation Results vs. TLP MeasurementA ggNMOS device
50
Id Vd GGNMOS Configuration
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Deep submicron CMOS Model Scalability
W = 300m 0.18 < L < 0.30 m Stripes = 12 Wrap-around backgate contact
0
0.2
0.4
0.6
0.8
1
0 1 2 3 4 5 6 7 8VOLTAGE (V)
0
0.2
0.4
0.6
0.8
10
0.2
0.4
0.6
0.8
1 CURRENT (A)
L=0.18m
L=0.30m
L=0.20m
VB3
VB2
VB1
MOS CHARACTERISTICS & MODEL
G
S
D
BG
GGNMOS
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0
0.2
0.4
0.6
0.8
1
0 1 2 3 4 5 6 7 8VOLTAGE (V)
0
0.2
0.4
0.6
0.8
1 CURRENT (A)
GCNMOSR=10k
GGNMOSR=0
VB2
VB1
Deep submicron CMOS W/L = 300/0.18m; Stripes = 12
GGNMOS GCNMOS
100ns TLP: Sim vs. msmt
MOS CHARACTERISTICS & MODEL
R=10k G
S
D
BGG
S
D
BG
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SCR Devices
N+ P+ P+
Nwell
Rnwell Pwell
Rpwell
CATHODE ANODE
N+
Rnwell
Rpwell
npn
pnp
CATHODE
ANODE
N+ N+ N+ P+ P+
Nwell
Rnwell Pwell
Rpwell
CATHODE ANODE
Rnwell
Rpwell
npn
pnpnmos
CATHODE
ANODE
SCR LVTSCR
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Macro Model for LVTSCR Similar approach to MOS New model consists of four components: An NMOS modeled by BSIM4 A four terminal NPN modeled by Mextram Two resistors
BSIM4
MEXTRAM
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Key effects in New LVTSCR Macro Model
The PNP is modeled by the parasitic BJT in the 4 terminal NPN modeled by a Mextram-like model
Current sources for avalanche and GIDL are intrinsically built in MOS and BJT models
Decoupled multiplication factors for BJT and MOS are included in IAVL and ISUB respectively
The dV/dt effect is modeled by Collector/Base junction capacitance of the BJT
IGEN = IAVL + ISUB + IGIDL
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CMOS: SCR-1
100nsec TLP Pulse Different pulse rise-time
SCR CHARACTERISTICS & MODEL
VDUT (t)
IDUT (t)
100 ns
t rise VTLP
ITLP
0
0.2
0.4
0.6
0.8
1.0
1.2
0 1 2 3 4 5 6 7 8VOLTAGE (V)
0
0.2
0.4
0.6
0.8
1.0
1.2
0
0.2
0.4
0.6
0.8
1.0
1.2
=10nsec.
=2nsec.
=0.2nsec.
VB1
VB2
VB3
CURRENT (A)
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-5
0
5
10
15
20
25
0
10
20
30
40
0 1 2 3 4 5 6 7 8TIME (nsec.)
CU
RR
EN
T(A
)V
OL
TA
GE
(V)
SIMULATED
MEASURED
SCR CHARACTERISTICS & MODEL
CMOS: SCR-1
VFTLP: SCR ADICE Simulation vs. measurement
33 —Analog Devices Proprietary Information—
CIRCUIT SIMULATIONHuman Body Model (HBM)
Simulates the discharge from the finger of a standing person