-
1®
IVC102
IIN
VB
1
2
3
4
5
6
11 12 13
DigitalGround
AnalogGround
Logic Low closes switches
9
10
14
VO
V+
V–
S1 S2
IonizationChamber
Photodiode
60pF
30pF
10pF
S1
C1
C2
C3
S2
International Airport Industrial Park • Mailing Address: PO Box
11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. •
Tucson, AZ 85706Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable:
BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product
Info: (800) 548-6132
®
PRECISION SWITCHED INTEGRATORTRANSIMPEDANCE AMPLIFIER
APPLICATIONS● PRECISION LOW CURRENT MEASUREMENT
● PHOTODIODE MEASUREMENTS
● IONIZATION CHAMBER MEASUREMENTS● CURRENT/CHARGE-OUTPUT
SENSORS
● LEAKAGE CURRENT MEASUREMENT
IVC102
FEATURES● ON-CHIP INTEGRATING CAPACITORS
● GAIN PROGRAMMED BY TIMING● LOW INPUT BIAS CURRENT: 750fA
max
● LOW NOISE
● LOW SWITCH CHARGE INJECTION
● FAST PULSE INTEGRATION
● LOW NONLINEARITY: 0.005% typ
● 14-PIN DIP, SO-14 SURFACE MOUNT
DESCRIPTIONThe IVC102 is a precision integrating amplifier
withFET op amp, integrating capacitors, and low leakageFET
switches. It integrates low-level input current fora
user-determined period, storing the resulting voltageon the
integrating capacitor. The output voltage can beheld for accurate
measurement. The IVC102 providesa precision, lower noise
alternative to conventionaltransimpedance op amp circuits that
require a veryhigh value feedback resistor.
The IVC102 is ideal for amplifying low-level sensorcurrents from
photodiodes and ionization chambers.The input signal current can be
positive or negative.
TTL/CMOS-compatible timing inputs control the inte-gration
period, hold and reset functions to set theeffective transimpedance
gain and to reset (discharge)the integrator capacitor.
Package options include 14-Pin plastic DIP and
SO-14surface-mount packages. Both are specified for the–40°C to
85°C industrial temperature range.
© 1996 Burr-Brown Corporation PDS-1329A Printed in U.S.A. June,
1996
0V
Hold Integrate Hold Reset
Positive or NegativeSignal Integration
S1
S2
IIN(t)VO =–1 ∫ dtCINT
SBFS009
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2®
IVC102
The information provided herein is believed to be reliable;
however, BURR-BROWN assumes no responsibility for inaccuracies or
omissions. BURR-BROWN assumesno responsibility for the use of this
information, and all use of such information shall be entirely at
the user’s own risk. Prices and specifications are subject to
changewithout notice. No patent rights or licenses to any of the
circuits described herein are implied or granted to any third
party. BURR-BROWN does not authorize or warrantany BURR-BROWN
product for use in life support devices and/or systems.
NOTES: (1) Standard test timing: 1ms integration, 200µs hold,
100µs reset. (2) Hold mode output voltage after 1ms integration of
zero input current. Includes opamp offset voltage, integration of
input error current and switch charge injection effects.
SPECIFICATIONSAt TA = +25°C, VS = ±15V, RL = 2kΩ, CINT = C1 + C2
+ C3, 1ms integration period(1), unless otherwise specified.
IVC102P, U
PARAMETER CONDITIONS MIN TYP MAX UNITS
TRANSFER FUNCTION VO = –(IIN)(TINT)/CINTGain Error CINT = C1 +
C2 + C3 ±5 +25/–17 %
vs Temperature ±25 ppm/°CNonlinearity VO = ±10V ±0.005 %Input
Current Range ±100 µAOffset Voltage(2) IIN = 0, CIN = 50pF –5 ±20
mV
vs Temperature ±30 µV/°Cvs Power Supply VS = +4.75/–10 to
+18/–18V 150 750 µV/V
Droop Rate, Hold Mode –1 nV/µs
OP AMPInput Bias Current S1, S2 Open –100 ±750 fA
vs Temperature See Typical CurveOffset Voltage (Op Amp VOS) ±0.5
±5 mV
vs Temperature ±5 µV/°Cvs Power Supply VS = +4.75/–10 to
+18/–18V 10 100 µV/V
Noise Voltage f = 1kHz 10 nV/√Hz
INTEGRATION CAPACITORSC1 + C2 + C3 80 100 120 pF
vs Temperature ±25 ppm/°CC1 10 pFC2 30 pFC3 60 pF
OUTPUTVoltage Range, Positive RL = 2kΩ (V+)–3 (V+)–1.3 V
Negative RL = 2kΩ (V–)+3 (V–)+2.6 VShort-Circuit Current ±20
mACapacitive Load Drive 500 pFNoise Voltage See Typical Curve
DYNAMIC CHARACTERISTICOp Amp Gain-Bandwidth 2 MHzOp Amp Slew
Rate 3 V/µsReset
Slew Rate 3 V/µsSettling Time, 0.01% 10V Step 6 µs
DIGITAL INPUTS (TTL/CMOS Compatible)VIH (referred to digital
ground) (Logic High) 2 5.5 VVIL (referred to digital ground) (Logic
Low) –0.5 0.8 VIIH VIH = 5V 2 µAIIL VIL = 0V 0 µASwitching Time 100
ns
POWER SUPPLYVoltage Range: Positive +4.75 +15 +18 V
Negative –10 –15 –18 VCurrent: Positive 4.1 5.5 mA
Negative –1.6 –2.2 mAAnalog Ground –0.2 mADigital Ground –2.3
mA
TEMPERATURE RANGEOperating Range –40 85 °CStorage –55 125
°CThermal Resistance, θJA
DIP 100 °C/WSO-14 150 °C/W
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3®
IVC102
ELECTROSTATICDISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD.
Burr-Brownrecommends that all integrated circuits be handled
withappropriate precautions. Failure to observe proper handlingand
installation procedures can cause damage.
ESD damage can range from subtle performance degrada-tion to
complete device failure. Precision integrated circuitsmay be more
susceptible to damage because very smallparametric changes could
cause the device not to meet itspublished specifications.
ABSOLUTE MAXIMUM RATINGSSupply Voltage, V+ to V–
....................................................................
36VLogic Input Voltage
......................................................................
V– to V+Output Short Circuit to Ground
............................................... ContinuousOperating
Temperature ................................................. –40°C
to +125°CStorage Temperature
..................................................... –55°C to
+125°CLead Temperature (soldering, 10s)
................................................. 300°C
PIN CONNECTIONS
Top View 14-Pin DIP/SO-14 Surface Mount
PACKAGE INFORMATION
PACKAGE DRAWINGPRODUCT PACKAGE NUMBER (1)
IVC102P 14-Pin DIP 010IVC102U SO-14 Surface Mount 235
NOTE: (1) For detailed drawing and dimension table, please see
end of datasheet, or Appendix D of Burr-Brown IC Data Book.
V+
Digital Ground
S2
S1
VO
V–
NC
Analog Ground
IIN
–In
C1
C2
C3
NC
NC = No Internal Connection Connect to Analog Ground for Lowest
Noise
14
13
12
11
10
9
8
1
2
3
4
5
6
7
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4®
IVC102
10 100 1000
CIN (pF)
TOTAL OUTPUT NOISE vs CIN1000
100
10
1
Noi
se V
olta
ge (
µVrm
s)
rms Variationof 100 MeasurementCycles, TINT = 1ms.
CINT = 10pF
CINT = 30pF
CINT = 100pF
CINT = 300pF
CINT = 1000pF
Reset Mode, S1 Open, S2 Closed.
TYPICAL PERFORMANCE CURVESAt TA = +25°C, VS = ±15V, RL = 2kΩ,
CINT = C1 + C2 + C3, 1ms integration period, unless otherwise
specified.
–50 –25 0 25 50 75 100 125
Temperature (°C)
INPUT BIAS CURRENT vs TEMPERATURE100p
10p
1p
100f
10f
Inpu
t Bia
s C
urre
nt (
A)
S1, S2 Open
0 100 200 300 400 500 600 700 800 900 1000
CINT (pF)
RESET TIME vs CINT30
25
20
15
10
5
0
Res
et T
ime
(µs)
Time Required toReset from ±10Vto 0V.
0.01%
1%
10 100 1000
Input Capacitance, CIN (pF)
S1 CHARGE INJECTION vs INPUT CAPACITANCE2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
Cha
rge
Inje
ctio
n, ∆
Q (
pC)
100pF
∆VO =∆Q
100pF
S1
CIN
10 100 1000
Input Capacitance, CIN (pF)
S2 CHARGE INJECTION vs INPUT CAPACITANCE1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Cha
rge
Inje
ctio
n, ∆
Q (
pC)
(V+) = +18V
(V+) = +15V
(V+) = +4.75V
100pF
∆VO =∆Q
100pF
CIN
S2
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5®
IVC102
Charge Injectionof S2
Op Amp VOS+
IIN • RS2
0V
Integrate
(S2 Open)
T1
0V
S2
VO
T2
10µsReset
10µsReset
IIN
Photodiode
60pF
30pF
10pF
0.1µF
0.1µF
1
2
3
4
5
6
11 12 13
10 VO
14
V++15V
LogicHigh(+5V)
S1
C1
C2
C3
S2DigitalGround
AnalogGround
S2
9
–15VV–
DigitalData
SamplingA/D
Converter
See timingsignal below
APPLICATION INFORMATIONFigure 1 shows the basic circuit
connections to operate theIVC102. Bypass capacitors are shown
connected to thepower supply pins. Noisy power supplies should be
avoidedor decoupled and carefully bypassed.
The Analog Ground terminal, pin 1, is shown internallyconnected
to the non-inverting input of the op amp. Thisterminal connects to
other internal circuitry and should beconnected to ground.
Approximately 200µA flows out ofthis terminal.
Digital Ground, pin 13, should be at the same voltagepotential
as analog ground (within 100mV). Analog andDigital grounds should
be connected at some point in thesystem, usually at the power
supply connections to thecircuit board. A separate Digital Ground
is provided so thatnoisy logic signals can be referenced to
separate circuitboard traces.
Integrator capacitors C1, C2 and C3 are shown connected
inparallel for a total CINT = 100pF. The IVC102 can be usedfor a
wide variety of integrating current measurements. Theinput signal
connections and control timing and CINT valuewill depend on the
sensor or signal type and other applica-tion details.
BASIC RESET-AND-INTEGRATE MEASUREMENT
Figure 1 shows the circuit and timing for a simple
reset-and-integrate measurement. The input current is connected
di-rectly to the inverting input of the IVC102, pin 3. Inputcurrent
is shown flowing out of pin 3, which produces apositive-going ramp
at VO. Current flowing into pin 3 wouldproduce a negative-going
ramp.
A measurement cycle starts by resetting the integrator
outputvoltage to 0V by closing S2 for 10µs. Integration of the
inputcurrent begins when S2 opens and the input current begins
tocharge CINT. VO is measured with a sampling a/d converterat the
end of an integration period, just prior to the next resetperiod.
The ideal result is proportional to the average inputcurrent (or
total accumulated charge).
Switch S2 is again closed to reset the integrator output to
0Vbefore the next integration period.
This simple measurement arrangement is suited to
manyapplications. There are, however, limitations to this
basicapproach. Input current continues to flow through S2 duringthe
reset period. This leaves a small voltage on CINT equalto the input
current times RS2, the on-resistance of S2,approximately 1.5kΩ.
FIGURE 1. Reset-and Integrate Connections and Timing.
Figure 1b
Figure 1a
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6®
IVC102
CINT
for constant IIN, at the end of TINT
VO = –IINTINTCINT
VO
IIN
IIN(t)VO =–1 ∫ dtCINT
In addition, the offset voltage of the internal op amp andcharge
injection of S2 contribute to the voltage on CINT at thestart of
integration.
Performance of this basic approach can be improved bysampling VO
after the reset period at T1 and subtracting this
measurement from the final sample at T2. Op amp offsetvoltage,
charge injection effects and I•RS2 offset voltage onS2 are removed
with this two-point measurement. The effec-tive integration period
is the time between the two measure-ments, T2-T1.
COMPARISON TO CONVENTIONAL TRANSIMPEDANCE AMPLIFIERS
With the conventional transimpedance amplifier circuitof Figure
2a, input current flows through the feedbackresistor, RF, to create
a proportional output voltage.
VO = –IIN RFThe transimpedance gain is determined by RF. Very
largevalues of RF are required to measure very small signalcurrent.
Feedback resistor values exceeding 100MΩ arecommon.
The IVC102 (Figure 2b) provides a similar function,converting an
input current to an output voltage. Theinput current flows through
the feedback capacitor, CINT,charging it at a rate that is
proportional to the inputcurrent. With a constant input current,
the IVC102’soutput voltage is
VO = –IIN TINT/ CINT
after an integration time of TINT.
VO is proportional to the integration time, TINT, andinversely
proportional to the feedback capacitor, CINT.The effective
transimpedance gain is TINT /CINT. Ex-tremely high gain that would
be impractical to achievewith a conventional transimpedance
amplifier can beachieved with small integration capacitor values
and/orlong integration times. For example the IVC102 withCINT =
100pF and TINT = 100ms provides an effectivetransimpedance of 1GΩ.
A 10nA input current wouldproduce a 10V output after 100ms
integration.
The integrating behavior of the IVC102 reduces noise byaveraging
the input noise of the sensor, amplifier, andexternal sources.
Conventional Transimpedance AmplifierFigure 2a
Integrating Transimpedance AmplifierFigure 2b
RF
VO = –IIN RF
VO
IIN
CURRENT-OUTPUT SENSORS
Figure 3 shows a model for many current-output sensorssuch as
photodiodes and ionization chambers. Sensor outputis a
signal-dependent current with a very high source resis-tance. The
output is generally loaded into a low impedance
FIGURE 2. Comparison to a Conventional Transimpedance
Amplifier.
so that the terminal voltage is kept very low. Typical
sensorcapacitance values range from 10pF to over 100pF.
Thiscapacitance plays a key role in operation of the switched-input
measurement technique (see next section).
Provides time-continuous outputvoltage proportional to IIN.
Output voltage after integration period isproportional to
average IIN throughoutthe period.
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7®
IVC102
60pF
30pF
10pF
0.1µF
0.1µF
1
I
PhotodiodeSensor
R C
2
3
4
5
6
11
I: Signal - Dependent CurrentR: Sensor ResistanceC: Sensor
Capacitance
12 13
10 VO
14
V++15V
S1
S1
C1
C2
C3
S2
S2
9
–15VV–
DigitalData
A/DConverter
See timingsignals below
3a
3b
3c
Charge transferredfrom sensor Cto CINT.
A
A
B
B
Transfer FunctionOffset Voltage
Ramp due toinput bias current
(exaggerated).
EffectiveSignal Integration
Period, TS
VO waveform withapprox. half-scale input current.
VO waveform withzero input current.
∆QS1 Opening
0V
0V
0V
VO
S2
S1
VO
0V
+10mV
–10mV
10µsHold
10µsReset
10µsHold
10µsReset
10µsPre-Int.
Hold
∆QS2 Opening
∆QS1 Closing
Op AmpVOS
(S1 Open) (S1 Closed)
(S2 Open)
FIGURE 3. Switched-Input Measurement Technique.
Input connections and timing are shown in Figure 3.
The timing diagram, Figure 3b, shows that S1 is closed onlywhen
S2 is open. During the short period that S1 is open(30µs in this
timing example), any signal current producedby the sensor will
charge the sensor’s source capacitance.This charge is then
transferred to CINT when S1 is closed. Asa result, no charge
produced by the sensor is lost and theinput signal is continuously
integrated. Even fast inputpulses are accurately integrated.
SWITCHED-INPUT MEASUREMENT TECHNIQUE
While the basic reset-and-integrate measurement arrange-ment in
Figure 1 is satisfactory for many applications, theswitched-input
timing technique shown in Figure 3 hasimportant advantages. This
method can provide continuousintegration of the input signal.
Furthermore, it can hold theoutput voltage constant after
integration for stable conver-sion (desirable for a/d converter
without a sample/hold).
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8®
IVC102
The input current, IIN, is shown as a conventional
currentflowing into pin 2 in this diagram but the input current
couldbe bipolar (positive or negative). Current flowing out of pin2
would produce a positive-ramping VO.
The timing sequence proceeds as follows:
Reset PeriodThe integrator is reset by closing switch S2 with S1
open. A10µs reset time is recommended to allow the op amp to slewto
0V and settle to its final value.
Pre-Integration HoldS2 is opened, holding VO constant for 10µs
prior to integra-tion. This pre-integration hold period assures
that S2 is fullyopen before S1 is closed so that no input signal is
lost. Aminimum of 1µs is recommended to avoid switching over-lap.
The 10µs hold period shown in Figure 3b also allows ana/d converter
measurement to be made at point A. Thepurpose of this measurement
at A is discussed in the “OffsetErrors” section.
Integration on C INTIntegration of the input current on CINT
begins when S1 isclosed. An immediate step output voltage change
occurs asthe charge that was stored on the input sensor capacitance
istransferred to CINT. Although this period of charging CINToccurs
only while S1 is closed, the charge transferred as S1is closed
causes the effective integration time to be equal tothe complete
conversion period—see Figure 3b.
The integration period could range from 100µs to manyminutes,
depending on the input current and CINT value.While S1 is closed,
IIN charges CINT, producing a negative-going ramp at the integrator
output voltage, VO. The outputvoltage at the end of integration is
proportional to theaverage input current throughout the complete
conversioncycle, including the integration period, reset and both
holdperiods.
Hold PeriodOpening S1 halts integration on CINT. Approximately
5µsafter S1 is opened, the output voltage is stable and can
bemeasured (at point B). The hold period is 10µs in thisexample.
CINT remains charged until a S2 is again closed, toreset for the
next conversion cycle.
In this timing example, S1 is open for a total of 30µs.
Duringthis time, signal current from the sensor charges the
sensorsource capacitance. Care should be used to assure that
thevoltage developed on the sensor does not exceed approxi-mately
200mV during this time. The IIN terminal, pin 2, isinternally
clamped with diodes. If these diodes forward bias,signal current
will flow to ground and will not be accuratelyintegrated.
A maximum of 333nA signal current could be accuratelyintegrated
on a 50pF sensor capacitance for 30µs before200mV would be
developed on the sensor.
IMAX = (50pF) (200mV) / 30µs = 333nA
OFFSET ERRORS
Figure 3c shows the effect on VO due to op amp input
offsetvoltage, input bias current and switch charge injection.
Itassumes zero input current from the sensor. The variousoffsets
and charge injection (∆Q) jumps shown are typical ofthat seen with
a 50pF source capacitance. The specified“transfer function offset
voltage” is the voltage measuredduring the hold period at B.
Transfer function offset voltageis dominated by the charge
injection of S2 opening and opamp VOS. The opening and closing
charge injections of S1are very nearly equal and opposite and are
not significantcontributors.
Note that using a two-point difference measurement at Aand B can
dramatically reduce offset due to op amp VOS andS2 charge
injection. The remaining offset with this B-Ameasurement is due to
op amp input bias current chargingCINT. This error is usually very
small and is exaggerated inthe figure.
DIGITAL SWITCH INPUTS
The digital control inputs to S1 and S2 are compatible
withstandard CMOS or TTL logic. Logic input pins 11 and 12are high
impedance and the threshold is approximately 1.4Vrelative to
Digital Ground, pin 13. A logic “low” closes theswitch.
Use care in routing these logic signals to their respectiveinput
pins. Capacitive coupling of logic transitions to sensi-tive input
nodes (pins 2 through 6) and to the positive powersupply (pin 14)
will dramatically increase charge injectionand produce errors.
Route these circuit board traces over aground plane (digital
ground) and route digital ground tracesbetween logic traces and
other critical traces for lowestcharge injection. See Figure 4.
5V logic levels are generally satisfactory. Lower voltagelogic
levels may help reduce charge injection errors, de-pending on
circuit layout. Logic high voltages greater than5.5V, or higher
than the V+ supply are not recommended.
FIGURE 4. Circuit Board Layout Techniques.
•
••
•
•
•
•
•
•
•
•
•
•
•
•
Input trace guardedall the way to sensor.
Switch logic inputsguarded by digitalground.
AnalogGround
DigitalGround
Pins 7 and 8 have no internal connection but are connected
toground for lowest noise pickup.
V+
Input nodesguarded byanalog ground.
V–
VO
S1
S2
14
87
1
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9®
IVC102
CHOOSING CINTInternal capacitors C1, C2 and C3 are high quality
metal/oxide types with low leakage and excellent dielectric
char-acteristics. Temperature stability is excellent—see
typicalcurve. They can be connected for CINT = 10pF, 30pF,
40pF,60pF, 70pF, 90pF or 100pF. Connect unused internal ca-pacitor
pins to analog ground. Accuracy is ±20%, whichdirectly influences
the gain of the transfer function.
A larger value external CINT can be connected between pins3 and
10 for slower/longer integration. Select a capacitortype with low
leakage and good temperature stability.Teflon, polystyrene or
polypropylene capacitors generallyprovide excellent leakage,
temperature drift and voltagecoefficient characteristics. Lower
cost types such as NPOceramic, mica or glass may be adequate for
many applica-tions. Larger values for CINT require a longer reset
time—seetypical curves.
FREQUENCY RESPONSE
Integration of the input signal for a fixed period produces
adeep null (zero response) at the frequency 1/TINT and
itsharmonics. An ac input current at this frequency (or
itsharmonics) has zero average value and therefore producesno
output. This property can be used to position responsenulls at
critical frequencies. For example, a 16.67ms integra-tion period
produces response nulls at 60Hz, 120Hz, 180Hz,etc., which will
reject ac line frequency noise and its har-monics. Response nulls
can be positioned to reduce interfer-ence from system clocks or
other periodic noise.Response to all frequencies above f = 1/TINT
falls at –20dB/decade. The effective corner frequency of this
single-poleresponse is approximately 1/2.8TINT.
For the simple reset-and-integrate measurement technique,TINT is
equal to the to the time that S2 is open. The switched-input
technique, however, effectively integrates the inputsignal
throughout the full measurement cycle, including thereset period
and both hold periods. Using the timing shownin Figure 3, the
effective integration time is 1/Ts, where Tsis the repetition rate
of the sampling.
INPUT IMPEDANCE
The input impedance of a perfect transimpedance circuit iszero
ohms. The input voltage ideally would be zero for anyinput current.
The actual input voltage when directly drivingthe integrator input
(pin 3) is proportional to the output slewrate of the integrator. A
1V/µs slew rate produces approxi-mately 100mV at pin 3. The input
of the integrator can bemodeled as a resistance:
RIN = 10–7/CINT
with RIN in Ω and CINT in Farads.
Using the internal CINT = C1 + C2 + C3 = 100pF
RIN = 10–7/100pF = 1kΩ
(2)
(3)
INPUT BIAS CURRENT ERRORS
Careful circuit board layout and assembly techniques arerequired
to achieve the very low input bias current capabilityof the IVC102.
The critical input connections are at groundpotential, so analog
ground should be used as a circuit boardguard trace surrounding all
critical nodes. These includepins 2, 3, 4, 5 and 6. See Figure
4.
Input bias current increases with temperature—see
typicalperformance curve Input Bias Current vs Temperature.
HOLD MODE DROOP
Hold-mode droop is a slow change in output voltage prima-rily
due to op amp input bias current. Droop is specifiedusing the
internal CINT = 100pF and is based on a –100fAtypical input bias
current. Current flows out of the invertinginput of the internal op
amp.
With CINT = 100pF, the droop rate is typically only1nV/µs—slow
enough that it rarely contributes significanterror at moderate
temperatures.
Since the input bias current increases with temperature,
thedroop rate will also increase with temperature. The drooprate
will approximately double for each 10°C increase injunction
temperature—see typical curves.
Droop rate is inversely proportional to CINT. If an
externalintegrator capacitor is used, a low leakage capacitor
shouldbe selected to preserve the low droop performance of
theIVC102.
INPUT CURRENT RANGE
Extremely low input currents can be measured by integrat-ing for
long periods and/or using a small value for CINT.Input bias current
of the internal op amp is the primarysource of error.
Larger input currents can be measured by increasing thevalue of
CINT and/or using a shorter integration time. Inputcurrents greater
than 200µA should not be applied to the pin2 input, however. The
approximately 1.5kΩ series resistanceof S1 will create an input
voltage at pin 2 that will begin toforward-bias internal protection
clamp diodes. Any currentthat flows through these protection diodes
will not be accu-rately integrated. See “Input Impedance” section
for moreinformation on input current-induced voltage.
Input current greater than 200µA can, however, be con-nected
directly to pin 3, using the simple reset-integratetechnique shown
in Figure 1. Current applied at this inputcan be externally
switched to avoid excessive I•R voltageacross S2 during reset.
Inputs up to 5mA at pin 3 can beaccurately integrated if CINT is
made large enough to limitslew rate to less than 1V/µs. A 5mA input
current wouldrequire CINT = 5nF to produce a 1V/µs slew rate. The
inputcurrent appears as load current to the internal op
amp,reducing its ability to drive an external load.
Droop Rate = –100fACINT
Teflon E. I. Du Pont de Nemours & Co.
-
10®
IVC102
The input resistance seen at pin 2 includes an additional1.5kΩ,
the on-resistance of S1. The total input resistance isthe sum of
the switch resistance and RIN, or 2.5kΩ in thisexample.
Slew rate limit of the internal op amp is approximately3V/µs.
For most applications, the slew rate of VOUT shouldbe limited to
1V/µs or less. The rate of change is propor-tional to IIN and
inversely proportional to CINT:
This can be important in some applications since the
slew-induced input voltage is applied to the sensor or
signalsource. The slew-induced input voltage can be reduced
byincreasing CINT, which reduces the output slew rate.
NONLINEARITY
Careful nonlinearity measurements of the IVC102 yieldtypical
results of approximately ±0.005% using the internalinput capacitors
(CINT = 100pF). Nonlinearity will be de-graded by using an external
integrator capacitor with poorvoltage coefficient. Performance with
the internal capacitorsis typically equal or better than the
sensors it is used tomeasure. Actual application circuits with
sensors such as aphotodiode may have other sources of
nonlinearity.
1/10TINT 1/TINT 10/TINT
● ●●
–20dB/decadeslope
Frequency
0
–10
–20
–30
–40
–50
Fre
quen
cy R
espo
nse
(dB
)
Corner atf = 0.32/TINT
–3dB atf = 0.44/TINT
FIGURE 5. Frequency Response of Integrating Converter.
Slew Rate = IINCINT
-
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status(1)
Package Type PackageDrawing
Pins PackageQty
Eco Plan(2)
Lead finish/Ball material
(6)
MSL Peak Temp(3)
Op Temp (°C) Device Marking(4/5)
Samples
IVC102U ACTIVE SOIC D 14 50 RoHS & Green NIPDAU
Level-3-260C-168 HR -40 to 125 IVC102U
IVC102U/2K5 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU
Level-3-260C-168 HR -40 to 125 IVC102U
(1) The marketing status values are defined as follows:ACTIVE:
Product device recommended for new designs.LIFEBUY: TI has
announced that the device will be discontinued, and a lifetime-buy
period is in effect.NRND: Not recommended for new designs. Device
is in production to support existing customers, but TI does not
recommend using this part in a new design.PREVIEW: Device has been
announced but is not in production. Samples may or may not be
available.OBSOLETE: TI has discontinued the production of the
device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that
are compliant with the current EU RoHS requirements for all 10 RoHS
substances, including the requirement that RoHS substancedo not
exceed 0.1% by weight in homogeneous materials. Where designed to
be soldered at high temperatures, "RoHS" products are suitable for
use in specified lead-free processes. TI mayreference these types
of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to
mean products that contain lead but are compliant with EU RoHS
pursuant to a specific EU RoHS exemption.Green: TI defines "Green"
to mean the content of Chlorine (Cl) and Bromine (Br) based flame
retardants meet JS709B low halogen requirements of
-
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
-
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device PackageType
PackageDrawing
Pins SPQ ReelDiameter
(mm)
ReelWidth
W1 (mm)
A0(mm)
B0(mm)
K0(mm)
P1(mm)
W(mm)
Pin1Quadrant
IVC102U/2K5 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Dec-2020
Pack Materials-Page 1
-
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width
(mm) Height (mm)
IVC102U/2K5 SOIC D 14 2500 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Dec-2020
Pack Materials-Page 2
-
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