Práctica 7.pdf

Prctica 7

Equipo 2

Alumno(s): Jos Ricardo Gutirrez Urza, Juan Jos Negrn Granados, Jorge Luis Koyoc Koyoc.

Carrera: Licenciatura en Ingeniera en Computacin.

Maestro(a): Anabel Martn Gonzlez.

Materia: Sistemas Digitales.

Escuela: UADY Facultad de Matemticas.

Fecha: 24-04-15.

Problem 1. Create a NAND basic cell in the Xilinx tools using structural VHDL methods. Add a 1ns gate delay to both NAND gates (for both rising and falling transitions). Label inputs S and R and the outputs Q and QN as appropriate. Create a VHDL test bench to simulate the circuit, driving the inputs as specified below. Print the waveform output from the simulator, and annotate it with a pen or pencil to indicate the output features in the list below.Submitthesourcefileandannotatedoutputtimingdiagramforcredit.Deassert both inputs at the start of the simulation. At 100ns, asset S. At 200ns, deassert S. At 300ns, assert R. At 400ns, deassert R. At 500ns, assert both inputs. At 600ns, deassertbothinputs.At700ns,assertbothinputs.1.Anundefinedoutput2.Asetoperation3.Aresetoperation4.A0beingstoredinmemory5.A1beingstoredinmemory6.AstatewheretheQandQNoutputsarebothdriventothesamevalue7.Ametastablestate

CdigodelacompuertaNANDlibraryIEEEuseIEEE.STD_LOGIC_1164.ALLentityCOMPONENT_NANDis

port(CS:instd_logicCR:instd_logicCQ:INoutstd_logic)

endCOMPONENT_NANDarchitectureBehavioralofCOMPONENT_NANDissignalnotCQ:STD_LOGICbegin

notCQ R, CQ => Q)ENDBEHAVIORALCdigodelTestBenchLIBRARYieee

USEieee.std_logic_1164.ALLUncommentthefollowinglibrarydeclarationifusingarithmeticfunctionswithSignedorUnsignedvaluesUSEieee.numeric_std.ALLENTITYtestISENDtestARCHITECTUREbehaviorOFtestISComponentDeclarationfortheUnitUnderTest(UUT)COMPONENTSRPORT(S:INstd_logicR:INstd_logicQ:INOUTstd_logic)ENDCOMPONENT InputssignalS:std_logic:='0'signalR:std_logic:='0'

BiDirssignalQ:std_logicNoclocksdetectedinportlist.ReplacebelowwithappropriateportnameBEGIN

InstantiatetheUnitUnderTest(UUT)uut:SRPORTMAP(S=>S,R=>R,Q=>Q)Stimulusprocess

stim_proc:processbegin

S

CdigodelcomponentNORlibraryIEEEuseIEEE.STD_LOGIC_1164.ALLentityCOMPONENT_NORisport(

CS:instd_logicCR:instd_logicCQ:INoutstd_logic)

endCOMPONENT_NORarchitectureBehavioralofCOMPONENT_NORis

signalnotCQ:STD_LOGICbeginCQR,CQ=>Q)ENDBEHAVIORALCdigodeltestbenchLIBRARYieeeUSEieee.std_logic_1164.ALLUncommentthefollowinglibrarydeclarationifusingarithmeticfunctionswithSignedorUnsignedvaluesUSEieee.numeric_std.ALLENTITYtestISENDtest

ARCHITECTUREbehaviorOFtestISComponentDeclarationfortheUnitUnderTest(UUT)COMPONENTSRPORT(S:INstd_logicR:INstd_logicQ:INOUTstd_logic)ENDCOMPONENTInputssignalS:std_logic:='0'signalR:std_logic:='0'

BiDirssignalQ:std_logicNoclocksdetectedinportlist.ReplacebelowwithappropriateportnameBEGIN

InstantiatetheUnitUnderTest(UUT)uut:SRPORTMAP(S=>S,R=>R,Q=>Q)Stimulusprocess

stim_proc:processbegin

S

Simulacin

1.Anundefinedoutput2.Asetoperation3.Aresetoperation4.A0beingstoredinmemory5.A1beingstoredinmemory6. A state where the Q and QN outputs are both driven to the same value 7.Ametastablestate

S R NANDOUTPUT NOROUTPUT

1=>0 1=>1 1 0

1=>1 1=>0 0 1

1=>1 1=>1 q Nodeterminado

1=>0 1=>0 Nodeterminado q

0=>1 0=>1 q Nodeterminado

0=>0 0=>0 Nodeterminado q

0=>0 0=>1 1 0

0=>1 0=>0 0 1Problem 3. Modify the test bench for the NAND basic cell by deasserting S at 600ns and R at 601ns, and resimulate. Comment on any differences in the output, and more importantly,giveareasonforanydifferencesseen.

En este caso resolvemos el problema que nos da, el primer ejercicio al tener Q y Not Q con el mismo valor este caso se resuelve haciendo un set un ns antes de hacer un hold, manteniendoel1delsetanterior.TestBenchLIBRARYieeeUSEieee.std_logic_1164.ALLUncommentthefollowinglibrarydeclarationifusingarithmeticfunctionswithSignedorUnsignedvaluesUSEieee.numeric_std.ALLENTITYtestISENDtestARCHITECTUREbehaviorOFtestISComponentDeclarationfortheUnitUnderTest(UUT)COMPONENTSRPORT(S:INstd_logicR:INstd_logicQ:INOUTstd_logic)ENDCOMPONENT InputssignalS:std_logic:='0'signalR:std_logic:='0'

BiDirs

signalQ:std_logicNoclocksdetectedinportlist.ReplacebelowwithappropriateportnameBEGIN

InstantiatetheUnitUnderTest(UUT)uut:SRPORTMAP(S=>S,R=>R,Q=>Q)Stimulusprocess

stim_proc:processbegin

S

useUNISIM.VComponents.allentitymainisPort(clk:inSTD_LOGICresetS:inSTD_LOGIC

resetA:inSTD_LOGICD:inSTD_LOGIC_VECTOR(7downto0)Q:outSTD_LOGIC_VECTOR(7downto0))endmainarchitectureBehavioralofmainisbeginprocess(clk)Seactiaelffenambosflancosbegin

ifresetA='1'thenQ

PORT(clk:INstd_logicresetS:INstd_logicresetA:INstd_logicD:INstd_logic_vector(7downto0)Q:OUTstd_logic_vector(7downto0))ENDCOMPONENT Inputssignalclk:std_logic:='0'signalresetS:std_logic:='0'signalresetA:std_logic:='0'signalD:std_logic_vector(7downto0):=(others=>'0') OutputssignalQ:std_logic_vector(7downto0)Clockperioddefinitionsconstantclk_period:time:=10nsBEGIN

InstantiatetheUnitUnderTest(UUT)uut:mainPORTMAP(clk=>clk,resetS=>resetS,resetA=>resetA,D=>D,Q=>Q)Clockprocessdefinitionsclk_process:processbegin

clk

Problem 5. Create and simulate a source file for a T flipflop. Show all pertinent operating states in the simulation, and have the lab assistant inspect your work. Submit your source andsimulationfilesforcredit.Este es el circuito equivalente de un flip flop tipo T, se puede observar que el siguienteestadocambiaduranteunflancopositivoderelojyTes1

CdigoVHDLlibraryIEEEuseIEEE.STD_LOGIC_1164.ALLentityFF_Tis

Port(T:inSTD_LOGIC Clock:inSTD_LOGIC Q:inoutSTD_LOGIC:='0')endFF_TarchitectureBehavioralofFF_Tisbegin

process(Clock,T) begin ifClock'eventandClock='1'andT='1'then QT, Clock=>Clock, Q=>Q )

Problem 6. Create and simulate a source file for a JK flipflop. Show all pertinent operatingstatesinthesimulation,andsubmityoursourceandsimulationfilesforcredit.ElsiguienteeselcircuitoequivalenteaunflipfloptipoJKylatabladeverdadesequivalentealaecuacinQ(next)=JQ'+K'Q

CdigoVHDLlibraryIEEEuseIEEE.STD_LOGIC_1164.ALLentityFF_JKis

Port(J:inSTD_LOGIC K:inSTD_LOGIC Clock:inSTD_LOGIC Q:inoutSTD_LOGIC:='0')endFF_JKarchitectureBehavioralofFF_JKisbegin process(Clock,J,K)

begin ifClock'eventandClock='1'then QJ,