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A Wallace tree is an efficient hardwire implementationof a digital circuit that multiplies two integers.

The Wallace tree has three steps:

Multiply (that is - AND) each bit of one of the arguments,

by each bit of the other, yielding n2 results. Depending

on position of the multiplied bits, the wires carry different

weights, for example wire of bit carrying result ofa2b3 is

32.

Reduce the number of partial products to two by layersof full and half adders.

Group the wires in two numbers, and add them with a

conventional adder.


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Take any three wires with the same weights and input

them into a full adder. The result will be an output wire of

the same weight and an output wire with a higher weight

for each three input wires.

If there are two wires of the same weight left, input them

into a half adder.

If there is just one wire left, connect it to the next layer.


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Suppose two numbers are being multiplied:

a3a2a1a0 X b3b2b1b0

___________________________________

a3b0 a2b0 a1b0 a0b0a3b1 a2b1 a1b1 a0b1

a3b2 a2b2 a1b2 a0b2

a3b3 a2b3 a1b3 a0b3

_____________________________________


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a3b3 a2b3 a1b3 a0b3 a0b2 a0b1 a0b0

a3b2 a2b2 a1b2 a1b1 a1b0

a3b1 a2b1 a2b0a3b0


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1111 x 1101

1 1 1 1 1 1 1 1 1 0

1

0 0 0 0 1 1 1 0 1

1 1 1 1 0 0 11 1 1 1 1

1 1 1 1 1 0 1 1 0 0 1 1

0 1 1 1 1 1 0 1 1 1 1 0

1 1

0 0 1 1

HA

FA

First stage

Second stage Final Adder

Partial

Products

1 1 0 0 0 0 1 1

Example for 4bit Multiplication using

Wallace tree:


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a3b3 a2b3a3b2

a3b1a2b2

a1b3

a2b1

a3b0

a0b3

a1b2

a1b1

a2b0

a0b2

a1b0

a0b1 a0b0Partial products

HA


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FULL ADDER HALF ADDER


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Each layer of the tree reduces the number of vectors by

a factor of 3:2

Minimum propagation delay.

The benefit of the Wallace tree is that there are only

O(log n) reduction layers, but adding partial products

with regular adders would require O(logn)2

time.


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Wallace trees do not provide any advantage over ripple

adder trees in many FPGAs.

Due to the irregular routing, they may actually be slowerand are certainly more difficult to route.

Adder structure increases for increased bit multiplication.


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Wallace Tree multiplier can also be implemented

using Carry Save Adders.

Sometimes Wallace Tree Multiplier is Combined

with Booth Encoding. Various other researches have been done to

reduce the number of adders, for higher order

bits such as 16 & 32.

Applications, as the use in DSP for performing

FFT,FIR, etc.,

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