Ppt 1

process variation aware FINFET basedsram cell

Ashvinikumar Dongresumit patel

16 April,2012

Contents

Contents:

1. Introduction

2. Need for Novel devices

3. FinFET models

4. Classification of process variation

I What is NBTI/PBTI

5. Variations on stability of 6T FinFET SRAM cellswith various surface orientations due toNBTI/PBTI

6. Work progress

7. Reference

Introduction

Introduction

I As dimensions of MOS devices have been scaled down, newreliability problems are coming into effect.

I One of these emerging reliability issues is aging effects whichresult in device performance degradation over time.

I NBTI (Negative Bias Temperature Instability) and PBTI(Positive Bias Temperature Instability) are well known agingeffects which cause the threshold voltage degradation ofPMOS and NMOS transistors over time.

I Thus NBTI (for PFET) and PBTI (for NFET)) have becomemajor long-term reliability concerns as they weaken MOSFETsover time, thus resulting in temporal degradation in thestability of the SRAM cells.

Why there is a need to switch over from cmos to novel devices.

Why there is a need to switch over fromcmos to novel devices.

I Bulk CMOS vs SOI CMOS1. In a bulk CMOS device, each transistor is isolated by

reverse−biased p−n junctions in a well structure. On the otherhand, in a SOI CMOS device, each transistor is completelyisolated by the Oxide insulator. Thus, parasitic effects in a SOIdevice are very small.

FDSOI

FDSOI

I There are two kinds of SOI devices; Partially Depleted(PD)-SOI and Fully Depleted (FD)SOI. The PD-SOI has arelatively thick SOI Si thickness (100-200 nm),while in the FDSOI the SOI thickness is less than 50 nm in the FD-SOI theSOI thickness is less than 50 nm.

I In PD-SOI, there remains a neutral region in the body.

I In FD-SOI, the whole body under the gate will deplete.

Scaling challenges

Scaling challenges

I At the device gate length (L) less than 100nm, further,reduction in L has yielded limited improvements inperformance due to velocity saturation and source velocitylimit.

I As the physical thickness of the SiO2 gate dielectric (Tox ) isscaled beyond 1.2nm, quantum mechanical tunneling currentfrom the gate into the channel becomes signicant.

I Further reduction in Tox will result in large static leakagecurrent and large power consumption even when the device isturned off.

Scaling challenges contd...

I A new approach is needed to allow future reduction of channellength. The multi−gate structure is a promising approach.

Multigate advantages

Multigate advantages

I The main advantage of the multigate devices is the improvedshort channel effects . Since the channel is controlledelectrostatically by the gate from multiple sides, the channel isbetter controlled by the gate than in the conventionaltransistor structure.

I Unwanted leakage components are reduced.

I Improved gate control also provides lower output conductance.

I The second advantage is improved on state drive current(Ion)and therefore faster circuit speed.

Multigate advantages(contd...)

Multigate advantages(contd...)

I The FinFET, provides a larger channel width with a smallfootprint in area. This raises Ion , which is handy for driving alarge capacitive load such as long interconnect.

I The third advantage is the reduced manufacturing variation.In the absence of channel dopants, the effect of randomdopant uctuation (RDF) is minimized.

FinFET Variants

FinFET Variants

FinFET models

FinFET models

I Multi gate MOSFETs are divided in two main categories:

1. independent multi−gate (IMG)2. common multi− gate (CMG) MOSFETs.

I BSIM IMG

1. IMG refers to independent double−gate MOSFETs with twoseparate gates.

2. The front and back gate stacks are allowed to have deferentgate workfunctions, biases, dielectric thicknesses and materials.

3. Independent−gate FinFET and the planar double−gate SOIbelong to this category.

FinFET models(contd...)

FinFET models(contd...)

I BSIM−CMG

1. CMG refers to a special case where the gates are connectedtogether.

2. The gate stacks of CMG MOSFETs have identical gateworkfunction, bias and dielectric thickness and material.

3. Regular FinFETs and all around gate MOSFETs fall into tothis category.

Small signal model for FinFET(contd...)

Small signal model for FinFET(contd...)

Small signal model for FinFET

Small signal model for FinFET

Small signal model for FinFET(contd...)

Small signal model for FinFET(contd...)

Classification on process variation

Classification on process variation

NBTI Mechanism and modelling

NBTI Mechanism and modelling

I NBTI is caused by broken Si-H bonds, which are induced bypositive holes from the channel. Then H, in a neutral form,diffuses away; positive interface traps (N it ) (i.e., from Si + )are left, which cause the increase of V th.

I the change in vth due to NBTI can be modelled as

....(1)and Nit is positive interface trap which can be expressed as

....(2)

NBTI Modelling contd...

NBTI Modelling contd...

I K is the generation rate of Nit and found to be linearlyproportional to the hole density and exponentially dependenton temperature (T) and the electric field (Eox)Therefore, forV ds =0:

....(3)

I The dependence of K on Vds can be derived from Eq. (3) as:

....(4)

NBTI Modelling contd...

NBTI modelling contd...I In Phase II, when Vg=VDD (i.e., V gs =0), holes are not

present in the channel and thus,no new interface traps aregenerated; instead, H diffuses back and anneals the brokenSi-H. As a result, the number of interface traps is reducedduring this stage and the NBTI degradation is recovered.

I Assuming the recovery happens at t=t 0 with Nit=Nit0 , thechange of Nit can then be modeled as ....(5)

I following figure explains the behaviour of NBTI in more detail

Effects of NBTI/PBTI on SRAM

Effects of NBTI/PBTI on SRAMI As we can see the PU(pull up)transistors are effected by NBTI

and PD(pull down)PG(pass gate)transistors are affected byPBTI.

I These are the effect of NBTI/PBTI on Vth at 32nm node.

Effects of NBTI/PBTI on SRAM

Effects of NBTI/PBTI on SRAM

I Surprising we see that SNM increases in presence ofNBTI/PBTI.

I But at the same time decrease in Iread may cause read failure.

Techniques to mitigate effects of NBTI/PBTI

Techniques to mitigate effects of NBTI/PBTI

I From above discussion we can conclude that NBTI/PBTIdepends onProcess parameters : Vth,ToxDesign parameters : VDD,Vds,Duty cycle

I Keeping these points in mind the techniques available tomitigate the effect of NBTI can be stated as

1. An optimal VDD exists to minimise the degradation2. PMOS sizing3. Reducing the duty cycle

WHY FinFET in SRAM..???

WHY FinFet in SRAM..???

I FinFet based SRAM is found to be more immune to mismatchinduced by process variation.

I A FinFet uses an intrinsic body,it greatly suppresses thedevice-performance variability caused by fluctuations innumber of dopant ions.

I FinFet is suitable for future nano scale memory circuits designdue to its reduced short channel effects.

I FinFet cell offers superior noise margins and switching speedsas well.

I An added advantage of the FinFet is that it can be easilyfabricated along different channel planes in a singledie,whereas Fabrication of conventional planar MOSFETsalong any plane other than (100) is difficult due to increasedprocess variations and interface traps

Oriented FinFETs

Oriented FinFets

I With the advent of FinFETs, fabrication of transistors alongthe (110) plane has become feasible, leading to design ofcircuits using differently oriented transistors.

I Electron mobility is highest in the (100) plane and the holemobility along the (110) plane. Thus, logic gates consisting ofp-type FinFETs implemented in the (110) plane and n-typeFinFETs in the (100) plane will be the fastest.

Effect of NBTI/PBTI on FinFET with different orientation

Effect of NBTI/PBTI on FinFET withdifferent orientation

I The variability of RSNM due to NBTI/PBTI can be shown as

I The variability of WSNM due to NBTI/PBTI can be shown as

Effect of NBTI/PBTI on FinFET with different orientation

Effect of NBTI/PBTI on FinFET withdifferent orientation

I The entire analysis can be summarised as

Work progress

Work progress

I Tools used

1. SILVACO-ICCAD(GATEWAY,SMARTSPICE)2. SILVACO-TCAD(ATHENA, ATLAS,DevEdit3D)

I We found two ways to implement Finfet based SRAM

1. Take the model files and work on circuit level.2. Start work from device level and then use that device at circuit

level.

I We started from device level

I We went through the device and process simulation steps andtried to modified the example of FinFET according to ourrequirement.

I Still working on how to use BSIM-CMG 106.0.0(latest modelreleased on 15th march 2012) for Finfet simulation

Reference

Reference

I Vita Pi-Ho Hu, Ming-Long Fan, Chien-Yu Hsieh, Pin Su andChing-Te Chuang,”FinFET SRAM Cell OptimizationConsidering Temporal Variability due to NBTI/PBTI andSurface Orientation” , SISPAD 2010

I Rakesh Vattikonda,Wenping Wang,Yu Cao,”Modeling andMinimization of PMOS NBTI Effect for Robust NanometerDesign”,DAC 2006, San Francisco, California, USA.

I Harwinder Singh,San Francisco State University,California,Thesis on ”ANALYSIS OF SRAM RELIABILITYUNDER COMBINED EFFECT OF TRANSISTORAGING,PROCESS AND TEMPERATURE VARIATIONS INNANO-SCALE CMOS”.