PowerPC Operating Environment Architecture Book III Version 2mueller/cluster/ps3/SDK... · II, PowerPC Virtual Environment Architecture defines the storage model and related instructions

Version 2.02

PowerPC Operating Environment Architecture

Book III

Version 2.02

January 28, 2005

Manager:

Joe Wetzel/Poughkeepsie/IBM

Technical Content:

Ed Silha/Austin/IBM Cathy May/Watson/IBM Brad Frey/Austin/IBM

Junichi Furukawa/Austin/IBM Giles Frazier/Austin/IBM

i

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ii PowerPC Operating Environment Architecture

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Preface

This document defines the additional instructions andfacilities, beyond those of the PowerPC User Instruc-tion Set Architecture and PowerPC Virtual EnvironmentArchitecture, that are provided by the PowerPC Operat-ing Environment Architecture. It covers instructionsand facilities not available to the application program-mer, affecting storage control, interrupts, and timingfacilities.

Other related documents define the PowerPCUserInstruction Set Architecture, the PowerPC Virtual Envi-ronment Architecture, and PowerPC ImplementationFeatures. Book I, PowerPC User Instruction Set Archi-tecture defines the base instruction set and relatedfacilities available to the application programmer. BookII, PowerPC Virtual Environment Architecture definesthe storage model and related instructions and facilitiesavailable to the application programmer, and the TimeBase as seen by the application programmer. Book IV,PowerPC Implementation Features defines the imple-mentation-dependent aspects of a particular implemen-tation.

As used in this document, the term “PowerPC Architec-ture” refers to the instructions and facilities described inBooks I, II, and III. The description of the instantiation ofthe PowerPC Architecture in a given implementationincludes also the material in Book IV for that implemen-tation.

Note: Change bars indicate changes relative to Version2.01.

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iv PowerPC Operating Environment Architecture

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Table of Contents

Chapter 1. Introduction . . . . . . . . . . 11.1 Overview. . . . . . . . . . . . . . . . . . . . . . 11.2 Compatibility with the POWER Archi-

tecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Document Conventions . . . . . . . . . . 11.3.1 Definitions and Notation. . . . . . . . . 11.3.2 Reserved Fields. . . . . . . . . . . . . . . 21.4 General Systems Overview . . . . . . . 31.5 Exceptions . . . . . . . . . . . . . . . . . . . . 31.6 Synchronization . . . . . . . . . . . . . . . . 41.6.1 Context Synchronization . . . . . . . . 41.6.2 Execution Synchronization . . . . . . 41.7 Logical Partitioning (LPAR). . . . . . . . 51.7.1 Logical Partitioning Control Register

(LPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 51.7.2 Real Mode Offset Register (RMOR)61.7.3 Hypervisor Real Mode Offset Regis-

ter (HRMOR). . . . . . . . . . . . . . . . . . . . . . 61.7.4 Logical Partition

Identification Register (LPIDR) . . . . . . . . 71.7.5 Other Hypervisor Resources . . . . . 71.7.6 Sharing Hypervisor Resources . . . 8

Chapter 2. Branch Processor . . . . . 92.1 Branch Processor Overview . . . . . . . 92.2 Branch Processor Registers . . . . . . . 92.2.1 Machine Status Save/Restore Regis-

ters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.2.2 Hypervisor Machine Status Save/

Restore Registers . . . . . . . . . . . . . . . . . . 92.2.3 Machine State Register . . . . . . . . 102.3 Branch Processor Instructions . . . . 122.3.1 System Linkage Instructions . . . . 12

Chapter 3. Fixed-Point Processor 153.1 Fixed-Point Processor Overview . . 153.2 Special Purpose Registers . . . . . . . 153.3 Fixed-Point Processor Registers . . 153.3.1 Data Address Register. . . . . . . . . 153.3.2 Data Storage Interrupt

Status Register . . . . . . . . . . . . . . . . . . . 163.3.3 Software-use SPRs . . . . . . . . . . . 163.3.4 Control Register. . . . . . . . . . . . . . 173.3.5 Processor Version Register . . . . . 173.3.6 Processor Identification Register . 17

3.4 Fixed-Point Processor Instructions . 183.4.1 OR Instruction . . . . . . . . . . . . . . . 183.4.2 Move To/From System Register

Instructions . . . . . . . . . . . . . . . . . . . . . . 18

Chapter 4. Storage Control . . . . . . 254.1 Storage Addressing. . . . . . . . . . . . . 254.2 Storage Model . . . . . . . . . . . . . . . . 264.2.1 Storage Exceptions . . . . . . . . . . . 264.2.2 Instruction Fetch . . . . . . . . . . . . . 274.2.3 Data Access . . . . . . . . . . . . . . . . . 274.2.4 Performing Operations

Out-of-Order . . . . . . . . . . . . . . . . . . . . . 274.2.5 32-Bit Mode . . . . . . . . . . . . . . . . . 294.2.6 Real Addressing Mode. . . . . . . . . 294.2.7 Address Ranges Having Defined

Uses . . . . . . . . . . . . . . . . . . . . . . . . . . . 314.2.8 Invalid Real Address . . . . . . . . . . 314.3 Address Translation Overview . . . . 324.4 Virtual Address Generation . . . . . . . 334.4.1 Segment Lookaside Buffer (SLB). 334.4.2 SLB Search . . . . . . . . . . . . . . . . . 344.5 Virtual to Real Translation . . . . . . . . 354.5.1 Page Table . . . . . . . . . . . . . . . . . . 364.5.2 Storage Description

Register 1 . . . . . . . . . . . . . . . . . . . . . . . 374.5.3 Page Table Search. . . . . . . . . . . . 384.6 Data Address Compare. . . . . . . . . . 394.7 Data Address Breakpoint . . . . . . . . 404.8 Storage Control Bits . . . . . . . . . . . . 414.8.1 Storage Control Bit Restrictions . . 424.8.2 Altering the Storage Control Bits . 424.9 Reference and Change Recording . 434.10 Storage Protection. . . . . . . . . . . . . 454.10.1 Storage Protection, Address Trans-

lation Enabled . . . . . . . . . . . . . . . . . . . . 454.10.2 Storage Protection, Address Trans-

lation Disabled . . . . . . . . . . . . . . . . . . . . 464.11 Storage Control Instructions . . . . . 474.11.1 Cache Management Instructions 474.11.2 Synchronize Instruction . . . . . . . 474.11.3 Lookaside Buffer

Management . . . . . . . . . . . . . . . . . . . . . 474.12 Page Table Update

Synchronization Requirements . . . . . . . 574.12.1 Page Table Updates. . . . . . . . . . 57

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Chapter 5. Interrupts . . . . . . . . . . . 615.1 Overview . . . . . . . . . . . . . . . . . . . . .615.2 Interrupt Synchronization . . . . . . . . .615.3 Interrupt Classes . . . . . . . . . . . . . . .625.3.1 Precise Interrupt . . . . . . . . . . . . . .625.3.2 Imprecise Interrupt . . . . . . . . . . . .625.4 Interrupt Processing . . . . . . . . . . . . .625.4.1 Hypervisor Interrupts. . . . . . . . . . .635.5 Interrupt Definitions . . . . . . . . . . . . .655.5.1 System Reset Interrupt . . . . . . . . .665.5.2 Machine Check Interrupt . . . . . . . .665.5.3 Data Storage Interrupt. . . . . . . . . .665.5.4 Data Segment Interrupt. . . . . . . . .685.5.5 Instruction Storage Interrupt . . . . .685.5.6 Instruction Segment

Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .695.5.7 External Interrupt. . . . . . . . . . . . . .695.5.8 Alignment Interrupt . . . . . . . . . . . .695.5.9 Program Interrupt . . . . . . . . . . . . .705.5.10 Floating-Point Unavailable

Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .725.5.11 Decrementer Interrupt . . . . . . . . .725.5.12 Hypervisor Decrementer

Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .725.5.13 System Call Interrupt. . . . . . . . . .735.5.14 Trace Interrupt. . . . . . . . . . . . . . .735.5.15 Performance Monitor

Interrupt (Optional) . . . . . . . . . . . . . . . . .735.6 Partially Executed

Instructions . . . . . . . . . . . . . . . . . . . . . . .735.7 Exception Ordering . . . . . . . . . . . . .745.7.1 Unordered Exceptions. . . . . . . . . .745.7.2 Ordered Exceptions . . . . . . . . . . .745.8 Interrupt Priorities. . . . . . . . . . . . . . .76

Chapter 6. Timer Facilities. . . . . . . 796.1 Overview . . . . . . . . . . . . . . . . . . . . .796.2 Time Base . . . . . . . . . . . . . . . . . . . .796.2.1 Writing the Time Base. . . . . . . . . .806.3 Decrementer . . . . . . . . . . . . . . . . . .806.3.1 Writing and Reading the Decre-

menter . . . . . . . . . . . . . . . . . . . . . . . . . .816.4 Hypervisor Decrementer . . . . . . . . .816.5 Processor Utilization of Resources

Register (PURR). . . . . . . . . . . . . . . . . . .82

Chapter 7. Synchronization Requirements for Context Alterations85

Chapter 8. Optional Facilities and Instructions . . . . . . . . . . . . . . . . . . . 89

8.1 External Control . . . . . . . . . . . . . . . .898.1.1 External Access Register . . . . . . .89

8.1.2 External Access Instructions . . . . 908.2 Real Mode Storage Control . . . . . . 908.3 Move to Machine State Register

Instruction . . . . . . . . . . . . . . . . . . . . . . . 918.4 Fixed-Point Storage Access Instruc-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Chapter 9. Optional Facilities and Instructions that are being Phased Out . . . . . . . . . . . . . . . . . . . . . . . . . . 93

9.1 Bridge to SLB Architecture . . . . . . . 939.1.1 Segment Register

Manipulation Instructions . . . . . . . . . . . 93

Appendix A. Assembler Extended Mnemonics . . . . . . . . . . . . . . . . . . . 97

A.1 Move To/From Special Purpose Regis-ter Mnemonics . . . . . . . . . . . . . . . . . . . 98

Appendix B. Cross-Reference for Changed POWER Mnemonics. . . 101

Appendix C. New and Newly Optional Instructions . . . . . . . . . . 103

Appendix D. Interpretation of the DSISR as Set by an Alignment Interrupt. . . . . . . . . . . . . . . . . . . . . 105

Appendix E. Example Performance Monitor (Optional) . . . . . . . . . . . . 107

E.1 PMM Bit of the Machine State Register108

E.2 Special Purpose Registers . . . . . . 109E.2.1 Performance Monitor Counter Regis-

ters . . . . . . . . . . . . . . . . . . . . . . . . . . . 109E.2.2 Monitor Mode Control Register 1 112E.2.3 Monitor Mode Control Register A113E.2.4 Sampled Instruction Address Regis-

ter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113E.2.5 Sampled Data Address Register 114E.3 Performance Monitor

Interrupt. . . . . . . . . . . . . . . . . . . . . . . . 114E.4 Interaction with the Trace Facility. 114

Appendix F. Example Trace Extensions (Optional) . . . . . . . . . .117

Appendix G. PowerPC Operating Environment Instruction Set . . . . .119

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Figures

1. Logical view of the PowerPC processor architecture . . . . . . . . . . . . . . . . . . 3

2. Logical Partitioning Control Register . . . . . . . . . . 53. Real Mode Offset Register . . . . . . . . . . . . . . . . . 64. Hypervisor Real Mode Offset Register . . . . . . . . 65. Logical Partition Identification Register . . . . . . . . 76. Save/Restore Registers . . . . . . . . . . . . . . . . . . . 97. Hypervisor Save/Restore Registers . . . . . . . . . . 98. Machine State Register . . . . . . . . . . . . . . . . . . . 109. Data Address Register . . . . . . . . . . . . . . . . . . . 1510. Data Storage Interrupt Status Register . . . . . . 1611. SPRs for use by privileged non-hypervisor pro-

grams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1612. SPRs for use by hypervisor programs. . . . . . . 1613. Control Register . . . . . . . . . . . . . . . . . . . . . . . 1714. Processor Version Register. . . . . . . . . . . . . . . 1715. Processor Identification Register. . . . . . . . . . . 1716. Priority hint levels for or Rx,Rx,Rx. . . . . . . . . . 1817. SPR encodings for mtspr . . . . . . . . . . . . . . . . 1918. SPR encodings for mfspr . . . . . . . . . . . . . . . . 2119. Address translation overview . . . . . . . . . . . . . 3220. Translation of 64-bit effective address to

80-bit virtual address . . . . . . . . . . . . . . . . . . 3321. SLB Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3322. Translation of 80-bit virtual address to 62-bit real

address . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3523. Page Table Entry. . . . . . . . . . . . . . . . . . . . . . . 3624. SDR1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3725. Address Compare Control Register . . . . . . . . 3926. Data Address Breakpoint Register . . . . . . . . . 4027. Data Address Breakpoint Register Extension . 4028. Storage control bits . . . . . . . . . . . . . . . . . . . . . 4129. Setting the Reference and Change bits . . . . . 4430. PP bit protection states, address

translation enabled. . . . . . . . . . . . . . . . . . . . 4531. Protection states, address translation

disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4632. GPR contents for slbmte . . . . . . . . . . . . . . . . . 5133. GPR contents for slbmfev . . . . . . . . . . . . . . . . 5234. GPR contents for slbmfee . . . . . . . . . . . . . . . . 5235. MSR setting due to interrupt . . . . . . . . . . . . . . 6536. Effective address of interrupt vector by

interrupt type . . . . . . . . . . . . . . . . . . . . . . . . 6537. Time Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7938. Decrementer . . . . . . . . . . . . . . . . . . . . . . . . . . 8039. Hypervisor Decrementer . . . . . . . . . . . . . . . . . 8140. Processor Utilization of Resources Register . . 8241. External Access Register . . . . . . . . . . . . . . . . 89

42. GPR contents for mtsr, mtsrin, mfsr, and mfsrin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

43. Performance Monitor SPR encodings formtspr and mfspr . . . . . . . . . . . . . . . . . . . . . 109

44. Performance Monitor Counter registers . . . . . 10945. Monitor Mode Control Register 0 . . . . . . . . . . 11046. Monitor Mode Control Register 1 . . . . . . . . . . 11247. Monitor Mode Control Register A. . . . . . . . . . 11348. Sampled Instruction Address Register. . . . . . 11349. Sampled Data Address Register . . . . . . . . . . 114

Figures vii

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viii PowerPC Operating Environment Architecture

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Chapter 1. Introduction

1.1 Overview. . . . . . . . . . . . . . . . . . . . . . 11.2 Compatibility with the POWER Archi-

tecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Document Conventions . . . . . . . . . . 11.3.1 Definitions and Notation. . . . . . . . . 11.3.2 Reserved Fields. . . . . . . . . . . . . . . 21.4 General Systems Overview . . . . . . . 31.5 Exceptions . . . . . . . . . . . . . . . . . . . . 31.6 Synchronization . . . . . . . . . . . . . . . . 41.6.1 Context Synchronization . . . . . . . . 41.6.2 Execution Synchronization . . . . . . 4

1.7 Logical Partitioning (LPAR) . . . . . . . . 51.7.1 Logical Partitioning Control Register

(LPCR). . . . . . . . . . . . . . . . . . . . . . . . . . . 51.7.2 Real Mode Offset Register (RMOR)61.7.3 Hypervisor Real Mode Offset Regis-

ter (HRMOR) . . . . . . . . . . . . . . . . . . . . . . 61.7.4 Logical Partition

Identification Register (LPIDR) . . . . . . . . 71.7.5 Other Hypervisor Resources . . . . . 71.7.6 Sharing Hypervisor Resources . . . 8

1.1 OverviewChapter 1 of Book I, PowerPC User Instruction SetArchitecture describes computation modes, compatibil-ity with the POWER Architecture, document conven-tions, a general systems overview, instruction formats,and storage addressing. This chapter augments thatdescription as necessary for the PowerPC OperatingEnvironment Architecture.

1.2 Compatibility with the POWER ArchitectureThe PowerPC Architecture provides binary compatibil-ity for POWER application programs, except asdescribed in the appendix entitled “Incompatibilitieswith the POWER Architecture” in Book I, PowerPCUser Instruction Set Architecture. Binary compatibilityis not necessarily provided for privileged POWERinstructions.

1.3 Document ConventionsThe notation and terminology used in Book I apply tothis Book also, with the following substitutions.

� For “system alignment error handler” substitute“Alignment interrupt”.

� For “system data storage error handler” substitute“Data Storage interrupt”, “Data Segment interrupt”,

or “Data Storage or Data Segment interrupt”, asappropriate.

� For “system error handler” substitute “interrupt”.

� For “system floating-point enabled exception errorhandler” substitute “Floating-Point Enabled Excep-tion type Program interrupt”.

� For “system illegal instruction error handler” substi-tute “Illegal Instruction type Program Interrupt”.

� For “system instruction storage error handler” sub-stitute “Instruction Storage interrupt”, “InstructionSegment interrupt”, or “Instruction Storage orInstruction Segment interrupt”, as appropriate.

� For “system privileged instruction error handler”substitute “Privileged Instruction type Programinterrupt”.

� For “system service program” substitute “SystemCall interrupt”, as appropriate.

� For “system trap handler” substitute “Trap typeProgram interrupt”.

1.3.1 Definitions and Notation

The definitions and notation given in Book I, PowerPCUser Instruction Set Architecture are augmented by thefollowing.

� A real page is a 4 KB unit of real storage that isaligned at a 4 KB boundary.

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� The context of a program is the environment (e.g.,privilege and relocation) in which the program exe-cutes. That context is controlled by the contents ofcertain System Registers, such as the MSR andSDR1, of certain lookaside buffers, such as theSLB and TLB, and of the Page Table.

� An exception is an error, unusual condition, orexternal signal, that may set a status bit and mayor may not cause an interrupt, depending uponwhether the corresponding interrupt is enabled.

� An interrupt is the act of changing the machinestate in response to an exception, as described inChapter 5. “Interrupts” on page 61.

� A trap interrupt is an interrupt that results from exe-cution of a Trap instruction.

� Additional exceptions to the rule that the processorobeys the sequential execution model, beyondthose described in the section entitled “InstructionFetching” in Book I, are the following.

- A System Reset or Machine Check interruptmay occur. The determination of whether aninstruction is required by the sequential exe-cution model is not affected by the potentialoccurrence of a System Reset or MachineCheck interrupt. (The determination isaffected by the potential occurrence of anyother kind of interrupt.)

- A context-altering instruction is executed(Chapter 7. “Synchronization Requirementsfor Context Alterations” on page 85). Thecontext alteration need not take effect until therequired subsequent synchronizing operationhas occurred.

- A Reference and Change bit is updated by theprocessor. The update need not be per-formed with respect to that processor until therequired subsequent synchronizing operationhas occurred.

� Hardware means any combination of hard-wiredimplementation, emulation assist, or interrupt forsoftware assistance. In the last case, the interruptmay be to an architected location or to an imple-mentation-dependent location. Any use of emula-tion assists or interrupts to implement thearchitecture is described in Book IV, PowerPCImplementation Features.

� /, //, ///, ... denotes a field that is reserved in aninstruction, in a register, or in an architected stor-age table.

1.3.2 Reserved Fields

Some fields of certain architected storage tables maybe written to automatically by the processor, e.g., Ref-erence and Change bits in the Page Table. When the

processor writes to such a table, the following rules areobeyed.

� Unless otherwise stated, no defined field otherthan the one(s) the processor is specifically updat-ing are modified.

� Contents of reserved fields are either preserved bythe processor or written as zero.

The handling of reserved bits in System Registersdescribed in Book I applies here as well. The readershould be aware that reading and writing of some ofthese registers (e.g., the MSR) can occur as a sideeffect of processing an interrupt and of returning froman interrupt, as well as when requested explicitly by theappropriate instruction (e.g., mtmsrd).

Software should set reserved fields in architectedstorage tables (e.g., the Page Table) to zero,because these fields may be assigned a meaningin some future version of the architecture.

Programming Note

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1.4 General Systems OverviewThe processor or processor unit contains the sequenc-ing and processing controls for instruction fetch,instruction execution, and interrupt action. Instructionsthat the processing unit can execute fall into threeclasses:

� instructions executed in the Branch Processor

� instructions executed in the Fixed-Point Processor

� instructions executed in the Floating-Point Proces-sor

Almost all instructions executed in the Branch Proces-sor, Fixed-Point Processor, and Floating-Point Proces-sor are nonprivileged and are described in Book I,PowerPC User Instruction Set Architecture. Book II,PowerPC Virtual Environment Architecture maydescribe additional nonprivileged instructions (e.g.,Book II describes some nonprivileged instructions forcache management). Instructions related to the privi-leged state of the processor, control of processorresources, control of the storage hierarchy, and allother privileged instructions are described here or inBook IV, PowerPC Implementation Features.

Figure 1. Logical view of the PowerPC processor architecture

1.5 ExceptionsThe following augments the list, given in Book I, ofexceptions that can be caused directly by the executionof an instruction:

� the execution of a floating-point instruction whenMSRFP=0 (Floating-Point Unavailable interrupt)

� an attempt to modify a hypervisor resource whenthe processor is in privileged but non-hypervisorstate (see Section 1.7), or an attempt to execute ahypervisor-only instruction (e.g., tlbie) when theprocessor is in privileged but non-hypervisor state.

� the execution of a traced instruction (Trace inter-rupt)

BRANCH

PROCESSOR

FIXED-POINT

PROCESSORDATACACHE

FLOATING-POINT

PROCESSOR

INSTRUCTIONCACHE

MAIN MEMORY

DIRECT MEMORY ACCESS


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1.6 Synchronization

The synchronization described in this section refers tothe state of the processor that is performing the syn-chronization.

1.6.1 Context Synchronization

An instruction or event is context synchronizing if it sat-isfies the requirements listed below. Such instructionsand events are collectively called context synchronizingoperations. Examples of context synchronizing opera-tions include the isync, sc, and rfid instructions, themtmsr[d] instruction if L=0, and most interrupts.

1. The operation causes instruction dispatching (theissuance of instructions by the instruction fetchmechanism to any instruction execution mecha-nism) to be halted.

2. The operation is not initiated or, in the case ofisync, does not complete, until all instructionsalready in execution have completed to a point atwhich they have reported all exceptions they willcause.

3. The operation ensures that the instructions thatprecede the operation will complete execution inthe context (privilege, relocation, storage protec-tion, etc.) in which they were initiated, except thatthe operation has no effect on the context in whichthe associated Reference and Change bit updatesare performed.

4. If the operation directly causes an interrupt (e.g.,sc directly causes a System Call interrupt) or is aninterrupt, the operation is not initiated until noexception exists having higher priority than theexception associated with the interrupt (seeSection 5.8, “Interrupt Priorities” on page 76).

5. The operation ensures that the instructions that fol-low the operation will be fetched and executed inthe context established by the operation. (Thisrequirement dictates that any prefetched instruc-tions be discarded and that any effects and sideeffects of executing them out-of-order also be dis-carded, except as described inSection 4.2.4, “Per-forming Operations Out-of-Order” on page 27.)

1.6.2 Execution Synchronization

An instruction is execution synchronizing if it satisfiesitems 2 and 3 of the definition of context synchroniza-tion (see Section 1.6.1). sync and ptesync are treatedlike isync with respect to item 2 (i.e., the conditionsdescribed in item 2 apply to the completion of sync andptesync). Examples of execution synchronizinginstructions are sync, ptesync, and mtmsrd.

A context synchronizing operation is necessarilyexecution synchronizing; see Section 1.6.2.

Unlike the Synchronize instruction, a context syn-chronizing operation does not affect the order inwhich storage accesses are performed.

Programming Note

All context synchronizing instructions are executionsynchronizing.

Unlike a context synchronizing operation, an exe-cution synchronizing instruction does not ensurethat the instructions following that instruction willexecute in the context established by that instruc-tion. This new context becomes effective some-time after the execution synchronizing instructioncompletes and before or at a subsequent contextsynchronizing operation.

Programming Note


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1.7 Logical Partitioning (LPAR)

The Logical Partitioning (LPAR) facility permits proces-sors and portions of real storage to be assigned to logi-cal collections called partitions, such that a programexecuting on a processor in one partition cannot inter-fere with any program executing on a processor in adifferent partition. This isolation can be provided forboth problem state and privileged state programs, byusing a layer of trusted software, called a hypervisorprogram (or simply a “hypervisor”), and the resourcesprovided by this facility to manage system resources.(A hypervisor is a program that runs in hypervisor state;see below.)

The number of partitions supported is implementation-dependent.

A processor is assigned to one partition at any giventime. A processor can be assigned to any given parti-tion without consideration of the physical configurationof the system (e.g., shared registers, caches, organiza-tion of the storage hierarchy), except that processorsthat share certain hypervisor resources may need to beassigned to the same partition; see Section 1.7.5. Theregisters and facilities used to control Logical Partition-ing are listed below and described in the following sub-sections.

Except in the following subsections, references to the"operating system" in Books I - III include the hypervi-sor unless otherwise stated or obvious from context.

1.7.1 Logical Partitioning Control Register (LPCR)

The layout of the Logical Partitioning Control Register(LPCR) is shown in Figure 2 below.

Figure 2. Logical Partitioning Control Register

The contents of the LPCR control a number of aspectsof the operation of the processor with respect to a logi-cal partition. Below are shown the bit definitions for theLPCR.

Bit Description

0:34 Reserved

35:37 Real Mode Offset Selector (RMLS)

The RMLS field specifies the largest effectiveaddress that can be used by partition softwarewhen address translation is disabled. Thevalid RMLS values and their meaning are

implementation-dependent powers of 2, 2j,where 12 � j � m.

38 Interrupt Little-Endian (ILE)

This bit is part of the optional Little-Endianfacility; see the section entitled “Little-Endian”in Book I.

If the Little-Endian facility is implemented, thecontent of ILE is copied into MSRLE on someinterrupts (only those that set MSRHV to 0; seeSection 5.5 on page 65) to establish theEndian environment for the interrupt handling

If the Little-Endian facility is not implemented,this bit is treated as reserved.

39:59 Reserved

60:61 Logical Partitioning Environment Selector(LPES)

Three of the four LPES values are sup-ported. The 0b10 value is reserved.

60 LPES0

Controls whether External interrupts setMSRHV to 1 or leave it unchanged.

61 LPES1

Controls how storage is accessed whenaddress translation is disabled, and whether asubset of interrupts set MSRHV to 1.

62 Real Mode Caching Inhibited Bit (RMI)

The RMI bit affects the manner in which stor-age accesses are performed in hypervisormode when address translation is disabled(see Section 4.2.6.2 on page 30).

// RMLS ILE // LPES RMI HDICE0 35 38 39 60 62 63

LPES1=0 provides an environment inwhich only the hypervisor can run withaddress translation disabled and in whichall interrupts invoke the hypervisor. Thisvalue (along with MSRHV=1) can also beused in a system that is not partitioned, topermit the operating system to access allsystem resources.

Setting LPES0:1 to 0b00 can be used toconfigure LPAR environments similar tothe environment selected by the LPES biton the POWER4 processor.

Programming Note


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63 Hypervisor Decrementer Interrupt Condi-tionally Enable (HDICE)

0 Hypervisor Decrementer interrupts aredisabled.

1 Hypervisor Decrementer interrupts areenabled if permitted by MSREE, MSRHV,and MSRPR; see Section 5.5.12 onpage 72.

See Section 4.2.6 on page 29 (including subsections)and Section 4.10 on page 45 for a description of howstorage accesses are affected by the setting of LPES1,RMLS, and RMI. See Section 5.5 on page 65 for adescription of how the setting of LPES0:1 affects theprocessing of interrupts.

1.7.2 Real Mode Offset Register (RMOR)

The layout of the Real Mode Offset Register (RMOR) isshown in Figure 3 below.

All other fields are reserved.

The supported RMO values are the non-negative multi-ples of 2s, where 2s is the smallest implementation-dependent limit value representable by the contents ofthe Real Mode Limit Selector field of the LPCR.

Figure 3. Real Mode Offset Register

The contents of the RMOR affect how some storageaccesses are performed as described in Section 4.2.6on page 29 and Section 4.2.7 on page 31.

1.7.3 Hypervisor Real Mode Offset Register (HRMOR)

The layout of the Hypervisor Real Mode Offset Register(HRMOR) is shown in Figure 4 below.


The supported HRMO values are the non-negativemultiples of 2r, where r is an implementation-dependentvalue and 12 � r � 26.

Figure 4. Hypervisor Real Mode Offset Register

The contents of the HRMOR affect how some storageaccesses are performed as described in Section 4.2.6on page 29 and Section 4.2.7 on page 31.

Because in real addressing mode all stor-age is not Caching Inhibited (unless theReal Mode Caching Inhibited bit is 1),software should not map a Caching Inhib-ited virtual page to storage that is treatedas non-Guarded in real addressing mode.Doing so could permit storage locations inthe virtual page to be copied into thecache, which could lead to violations ofthe requirement given in Section 4.8.2 forchanging the value of the I bit. See alsoSection 8.2 on page 90.

Programming Note

// RMO0 2 63

Bits Name Description2:63 RMO Real Mode Offset

// HRMO0 2 63

Bits Name Description2:63 HRMO Hypervisor Real Mode Offset


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1.7.4 Logical PartitionIdentification Register (LPIDR)

The layout of the Logical Partition Identification Regis-ter (LPIDR) is shown in Figure 5 below.

Figure 5. Logical Partition Identification Register

The contents of the LPIDR identify the partition towhich the processor is assigned, affecting operationsnecessary to manage the coherency of some transla-tion lookaside buffers (see Section 4.12.1 on page 57and Chapter 7 on page 85).

The supported LPID values consist of all non-negativevalues that are less than an implementation-dependentpower of 2, 2q, where 2q � (the maximum number ofprocessors in a system) � 2.

1.7.5 Other Hypervisor Resources

In addition to the resources described above, the fol-lowing resources are hypervisor resources, accessibleto software only when the processor is in hypervisormode.

� All implementation-specific resources, includingimplementation-specific registers (e.g., “HID” reg-isters), that control hardware functions or affect theresults of instruction execution. Examples includeresources that disable caches, disable hardwareerror detection, set breakpoints, control powermanagement, or significantly affect performance.

� ME bit of the MSR

� SDR1, EAR (if implemented), Time Base, PIR,Hypervisor Decrementer, DABR, DABRX, andPURR. (Note: Although the Time Base and thePURR can be altered only by a hypervisor pro-gram, the Time Base can be read by all programsand the PURR can be read when the processor isin privileged state.)

The contents of a hypervisor resource can be modifiedby the execution of an instruction (e.g., mtspr) only inhypervisor state (MSRHV PR = 0b10). Whether anattempt to modify the contents of a given hypervisorresource, other than MSRME, in privileged but non-hypervisor state (MSRHV PR = 0b00) is ignored (i.e.,treated as a no-op) or causes a Privileged Instructiontype Program interrupt is implementation-dependent.An attempt to modify MSRME in privileged but non-hypervisor state is ignored (i.e., the bit is not changed).

The tlbie, tlbiel, tlbia, and tlbsync instructions can beexecuted only in hypervisor state; see the descriptionsof these instructions on pages 53 and 56.

In general, if software violates a rule that is stated in theBooks using the word “must” (e.g., “this field must beset to 0”) the results are boundedly undefined. Theonly exception is that if hypervisor software violatessuch a rule that pertains to the contents of a hypervisorresource, to accessing storage in real addressingmode, or to using the tlbie and tlbsync instructions,the results are undefined, and may include alteringresources belonging to other partitions, causing thesystem to “hang”, etc.

LPID0 31

Bits Name Description0:31 LPID Logical Partition Identifier

On some implementations, software must preventthe execution of a tlbie instruction on any proces-sor for which the contents of the LPIDR is the sameas on the processor on which the LPIDR is beingmodified or is the same as the new value beingwritten to the LPIDR. This restriction can be metwith less effort if one partition identity is used onlyon processors on which no tlbie instruction is everexecuted. This partition can be thought of as thetransfer partition used exclusively to move a pro-cessor from one partition to another.

Programming Note

Because the SPRs listed above are privileged forwriting, an attempt to modify the contents of any ofthese SPRs in problem state (MSRPR=1) usingmtspr causes a Privileged Instruction type Pro-gram exception, and similarly for MSRME.

Programming Note


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1.7.6 Sharing Hypervisor Resources

Some hypervisor resources may be shared among pro-cessors. Programs that modify these resources mustbe aware of this sharing, and must allow for the factthat changes to these resources may affect more thanone processor. The following resources may be sharedamong processors.

� RMOR (see Section 1.7.2.)� HRMOR (see Section 1.7.3.)� LPIDR (see Section 1.7.4.)� PIR (see Section 3.3.6.)� SDR1 (see Section 4.5.2.)� Time Base (see Section 6.2.)� Hypervisor Decrementer (see Section 6.4.)� certain implementation-specific registers

See Book IV for information about the set of resourcesthat are shared for a given implementation.

Processors that share any of the resources listedabove, with the exception of the PIR and the HRMOR,must be in the same partition.

For each field of the LPCR except the RMI field and theHDICE field, software must ensure that the contents ofthe field are identical among all processors that are inthe same partition and are in a state such that the con-tents of the field could have side effects. (E.g., soft-ware must ensure that the contents of LPCRLPES areidentical among all processors that are in the same par-tition and are not in hypervisor state.) For the HDICEfield, software must ensure that the contents of the fieldare identical among all processors that share theHypervisor Decrementer and are in a state such thatthe contents of the field could have side effects. (Thereare no identity requirements for the RMI field.)


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Chapter 2. Branch Processor

2.1 Branch Processor Overview . . . . . . . 92.2 Branch Processor Registers . . . . . . . 92.2.1 Machine Status Save/Restore Regis-

ters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.2.2 Hypervisor Machine Status Save/

Restore Registers . . . . . . . . . . . . . . . . . . 9

2.2.3 Machine State Register . . . . . . . . 102.3 Branch Processor Instructions . . . . 122.3.1 System Linkage Instructions . . . . 12

2.1 Branch Processor OverviewThis chapter describes the details concerning the regis-ters and the privileged instructions implemented in theBranch Processor that are not covered in Book I, Pow-erPC User Instruction Set Architecture.

2.2 Branch Processor Registers

2.2.1 Machine Status Save/Restore Registers

When an interrupt occurs, the state of the machine issaved in the Machine Status Save/Restore registers(SRR0 and SRR1) unless the interrupt is an interruptthat sets HSRR0 and HSRR1. The contents of theseregisters is used to restore machine state when an rfidinstruction is executed.

Figure 6. Save/Restore Registers

2.2.2 Hypervisor Machine Status Save/Restore Registers

When a Hypervisor Decrementer interrupt occurs, thestate of the machine is saved in the HypervisorMachine Status Save/Restore registers (HSRR0 andHSRR1). The contents of these registers is used to

restore machine state when an hrfid instruction is exe-cuted.

Figure 7. Hypervisor Save/Restore Registers

SRR0 //0 62 63

SRR10 63

HSRR0 //0 62 63

HSRR10 63

Chapter 2. Branch Processor 9

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2.2.3 Machine State Register

The Machine State Register (MSR) is a 64-bit register.This register defines the state of the processor. Oninterrupt, the MSR bits are altered in accordance withFigure 35 on page 65. The MSR can also be modifiedby the mtmsr[d], rfid, and hrfid instructions. It can beread by the mfmsr instruction.

Figure 8. Machine State Register

Below are shown the bit definitions for the MachineState Register.

Bit Description

0 Sixty-Four-Bit Mode (SF)

0 The processor is in 32-bit mode.1 The processor is in 64-bit mode.

1:2 Reserved

3 Hypervisor State (HV)

0 The processor is not in hypervisor state.1 If MSRPR=0 the processor is in hypervisor

state; otherwise the processor is not inhypervisor state.

4:46 Reserved

47 Reserved

48 External Interrupt Enable (EE)

0 External and Decrementer interrupts aredisabled.

1 External and Decrementer interrupts areenabled.

This bit also affects whether Hypervisor Dec-rementer interrupts are enabled;Section 5.5.12 on page 72.

49 Problem State (PR)

0 The processor is in privileged state.1 The processor is in problem state.

50 Floating-Point Available (FP)

0 The processor cannot execute any float-ing-point instructions, including floating-point loads, stores, and moves.

1 The processor can execute floating-pointinstructions.

51 Machine Check Interrupt Enable (ME)

0 Machine Check interrupts are disabled.1 Machine Check interrupts are enabled.

This bit is a hypervisor resource; seeSection 1.7, “Logical Partitioning (LPAR)” onpage 5.

52 Floating-Point Exception Mode 0 (FE0)

See below.

53 Single-Step Trace Enable (SE)

0 The processor executes instructions nor-mally.

1 The processor generates a Single-Steptype Trace interrupt after successfullycompleting the execution of the nextinstruction, unless that instruction is hrfidor rfid, which are never traced. Success-ful completion means that the instructioncaused no other interrupt.

54 Branch Trace Enable (BE)

0 The processor executes branch instruc-tions normally.

1 The processor generates a Branch typeTrace interrupt after completing the exe-cution of a branch instruction, whether ornot the branch is taken. See Book IV,PowerPC Implementation Features.

Branch tracing may not be present on allimplementations. If the function is not imple-mented, this bit is treated as reserved.

55 Floating-Point Exception Mode 1 (FE1)

See below.

56:57 Reserved

58 Instruction Relocate (IR)

0 Instruction address translation is disabled.

MSR0 63

The privilege state of the processor isdetermined by MSRHV and MSRPR, asfollows.

HV PR

0 0 privileged0 1 problem1 0 privileged and hypervisor1 1 problem

MSRHV can be set to 1 only by the Sys-tem Call instruction and some interrupts.It can be set to 0 only by the rfid and hrfidinstructions.

Programming Note

Any instruction that sets MSRPR to 1 alsosets MSREE, MSRIR, and MSRDR to 1.

The only instructions that can alterMSRME are the rfid and hrfid instructions.

Programming Note

Programming Note


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1 Instruction address translation is enabled.

59 Data Relocate (DR)

0 Data address translation is disabled.Effective Address Overflow (EAO) (seeBook I) does not occur.

1 Data address translation is enabled. EAOcauses a Data Storage interrupt.

60 Reserved

61 Performance Monitor Mark (PMM)

This bit is part of the optional PerformanceMonitor facility; see Appendix E. If the Perfor-mance Monitor facility is not implemented ordoes not use this bit, this bit is treated asreserved.

62 Recoverable Interrupt (RI)

0 Interrupt is not recoverable.1 Interrupt is recoverable.

Additional information about the use of this bitis given in Sections 5.4, “Interrupt Processing”on page 62, 5.5.1, “System Reset Interrupt”on page 66, and 5.5.2, “Machine Check Inter-rupt” on page 66.

63 Little-Endian Mode (LE)

This bit is part of the optional Little-Endianfacility; see the section entitled “Little-Endian”in Book I.

If the Little-Endian facility is implemented, thisbit has the following meaning.

0 The processor is in Big-Endian mode.1 The processor is in Little-Endian mode.

If the Little-Endian facility is not implemented,this bit is treated as reserved.

The Floating-Point Exception Mode bits FE0 and FE1are interpreted as shown below. For further details seeBook I, PowerPC User Instruction Set Architecture.

See the Programming Note in the defini-tion of MSRPR.

See the Programming Note in the defini-tion of MSRPR.

FE0 FE1 Mode0 0 Ignore Exceptions0 1 Imprecise Nonrecoverable1 0 Imprecise Recoverable1 1 Precise

Programming Note

Programming Note


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2.3 Branch Processor Instructions

2.3.1 System Linkage Instructions

These instructions provide the means by which a pro-gram can call upon the system to perform a service,and by which the system can return from performing aservice or from processing an interrupt.

The System Call instruction is described in Book I,PowerPC User Instruction Set Architecture, but only atthe level required by an application programmer. Acomplete description of this instruction appears below.

System Call SC-form

sc LEV

[POWER mnemonic: svca]

SRR0 �iea CIA + 4SRR133:36 42:47 � 0SRR10:32 37:41 48:63 � MSR0:32 37:41 48:63MSR � new_value (see below)NIA � 0x0000_0000_0000_0C00

The effective address of the instruction following theSystem Call instruction is placed into SRR0. Bits 0:32,37:41, and 48:63 of the MSR are placed into the corre-sponding bits of SRR1, and bits 33:36 and 42:47 ofSRR1 are set to zero.

Then a System Call interrupt is generated. The inter-rupt causes the MSR to be set as described inSection 5.5, “Interrupt Definitions” on page 65. Thesetting of the MSR is affected by the contents of theLEV field. LEV values greater than 1 are reserved.Bits 0:5 of the LEV field (instruction bits 20:25) aretreated as a reserved field.

The interrupt causes the next instruction to be fetchedfrom effective address 0x0000_0000_0000_0C00.

This instruction is context synchronizing.

Special Registers Altered:SRR0 SRR1 MSR

17 /// /// // LEV // 1 /0 6 11 16 20 27 30 31

sc serves as both a basic and an extended mne-monic. The Assembler will recognize an sc mne-monic with one operand as the basic form, and ansc mnemonic with no operand as the extendedform. In the extended form the LEV operand isomitted and assumed to be 0.

If LEV=1 the hypervisor is invoked.

If LPES1=1, executing this instruction with LEV=1is the only way that executing an instruction cancause hypervisor state to be entered.

Because this instruction is not privileged, it is possi-ble for application software to invoke the hypervi-sor. However, such invocation should beconsidered a programming error.

Programming Note

Programming Note


Version 2.02

Return From Interrupt Doubleword XL-form

rfid

MSR0 � SRR10 | SRR11MSR51 � (MSR3 & SRR151) | ((¬MSR3) & MSR51)MSR3 � MSR3 & SRR13

MSR48 � SRR148 | SRR149 MSR58 � SRR158 | SRR149MSR59 � SRR159 | SRR149MSR1:2 4:32 37:41 49:50 52:57 60:63�SRR11:2 4:32 37:41 49:50 52:57 60:63NIA �iea SRR00:61 || 0b00

The result of ORing bits 0 and 1 of SRR1 is placed intoMSR0. If MSR3=1 then bits 3 and 51 of SRR1 areplaced into the corresponding bits of the MSR. Theresult of ORing bits 48 and 49 of SRR1 is placed intoMSR48. The result of ORing bits 58 and 49 of SRR1 isplaced into MSR58. The result of ORing bits 59 and 49of SRR1 is placed into MSR59. Bits 1:2, 4:32, 37:41,49:50, 52:57, and 60:63 of SRR1 are placed in the cor-responding bits of the MSR.

If the new MSR value does not enable any pendingexceptions, then the next instruction is fetched, undercontrol of the new MSR value, from the addressSRR00:61 || 0b00 (when SF=1 in the new MSR value)or 320 || SRR032:61 || 0b00 (when SF=0 in the new MSRvalue). If the new MSR value enables one or morepending exceptions, the interrupt associated with thehighest priority pending exception is generated; in thiscase the value placed into SRR0 or HSRR0 by theinterrupt processing mechanism (see Section 5.4,“Interrupt Processing” on page 62) is the address of theinstruction that would have been executed next had theinterrupt not occurred.

This instruction is privileged and context synchronizing.

Special Registers Altered:MSR

Hypervisor Return From InterruptDoubleword XL-form

hrfid

MSR0 � HSRR10 | HSRR11MSR48 � HSRR148 | HSRR149MSR58 � HSRR158 | HSRR149MSR59 � HSRR159 | HSRR149MSR1:32 37:41 49:57 60:63 � HSRR11:32 37:41 49:57 60:63NIA � HSRR00:61 || 0b00

The result of ORing bits 0 and 1 of HSRR1 is placedinto MSR0. The result of ORing bits 48 and 49 ofHSRR1 is placed into MSR48. The result of ORing bits58 and 49 of HSRR1 is placed into MSR58. The resultof ORing bits 59 and 49 of HSRR1 is placed intoMSR59. Bits 1:32, 37:41, 49:57, and 60:63 of HSRR1are placed into the corresponding bits of the MSR.

If the new MSR value does not enable any pendingexceptions, then the next instruction is fetched, undercontrol of the new MSR value, from the addressHSRR00:61 || 0b00 (when SF=1 in the new MSR value)or 320 || HSRR032:61 || 0b00 (when SF=0 in the newMSR value). If the new MSR value enables one ormore pending exceptions, the interrupt associated withthe highest priority pending exception is generated; inthis case the value placed into SRR0 or HSRR0 by theinterrupt processing mechanism (see Section 5.4,“Interrupt Processing” on page 62) is the address of theinstruction that would have been executed next had theinterrupt not occurred.

This instruction is privileged and context synchronizing,and can be executed only in hypervisor state. If it isexecuted in privileged but non-hypervisor state either aPrivileged Instruction type Program interrupt occurs orthe results are boundedly undefined.


19 /// /// /// 18 /0 6 11 16 21 31

If this instruction sets MSRPR to 1, it also setsMSREE, MSRIR, and MSRDR to 1.

On processors prior to POWER4+, setting MSRPRto 1 did not cause MSREE to be set to 1.

Programming Note

19 /// /// /// 274 /0 6 11 16 21 31

If this instruction sets MSRPR to 1, it also setsMSREE, MSRIR, and MSRDR to 1.

Programming Note


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Version 2.02

Chapter 3. Fixed-Point Processor

3.1 Fixed-Point Processor Overview . . 153.2 Special Purpose Registers . . . . . . . 153.3 Fixed-Point Processor Registers . . 153.3.1 Data Address Register. . . . . . . . . 153.3.2 Data Storage Interrupt

Status Register . . . . . . . . . . . . . . . . . . . 163.3.3 Software-use SPRs . . . . . . . . . . . 163.3.4 Control Register. . . . . . . . . . . . . . 17

3.3.5 Processor Version Register . . . . . 173.3.6 Processor Identification Register . 173.4 Fixed-Point Processor Instructions . 183.4.1 OR Instruction . . . . . . . . . . . . . . . 183.4.2 Move To/From System Register

Instructions . . . . . . . . . . . . . . . . . . . . . . 18

3.1 Fixed-Point Processor Over-viewThis chapter describes the details concerning the regis-ters and the privileged instructions implemented in theFixed-Point Processor that are not covered in Book I,PowerPC User Instruction Set Architecture.

3.2 Special Purpose RegistersSpecial Purpose Registers (SPRs) are read and writtenusing the mfspr (page 21) and mtspr (page 19)instructions. Most SPRs are defined in other chaptersof this book; see the index to locate those definitions.

3.3 Fixed-Point Processor Reg-isters

3.3.1 Data Address Register

The Data Address Register (DAR) is a 64-bit registerthat is set by the Machine Check, Data Storage, DataSegment, and Alignment interrupts; see Sections 5.5.2,5.5.3, 5.5.4, and 5.5.8. In general, when one of theseinterrupts occurs the DAR is set to an effective addressassociated with the storage access that caused theinterrupt, with the high-order 32 bits of the DAR set to 0if the interrupt occurs in 32-bit mode.

Figure 9. Data Address Register

DAR0 63

Chapter 3. Fixed-Point Processor 15

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3.3.2 Data Storage InterruptStatus Register

The Data Storage Interrupt Status Register (DSISR) isa 32-bit register that is set by the Machine Check, DataStorage, Data Segment, and Alignment interrupts; seeSections 5.5.2, 5.5.3, 5.5.4, and 5.5.8. In general, whenone of these interrupts occurs the DSISR is set to indi-cate the cause of the interrupt.

Figure 10. Data Storage Interrupt Status Register

DSISR bits may be treated as reserved in a givenimplementation if they are specified as being set eitherto 0 or to an undefined value for all interrupts that setthe DSISR (including implementation-dependent set-ting, e.g. by the Machine Check interrupt or by imple-mentation-specific interrupts; see the Book IV for theimplementation).

3.3.3 Software-use SPRs

SPRG0 through SPRG3 are 64-bit registers providedfor use by privileged software.

Figure 11. SPRs for use by privileged non-hypervisor programs

SPRG0, SPRG1, and SPRG2 are privileged registers.SPRG3 is a privileged register except that the contentsmay be copied to a GPR in Problem state whenaccessed using the mfspr instruction.

HSPRG0 and HSPRG1 are 64-bit registers providedfor use by hypervisor programs.

Figure 12. SPRs for use by hypervisor programs

DSISR0 31

SPRG0

SPRG1SPRG2SPRG3

0 63

Neither the contents of the SPRGs, nor accessingthem using mtspr or mfspr, has a side effect onthe operation of the processor. One or more of theregisters is likely to be needed by non-hypervisorinterrupt handler programs (e.g., as scratch regis-ters and/or pointers to per processor save areas).

Operating systems must ensure that no sensitivedata are left in SPRG3 when a problem state pro-gram is dispatched, and operating systems forsecure systems must ensure that SPRG3 cannotbe used to implement a “covert channel” betweenproblem state programs. These requirements canbe satisfied by clearing SPRG3 before passingcontrol to a program that will run in problem state.

In implementations prior to POWER5 that providedLPAR facilities, SPRG0 was treated as a privilegedSPR except that the execution of a mtspr instruc-tion would alter the contents only if MSRHV = 1.

HSPRG0HSPRG1

0 63

Neither the contents of the HSPRGs, nor accessingthem using mtspr or mfspr, has a side effect onthe operation of the processor. One or more of theregisters is likely to be needed by hypervisor inter-rupt handler programs (e.g., as scratch registersand/or pointers to per processor save areas).

Programming Note

Programming Note


Version 2.02

3.3.4 Control Register

The Control Register (CTRL) is a 32-bit register thatcontrols an external I/O pin. This signal may be usedfor the following:

� driving the RUN Light on a system operator panel� External interrupt routing� Performance Monitor Counter incrementing (see

Appendix E, “Example Performance Monitor(Optional)” on page 107)

All other fields are implementation-dependent.

Figure 13. Control Register

The CTRL RUN can be used by the operating systemto indicate when the processor is doing useful work.

The contents of the CTRL can be written by the mtsprinstruction and read by the mfspr instruction. Writeaccess to the CTRL is privileged. Reads can be per-formed in privileged or problem state.

3.3.5 Processor Version Register

The Processor Version Register (PVR) is a 32-bit read-only register that contains a value identifying the ver-sion and revision level of the processor. The contentsof the PVR can be copied to a GPR by the mfsprinstruction. Read access to the PVR is privileged; writeaccess is not provided.

Figure 14. Processor Version Register

The PVR distinguishes between processors that differin attributes that may affect software. It contains twofields.

Version A 16-bit number that identifies the versionof the processor. Different version num-bers indicate major differences betweenprocessors, such as which optional facili-ties and instructions are supported.

Revision A 16-bit number that distinguishes betweenimplementations of the version. Differentrevision numbers indicate minor differencesbetween processors having the same ver-sion number, such as clock rate and Engi-neering Change level.

Version numbers are assigned by the PowerPC Archi-tecture process. Revision numbers are assigned by animplementation-defined process.

3.3.6 Processor Identification Register

The Processor Identification Register (PIR) is a 32-bitregister that contains a value that can be used to distin-guish the processor from other processors in the sys-tem. The contents of the PIR can be copied to a GPRby the mfspr instruction. Read access to the PIR isprivileged; write access, if provided, is described in theBook IV, PowerPC Implementation Features documentfor the implementation.

Figure 15. Processor Identification Register

The means by which the PIR is initialized are imple-mentation-dependent (see Book IV).

The PIR is a hypervisor resource; see Section 1.7,“Logical Partitioning (LPAR)” on page 5.

/// RUN0 31

Bit Name Description31 RUN Run state bit

Version Revision0 16 31

PROCID0 31

Bits Name Description0:31 PROCID Processor ID


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3.4 Fixed-Point Processor Instructions

3.4.1 OR Instruction

Some forms of the OR instruction in which RS = RA =RB provide a hint to the processor regarding the prioritylevel of the program. The supported encodings areshown in Figure 16. No hint is provided if the privilegestate of the processor executing the instruction is lowerthan the privilege indicated in the figure.

Figure 16. Priority hint levels for or Rx,Rx,Rx

3.4.2 Move To/From System Reg-ister Instructions

The Move To Special Purpose Register and MoveFrom Special Purpose Register instructions aredescribed in Book I, PowerPC User Instruction SetArchitecture, but only at the level available to an appli-cation programmer. For example, no mention is madethere of registers that can be accessed only in privi-leged state. The descriptions of these instructionsgiven below extend the descriptions given in Book I, butdo not list Special Purpose Registers that are defined inBook IV, PowerPC Implementation Features. In thedescriptions of these instructions given below, the“defined” SPR numbers are the SPR numbers shown inthe figure for the instruction and the SPR numbersdefined in Book IV for the instruction, and similarly for“defined” registers.

Extended mnemonics

Extended mnemonics are provided for the mtspr andmfspr instructions so that they can be coded with theSPR name as part of the mnemonic rather than as anumeric operand. See Appendix A, “AssemblerExtended Mnemonics” on page 97.

Rx Priority Privileged

31 very low yes

1 low no

6 medium low no

2 medium (normal) no

5 medium high yes

3 high yes

7 very high hypv


Version 2.02

Move To Special Purpose RegisterXFX-form

mtspr SPR,RS

n � spr5:9 || spr0:4if length(SPREG(n)) = 64 then SPREG(n) � (RS)else SPREG(n) � (RS)32:63

The SPR field denotes a Special Purpose Register,encoded as shown in Figure 17. The contents of regis-ter RS are placed into the designated Special PurposeRegister. For Special Purpose Registers that are 32bits long, the low-order 32 bits of RS are placed into theSPR.

For this instruction, SPRs TBL and TBU are treated asseparate 32-bit registers; setting one leaves the otherunaltered.

spr0=1 if and only if writing the register is privileged.Execution of this instruction specifying a defined andprivileged register when MSRPR=1 causes a PrivilegedInstruction type Program interrupt. Execution of thisinstruction specifying a hypervisor resource whenMSRHV PR = 0b00 either has no effect or causes a Priv-ileged Instruction type Program interrupt (seeSection 1.7 on page 5).

Execution of this instruction specifying an SPR numberthat is not defined for the implementation causes eitheran Illegal Instruction type Program interrupt or one ofthe following.

� if spr0=0: boundedly undefined results� if spr0=1:

- if MSRPR=1: Privileged Instruction type Pro-gram interrupt

- if MSRPR=0 and MSRHV=0: boundedly unde-fined results

- if MSRPR=0 and MSRHV=1: undefined results

If the SPR field contains a value that is shown inFigure 17but corresponds to an optional Special Pur-pose Register that is not provided by the implementa-tion, the effect of executing this instruction is the sameas if the SPR number were not shown in the figure.

Special Registers Altered:See Figure 17.

Figure 17. SPR encodings for mtspr

31 RS spr 467 /0 6 11 21 31

decimalSPR1

spr5:9 spr0:4

Register Name

Privi-leged

1 00000 00001 XER no8 00000 01000 LR no9 00000 01001 CTR no

18 00000 10010 DSISR yes19 00000 10011 DAR yes22 00000 10110 DEC yes25 00000 11001 SDR1 5 hypv26 00000 11010 SRR0 yes27 00000 11011 SRR1 yes29 00000 11101 ACCR yes

152 00100 11000 CTRL yes272 01000 10000 SPRG0 yes273 01000 10001 SPRG1 yes274 01000 10010 SPRG2 yes275 01000 10011 SPRG3 yes

282 01000 11010 EAR 2,5 hypv284 01000 11100 TBL 5 hypv285 01000 11101 TBU 5 hypv304 01001 10000 HSPRG0 5 hypv305 01001 10001 HSPRG1 5 hypv309 01001 10101 PURR 5 hypv310 01001 10110 HDEC 5 hypv312 01001 11000 RMOR 5 hypv313 01001 11001 HRMOR 5 hypv314 01001 11010 HSRR0 5 hypv315 01001 11011 HSRR1 5 hypv318 01001 11110 LPCR 5 hypv319 01001 11111 LPIDR 5 hypv

784-799 11000 1xxxx perf_mon3 yes1012 11111 10101 DABR 4,5 hypv1015 11111 10111 DABRX 4,5 hypv

1 Note that the order of the two 5-bit halves of the SPR number is reversed.

2 Part of the optional External Control facility (see Section 8.1).

3 Part of the optional Performance Monitor facility

(see Appendix E).4 Part of the Data Address Breakpoint mechanism

(see Section 4.7).5 This register is a hypervisor resource, and can be

modified by this instruction only in hypervisor state (see Section 1.7).

All SPR numbers not shown above, or in Figure 18, or in Book IV are reserved.


Version 2.02

For the mtspr and mfspr instructions, the SPRnumber coded in assembler language does notappear directly as a 10-bit binary number in theinstruction. The number coded is split into two 5-bithalves that are reversed in the instruction, with thehigh-order 5 bits appearing in bits 16:20 of theinstruction and the low-order 5 bits in bits 11:15.This maintains compatibility with POWER SPRencodings, in which these two instructions haveonly a 5-bit SPR field occupying bits 11:15.

On processors prior to POWER4+ the following dif-ferences exist.� SPR alias number 259 (SPRG3 - not privi-

leged) is not implemented.� HDEC and PURR are not implemented.� SPRG0 is treated as a hypervisor register by

this instruction.

For a discussion of software synchronizationrequirements when altering certain Special Pur-pose Registers, see Chapter 7. “SynchronizationRequirements for Context Alterations” on page 85.

For a discussion of POWER compatibility withrespect to SPR numbers not shown in the instruc-tion descriptions for mtspr and mfspr, see theappendix entitled “Incompatibilities with thePOWER Architecture” in Book I, PowerPC UserInstruction Set Architecture.

Compiler and Assembler Note

Programming Note

Programming Note

Compatibility Note


Version 2.02

Move From Special Purpose RegisterXFX-form

mfspr RT,SPR

n � spr5:9 || spr0:4if length(SPREG(n)) = 64 then RT � SPREG(n)else RT � 320 || SPREG(n)

The SPR field denotes a Special Purpose Register,encoded as shown in Figure 18. The contents of thedesignated Special Purpose Register are placed intoregister RT. For Special Purpose Registers that are 32bits long, the low-order 32 bits of RT receive the con-tents of the Special Purpose Register and the high-order 32 bits of RT are set to zero.

spr0=1 if and only if reading the register is privileged.Execution of this instruction specifying a defined andprivileged register when MSRPR=1 causes a PrivilegedInstruction type Program interrupt.

Execution of this instruction specifying an SPR numberthat is not defined for the implementation causes eitheran Illegal Instruction type Program interrupt or one ofthe following.

� if spr0=0: boundedly undefined results� if spr0=1:

- if MSRPR=1: Privileged Instruction type Pro-gram interrupt

- if MSRPR=0: boundedly undefined results

If the SPR field contains a value that is shown inFigure 18 but corresponds to an optional Special Pur-pose Register that is not provided by the implementa-tion, the effect of executing this instruction is the sameas if the SPR number were not shown in the figure.

Special Registers Altered:None

Figure 18. SPR encodings for mfspr

31 RT spr 339 /0 6 11 21 31

See the Notes that appear with mtspr.

On processors prior to POWER4+ the following dif-ferences exist.� SPR alias number 259 (SPRG3) is not imple-

mented.� HDEC and PURR are not implemented.

Note

Programming Note

decimalSPR1

spr5:9 spr0:4

Register Name

Privi-leged

1 00000 00001 XER no8 00000 01000 LR no9 00000 01001 CTR no

18 00000 10010 DSISR yes19 00000 10011 DAR yes22 00000 10110 DEC yes25 00000 11001 SDR1 yes26 00000 11010 SRR0 yes27 00000 11011 SRR1 yes29 00000 11101 ACCR yes

136 00100 01000 CTRL no272 01000 10000 SPRG0 yes273 01000 10001 SPRG1 yes274 01000 10010 SPRG2 yes

259,275 01000 n0011 SPRG3 5 no,yes

282 01000 11010 EAR 2 yes287 01000 11111 PVR yes304 01001 10000 HSPRG0 hypv305 01001 10001 HSPRG1 hypv309 01001 10101 PURR 5 yes310 01001 10110 HDEC yes312 01001 11000 RMOR hypv313 01001 11001 HRMOR hypv314 01001 11010 HSRR0 hypv315 01001 11011 HSRR1 hypv318 01001 11110 LPCR hypv319 01001 11111 LPIDR hypv

768-799 11000 nxxxx perf_mon 3,5 no,yes1013 11111 10101 DABR 4 yes1015 11111 10111 DABRX 4 yes1023 11111 11111 PIR yes


2 Part of the optional External Control facility (see Section 8.1).

3 Part of the optional Performance Monitor facility

(see Appendix E).4 Part of the Data Address Breakpoint mechanism

(see Section 4.7). 5 Reading the SPR is privileged if and only if n=1.

Moving from the Time Base (TB and TBU) is accomplished with the mftb instruction, described in Book II.

All SPR numbers not shown above, or in Figure 17, or in Book IV are reserved.


Version 2.02

Move To Machine State RegisterDoubleword X-form

mtmsrd RS,L

if L = 0 then MSR0 � (RS)0 | (RS)1

MSR48 � (RS)48 | (RS)49 MSR58 � (RS)58 | (RS)49 MSR59 � (RS)59 | (RS)49 MSR1:2 4:47 49:50 52:57 60:63 � (RS)1:2 4:47 49:50 52:57 60:63else MSR48 62 � (RS)48 62

The MSR is set based on the contents of register RSand of the L field.

L=0:

The result of ORing bits 0 and 1 of register RS isplaced into MSR0. The result of ORing bits 48 and49 of register RS is placed into MSR48. The resultof ORing bits 58 and 49 of register RS is placedinto MSR58. The result of ORing bits 59 and 49 ofregister RS is placed into MSR59. Bits 1:2, 4:47,49:50, 52:57, and 60:63 of register RS are placedinto the corresponding bits of the MSR.

L=1:

Bits 48 and 62 of register RS are placed into thecorresponding bits of the MSR. The remaining bitsof the MSR are unchanged.

This instruction is privileged.

If L=0 this instruction is context synchronizing exceptwith respect to alterations to the LE bit; see Chapter7. “Synchronization Requirements for Context Alter-ations” on page 85. If L=1 this instruction is executionsynchronizing; in addition, the alterations of the EE andRI bits take effect as soon as the instruction completes.


Except in the mtmsrd instruction description in thissection, references to “mtmsrd” in Books I - III implyeither L value unless otherwise stated or obvious fromcontext (e.g., a reference to an mtmsrd instruction thatmodifies an MSR bit other than the EE or RI bit impliesL=0).

31 RS /// L /// 178 /0 6 11 15 16 21 31

Warning: Processors that comply with versions ofthe architecture that precede Version 2.01 ignorethe L field. These processors set the MSR as if Lwere 0, and perform synchronization as if L were 1.Therefore software that uses mtmsrd and will runon such processors must obey the following rules.

1. If L=1, the contents of bits of register RS otherthan bits 48 and 62 must be such that if L were0 the instruction would not alter the contents ofthe corresponding MSR bits.

2. If L=0 and the instruction alters the contents ofany of the MSR bits listed below, the instruc-tion must be followed by a context synchroniz-ing instruction or event in order to ensure thatthe context alteration caused by the mtmsrdinstruction has taken effect on such proces-sors; Chapter 7.

SF, PR, FP, FE0, FE1, SE, BE, US, IR, DR

To obtain the best performance on processorsthat comply with Version 2.01 of the architec-ture and with subsequent versions, if the con-text synchronizing instruction is isync theisync should immediately follow the mtmsrd.(Some such processors treat an isync instruc-tion that immediately follows an mtmsrdinstruction having L=0 as a no-op, therebyavoiding the performance penalty of a secondcontext synchronization.)

If this instruction sets MSRPR to 1, it also setsMSREE, MSRIR, and MSRDR to 1. On processorsprior to POWER4+, the setting of MSRPR does notaffect the setting of MSREE.

This instruction does not alter MSRHV or MSRME.

If the only MSR bits to be altered are MSREE RI, toobtain the best performance L=1 should be used.

Programming Note

Programming Note


Version 2.02

Move From Machine State RegisterX-form

mfmsr RT

RT � MSR

The contents of the MSR are placed into register RT.



If MSREE=0 and an External or Decrementerexception is pending, executing an mtmsrdinstruction that sets MSREE to 1 will cause theExternal or Decrementer interrupt to occur beforethe next instruction is executed, if no higher priorityexception exists (see Section 5.8, “Interrupt Priori-ties” on page 76). Similarly, if a Hypervisor Decre-menter interrupt is pending, execution of theinstruction by the hypervisor causes a HypervisorDecrementer interrupt to occur if HDICE=1.

For a discussion of software synchronizationrequirements when altering certain MSR bits, seeChapter 7.

mtmsrd serves as both a basic and an extendedmnemonic. The Assembler will recognize an mtm-srd mnemonic with two operands as the basicform, and an mtmsrd mnemonic with one operandas the extended form. In the extended form the Loperand is omitted and assumed to be 0.

Programming Note

Programming Note

31 RT /// /// 83 /0 6 11 16 21 31


Version 2.02


Version 2.02

Chapter 4. Storage Control

4.1 Storage Addressing . . . . . . . . . . . . 254.2 Storage Model . . . . . . . . . . . . . . . . 264.2.1 Storage Exceptions . . . . . . . . . . . 264.2.2 Instruction Fetch . . . . . . . . . . . . . 274.2.2.1 Implicit Branch . . . . . . . . . . . . . 274.2.2.2 Address Wrapping Combined with

Changing MSR Bit SF. . . . . . . . . . . . . . 274.2.3 Data Access. . . . . . . . . . . . . . . . . 274.2.4 Performing Operations

Out-of-Order . . . . . . . . . . . . . . . . . . . . . 274.2.4.1 Guarded Storage . . . . . . . . . . . 284.2.4.2 Out-of-Order Accesses to Guarded

Storage . . . . . . . . . . . . . . . . . . . . . . . . . 284.2.5 32-Bit Mode . . . . . . . . . . . . . . . . . 294.2.6 Real Addressing Mode . . . . . . . . 294.2.6.1 Hypervisor Offset Real Mode

Address. . . . . . . . . . . . . . . . . . . . . . . . . 294.2.6.2 Offset Real Mode Address . . . . 304.2.6.3 Storage Control Attributes for Real

Addressing Mode and for Implicit Storage Accesses. . . . . . . . . . . . . . . . . . . . . . . . 30

4.2.7 Address Ranges Having Defined Uses . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.2.8 Invalid Real Address . . . . . . . . . . 314.3 Address Translation Overview . . . . 324.4 Virtual Address Generation. . . . . . . 334.4.1 Segment Lookaside Buffer (SLB) 334.4.2 SLB Search . . . . . . . . . . . . . . . . . 344.5 Virtual to Real Translation . . . . . . . 354.5.1 Page Table. . . . . . . . . . . . . . . . . . 36

4.5.2 Storage DescriptionRegister 1 . . . . . . . . . . . . . . . . . . . . . . . 37

4.5.3 Page Table Search. . . . . . . . . . . . 384.6 Data Address Compare. . . . . . . . . . 394.7 Data Address Breakpoint . . . . . . . . 404.8 Storage Control Bits . . . . . . . . . . . . 414.8.1 Storage Control Bit Restrictions . . 424.8.2 Altering the Storage Control Bits . 424.9 Reference and Change Recording . 434.10 Storage Protection. . . . . . . . . . . . . 454.10.1 Storage Protection, Address Trans-

lation Enabled . . . . . . . . . . . . . . . . . . . . 454.10.2 Storage Protection, Address Trans-

lation Disabled . . . . . . . . . . . . . . . . . . . . 464.11 Storage Control Instructions . . . . . 474.11.1 Cache Management Instructions 474.11.2 Synchronize Instruction . . . . . . . 474.11.3 Lookaside Buffer

Management . . . . . . . . . . . . . . . . . . . . . 474.11.3.1 SLB Management Instructions 494.11.3.2 TLB Management Instructions

(Optional). . . . . . . . . . . . . . . . . . . . . . . . 534.12 Page Table Update

Synchronization Requirements . . . . . . . 574.12.1 Page Table Updates. . . . . . . . . . 574.12.1.1 Adding a Page Table Entry . . . 584.12.1.2 Modifying a Page Table Entry . 584.12.1.3 Deleting a Page Table Entry . . 59

4.1 Storage AddressingA program references storage using the effectiveaddress computed by the processor when it executes aLoad, Store, Branch, or Cache Management instruc-tion, or when it fetches the next sequential instruction.The effective address is translated to a real addressaccording to procedures described in Section 4.2.6 onpage 29, in Section 4.3 on page 32 and in the followingsections. The real address is what is presented to thestorage subsystem.

For a complete discussion of storage addressing andeffective address calculation, see the section entitled“Storage Addressing” in Book I, PowerPC User Instruc-tion Set Architecture.

Storage Control Overview� Real address space size is 2m bytes, m�62; see

Note 1.

� Real page size is 212 bytes (4 KB).

� Effective address space size is 264 bytes.

Chapter 4. Storage Control 25

Version 2.02

� An effective address is translated to a virtualaddress via the Segment Lookaside Buffer (SLB).

- Virtual address space size is 2n bytes,65�n�80; see Note 2.

- Segment size is 228 bytes (256 MB).- Number of virtual segments is 2n-28; see Note

2.- Virtual page size is 2p bytes, 12�p�28; two

sizes are supported simultaneously, 4 KB(p=12) and a larger size; see Note 3.

� A virtual address is translated to a real address viathe Page Table.

Notes:

1. The value of m is implementation-dependent (sub-ject to the maximum given above). When used toaddress storage, the high-order 62-m bits of the“62-bit” real address must be zeros.

2. The value of n is implementation-dependent (sub-ject to the range given above). In references to80-bit virtual addresses elsewhere in this Book, thehigh-order 80-n bits of the “80-bit” virtual addressare assumed to be zeros.

3. The value of p for the larger virtual page size isimplementation-dependent (subject to the rangegiven above).

4.2 Storage Model The storage model provides the following features.

1. The architecture allows the storage implementa-tions to take advantage of the performance bene-fits of weak ordering of storage accesses betweenprocessors or between processors and I/Odevices.

2. In general, storage accesses appear to be per-formed in program order with respect to the pro-cessor performing them but may be performed indifferent orders with respect to other processorsand mechanisms. Exceptions to this rule arestated in the appropriate sections.

3. The architecture provides instructions that allowthe programmer to ensure a consistent andordered storage state.

4. Storage consistency between processors, andbetween a processor and an I/O device, is con-trolled by software using the “WIM” storage controlbits (see Section 4.8). These bits allow software tocontrol whether a given storage location has any ofthe following attributes.

� Write Through Required (W)� Caching Inhibited (I)� Memory Coherence Required (M)

4.2.1 Storage Exceptions

A storage exception is an exception that causes anInstruction Storage interrupt, an Instruction Segmentinterrupt, a Data Storage interrupt, a Data Segmentinterrupt, or an Alignment interrupt. Attempting to fetchor execute an instruction causes a storage exception ifcertain conditions apply. Such conditions include thefollowing.

� The appropriate relocate bit in the MSR is set to 1and the effective address cannot be translated to areal address.

� The access is not permitted by the storage protec-tion mechanism.

� The access causes a Data Address Comparematch or a Data Address Breakpoint match.

In certain cases a storage exception may result in the“restart” of (re-execution of at least part of) a Load orStore instruction. See the section entitled “InstructionRestart” in Book II, PowerPC Virtual Environment

� dcbf[l] � lwarx� dcbst � stdcx.� eieio � stwcx.� icbi � Synchronize� isync � tlbsync� ldarx


Version 2.02

Architecture, and Section 5.6, “Partially ExecutedInstructions” on page 73 in this Book.

4.2.2 Instruction Fetch

Instructions are fetched under control of MSRIR.

MSRIR=0

The effective address of the instruction is inter-preted as described in Section 4.2.6, “RealAddressing Mode” on page 29.

MSRIR=1

The effective address of the instruction is trans-lated by the Address Translation mechanism. (If itcannot be translated, a storage exception occurs.)

4.2.2.1 Implicit Branch

Explicitly altering certain MSR bits (using mtmsr[d]), orexplicitly altering SLB entries, Page Table entries, orcertain System Registers (including the HRMOR, andpossibly other implementation-dependent registers),may have the side effect of changing the addresses,effective or real, from which the current instructionstream is being fetched. This side effect is called animplicit branch. For example, an mtmsrd instructionthat changes the value of MSRSF may change theeffective addresses from which the current instructionstream is being fetched. The MSR bits and SystemRegisters (excluding implementation-dependent regis-ters) for which alteration can cause an implicit branchare indicated as such in Chapter 7. “SynchronizationRequirements for Context Alterations” on page 85.Implicit branches are not supported by the PowerPCArchitecture. If an implicit branch occurs, the resultsare boundedly undefined.

4.2.2.2 Address Wrapping Combined with Changing MSR Bit SF

If the current instruction is at effective address 232 - 4and is an mtmsrd instruction that changes the contentsof MSRSF, the effective address of the next sequentialinstruction is undefined.

4.2.3 Data Access

Data accesses are controlled by MSRDR.

MSRDR=0

The effective address of the data is interpreted asdescribed in Section 4.2.6, “Real AddressingMode”.

MSRDR=1

The effective address of the data is translated bythe Address Translation mechanism. (If it cannotbe translated, a storage exception occurs.)

4.2.4 Performing Operations Out-of-Order

An operation is said to be performed “in-order” if, at thetime that it is performed, it is known to be required bythe sequential execution model. An operation is said tobe performed “out-of-order” if, at the time that it is per-formed, it is not known to be required by the sequentialexecution model.

Operations are performed out-of-order by the proces-sor on the expectation that the results will be needed byan instruction that will be required by the sequentialexecution model. Whether the results are reallyneeded is contingent on everything that might divert thecontrol flow away from the instruction, such as Branch,Trap, System Call, rfid, and hrfid instructions, andinterrupts, and on everything that might change thecontext in which the instruction is executed.

Typically, the processor performs operations out-of-order when it has resources that would otherwise beidle, so the operation incurs little or no cost. If subse-quent events such as branches or interrupts indicatethat the operation would not have been performed inthe sequential execution model, the processor aban-dons any results of the operation (except as describedbelow).

In the remainder of this section, including its subsec-tions, “Load instruction” includes the Cache Manage-ment and other instructions that are stated in theinstruction descriptions to be “treated as a Load”, andsimilarly for “Store instruction”.

A data access that is performed out-of-order may corre-spond to an arbitrary Load or Store instruction (e.g., aLoad or Store instruction that is not in the instructionstream being executed). Similarly, an instruction fetchthat is performed out-of-order may be for an arbitraryinstruction (e.g., the aligned word at an arbitrary loca-tion in instruction storage).

In the case described in the preceding paragraph, ifan interrupt occurs before the next sequentialinstruction is executed, the contents of SRR0 orHSRR0, as appropriate to the interrupt, are unde-fined.

Programming Note


Version 2.02

Most operations can be performed out-of-order, as longas the machine appears to follow the sequential execu-tion model. Certain out-of-order operations arerestricted, as follows.

� Stores

Stores are not performed out-of-order (even if theStore instructions that caused them were executedout-of-order). Moreover, address translationsassociated with instructions preceding the corre-sponding Store instruction are not performed againafter the store has been performed.

� Accessing Guarded Storage

The restrictions for this case are given in Section4.2.4.2.

The only permitted side effects of performing an opera-tion out-of-order are the following.

� A Machine Check or Checkstop that could becaused by in-order execution may occur out-of-order, except as described in Section 8.2 if theoptional Real Mode Storage Control facility isimplemented.

� Reference and Change bits may be set asdescribed in Section 4.9, “Reference and ChangeRecording” on page 43.

� Non-Guarded storage locations that could befetched into a cache by in-order fetching or execu-tion of an arbitrary instruction may be fetched out-of-order into that cache.

4.2.4.1 Guarded Storage

Storage is said to be “well-behaved” if the correspond-ing real storage exists and is not defective, and if theeffects of a single access to it are indistinguishablefrom the effects of multiple identical accesses to it.Data and instructions can be fetched out-of-order fromwell-behaved storage without causing undesired sideeffects.

Storage is said to be Guarded if either of the followingconditions is satisfied.

� MSR bit IR or DR is 1 for instruction fetches ordata accesses respectively, and the G bit is 1 inthe relevant Page Table Entry.

� MSR bit IR or DR is 0 for instruction fetches ordata accesses respectively, MSRHV=1, and theoptional Real Mode Storage Control facility (seeSection 8.2) is not implemented. In this case all ofstorage is Guarded for the correspondingaccesses.

In general, storage that is not well-behaved should beGuarded. Because such storage may represent a con-trol register on an I/O device or may include locationsthat do not exist, an out-of-order access to such stor-age may cause an I/O device to perform unintendedoperations or may result in a Machine Check.

The following rules apply to in-order execution of Loadand Store instructions for which the first byte of thestorage operand is in storage that is both CachingInhibited and Guarded.

� Load or Store instruction that causes an atomicaccess

If any portion of the storage operand has beenaccessed and an External, Decrementer, Hypervi-sor Decrementer, or Imprecise mode Floating-Point Enabled exception is pending, the instructioncompletes before the interrupt occurs.

� Load or Store instruction that causes an Alignmentexception, or that causes a Data Storage excep-tion for reasons other than Data Address Comparematch or Data Address Breakpoint match

The portion of the storage operand that is in Cach-ing Inhibited and Guarded storage is not accessed.

(The corresponding rules for instructions thatcause a Data Address Compare match or DataAddress Breakpoint match are given in Sections4.6 and 4.7 respectively.)

4.2.4.2 Out-of-Order Accesses to Guarded Storage

In general, Guarded storage is not accessed out-of-order. The only exceptions to this rule are the following.

Load Instruction

If a copy of any byte of the storage operand is in acache then that byte may be accessed in the cache orin main storage.

Instruction Fetch

If MSRIR=0 then an instruction may be fetched if any ofthe following conditions are met.

The fact that address translations associatedwith preceding instructions are not performedagain after the store has been performed per-mits Page Table Entries to be updated withouta preceding context synchronizing operation;Section 4.12, “Page Table Update Synchroni-zation Requirements” on page 57. (Theseaddress translations must have been per-formed before the store was determined to berequired by the sequential execution model,because they might have caused an excep-tion.)

Programming Note


Version 2.02

1. The instruction is in a cache. In this case it may befetched from the cache or from main storage.

2. The instruction is in a real page from which aninstruction has previously been fetched, exceptthat if that previous fetch was based on condition 1then the previously fetched instruction must havebeen in the instruction cache.

3. The instruction is in the same real page as aninstruction that is required by the sequential execu-tion model, or is in the real page immediately fol-lowing such a page.

4.2.5 32-Bit Mode

The computation of the 64-bit effective address is inde-pendent of whether the processor is in 32-bit mode or64-bit mode. In 32-bit mode (MSRSF=0), the high-order32 bits of the 64-bit effective address are treated aszeros for the purpose of addressing storage. Thisapplies to both data accesses and instruction fetches.It applies independent of whether address translation isenabled or disabled. This truncation of the effectiveaddress is the only respect in which storage accessesin 32-bit mode differ from those in 64-bit mode.

4.2.6 Real Addressing Mode

A storage access is said to be performed in “realaddressing mode” if the access is an instruction fetchand instruction address translation is disabled, or if theaccess is a data access and data address translation isdisabled. Storage accesses in real addressing modeare performed in a manner that depends on the con-tents of MSRHV, LPES, HRMOR, RMLR, and RMOR(see Section 1.7, “Logical Partitioning (LPAR)” onpage 5), and bit 0 of the effective address (EA0) asdescribed below. Bit 1 of the effective address isignored.

MSRHV=1

� If EA0=0, the Hypervisor Offset Real ModeAddress mechanism, described in Section 4.2.6.1,controls the access.

� If EA0=1, bits 2:63 of the effective address areused as the real address for the access.

MSRHV=0

� If LPES1=0, the access causes a storage excep-tion as described in Section 4.10.2, “Storage Pro-tection, Address Translation Disabled” on page 46.

� If LPES1=1, the Offset Real Mode Address mecha-nism, described in Section 4.2.6.2, controls theaccess.

4.2.6.1 Hypervisor Offset Real Mode Address

If MSRHV = 1 and EA0 = 0, the access is controlled bythe contents of the Hypervisor Real Mode Offset Regis-ter, as follows.

Hypervisor Real Mode Offset Register (HRMOR)

Bits 2:63 of the effective address for the accessare ORed with the 62-bit offset represented by thecontents of the HRMOR, and the 62-bit result isused as the real address for the access. The sup-ported offset values are all values of the form i�2r,where 0 � i < 2j, and j and r are implementation-dependent values having the properties that 12 � r� 26 (i.e., the minimum offset granularity is 4 KBand the maximum offset granularity is 64 MB) andj+r � m � 62, where the real address size sup-ported by the implementation is m bits.

Software should ensure that only well-behavedstorage is copied into a cache, either by accessingas Caching Inhibited (and Guarded) all storage thatmay not be well-behaved, or by accessing suchstorage as not Caching Inhibited (but Guarded) andreferring only to cache blocks that are well-behaved.

If a real page contains instructions that will be exe-cuted when MSRIR=0 and MSRHV=1, softwareshould ensure that this real page and the next realpage contain only well-behaved storage (or, if theoptional Real Mode Storage Control facility isimplemented, that this real page is not Guarded).

Treating the high-order 32 bits of the effectiveaddress as zeros effectively truncates the 64-biteffective address to a 32-bit effective address suchas would have been generated on a 32-bit imple-mentation of the PowerPC Architecture. Thus, forexample, the ESID in 32-bit mode is the high-orderfour bits of this truncated effective address; theESID thus lies in the range 0-15. When addresstranslation is enabled, these four bits would selecta Segment Register on a 32-bit implementation ofthe PowerPC Architecture. The SLB entries thattranslate these 16 ESIDs can be used to emulatethese Segment Registers.

Programming Note

Programming Note


Version 2.02

4.2.6.2 Offset Real Mode Address

If MSRHV=0 and LPES1=1, the access is controlled bythe contents of the Real Mode Limit Register and RealMode Offset Register, as follows.

Real Mode Limit Register (RMLR)

If bits 2:63 of effective address for the access aregreater than or equal to the value (limit) repre-sented by the contents of the RMLR, the accesscauses a storage exception (see Section 4.10.2).In this comparison, if m<62, bits 2:63-m of theeffective address may be ignored (i.e., treated as ifthey were zeros), where the real address size sup-ported by the implementation is m bits. The sup-ported limit values are of the form 2j, where 12 � j� 62. Subject to the preceding sentence, thenumber and values of the limits supported areimplementation-dependent.

Real Mode Offset Register (RMOR)

If the access is permitted by the RMLR, bits 2:63 ofthe effective address for the access are ORed withthe 62-bit offset represented by the contents of theRMOR, and the low-order m bits of the 62-bit resultare used as the real address for the access. Thesupported offset values are all values of the formi�2s, where 0 � i < 2k, and k and s are implementa-tion-dependent values having the properties that2s is the minimum limit value supported by theimplementation (i.e., the minimum value represent-able by the contents of the RMLR) and m � k+s �62.

4.2.6.3 Storage Control Attributes for Real Addressing Mode and for Implicit Storage Accesses

Data accesses and instruction fetches in real address-ing mode when the processor is in hypervisor state areperformed as though all of storage had the followingstorage control attributes, except as modified by theoptional Real Mode Storage Control facility (seeSection 8.2) if that facility is implemented. (The stor-age control attributes are defined in Book II, PowerPCVirtual Environment Architecture.)

� not Write Through Required� not Caching Inhibited, for instruction fetches� not Caching Inhibited, for data accesses if the Real

Mode Caching Inhibited bit is set to 0; CachingInhibited, for data accesses if the Real ModeCaching Inhibited bit is set to 1

� Memory Coherence Required, for data accesses� Guarded

Storage accesses in real addressing mode when theprocessor is not in hypervisor state are performed asthough all of storage had the following storage controlattributes. (Such accesses use the Offset Real ModeAddress mechanism.)

� not Write Through Required� not Caching Inhibited� Memory Coherence Required, for data accesses� not Guarded

Implicit accesses to the Page Table by the processor inperforming address translation and in recording refer-ence and change information are performed as thoughthe storage occupied by the Page Table had the follow-ing storage control attributes.

� not Write Through Required� not Caching Inhibited� Memory Coherence Required� not Guarded

The definition of “performed” given in Book II appliesalso to these implicit accesses; accesses for perform-ing address translation are considered to be loads inthis respect, and accesses for recording reference andchange information are considered to be stores. Theseimplicit accesses are ordered by the ptesync instruc-tion as described in Section 4.11.2 on page 47.

Software must ensure that any data storage locationthat is accessed with the Real Mode Caching Inhibitedbit set to 1 is not in the caches.

Software must ensure that the Real Mode CachingInhibited bit contains 0 whenever data address transla-tion is enabled and whenever the processor is not inhypervisor state.

EA2:63-r should equal 62-r0. If this condition is satis-fied, ORing the effective address with the offsetproduces a result that is equivalent to adding theeffective address and the offset.

If m<62, EA2:63-m and HRMOR0:61-m must bezeros.

Software must ensure that altering the HRMORdoes not cause an implicit branch.

The offset specified by the RMOR should be a non-zero multiple of the limit specified by the RMLR. Ifthese registers are set thus, ORing the effectiveaddress with the offset produces a result that isequivalent to adding the effective address and theoffset. (The offset must not be zero, because realpage 0 contains the fixed interrupt vectors and realpages 1 and 2 may be used for implementation-specific purposes; see Section 4.2.7, “AddressRanges Having Defined Uses” on page 31.)

Programming Note

Programming Note


Version 2.02

4.2.7 Address Ranges Having Defined Uses

The address ranges described below have uses thatare defined by the architecture.

� Fixed interrupt vectors

Except for the first 256 bytes, which are reservedfor software use, the real page beginning at realaddress 0x0000_0000_0000_0000 is either usedfor interrupt vectors or reserved for future interruptvectors.

� Implementation-specific use

The two contiguous real pages beginning at realaddress 0x0000_0000_0000_1000 are reservedfor implementation-specific purposes.

� Offset Real Mode interrupt vectors

The real pages beginning at the real address spec-ified by the HRMOR and RMOR are used similarlyto the page for the fixed interrupt vectors.

� Page Table

A contiguous sequence of real pages beginning atthe real address specified by SDR1 contains thePage Table.

4.2.8 Invalid Real Address

A storage access (including an access that is per-formed out-of-order; see Section 4.2.4) may cause aMachine Check if the accessed storage location con-tains an uncorrectable error or does not exist. In thelatter case the Checkstop state may be entered. SeeSection 5.5.2, “Machine Check Interrupt” on page 66.

Because storage accesses in real addressingmode do not use the SLB or the Page Table,accesses in this mode bypass all checking andrecording of information contained therein (e.g.,storage protection checks that use information con-tained therein are not performed, and referenceand change information is not recorded).

The Real Mode Caching Inhibited bit can be usedto permit a control register on an I/O device to beaccessed without permitting the correspondingstorage location to be copied into the caches. Thebit should normally contain 0. Software would setthe bit to 1 just before accessing the control regis-ter, access the control register as needed, and thenset the bit back to 0.

Programming Note

Hypervisor software must ensure that a storageaccess by a program in one partition will not causea Checkstop or other system-wide event that couldaffect the integrity of other partitions (seeSection 1.7, “Logical Partitioning (LPAR)” onpage 5). For example, such an event could occur ifa real address placed in a Page Table Entry ormade accessible to a partition using the Offset RealMode Address mechanism (see Section 4.2.6.3)does not exist.

Programming Note


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4.3 Address Translation Overview

The effective address (EA) is the address generated bythe processor for an instruction fetch or for a dataaccess. If address translation is enabled, this addressis passed to the Address Translation mechanism,which attempts to convert the address to a real addresswhich is then used to access storage.

The first step in address translation is to convert theeffective address to a virtual address (VA), asdescribed in Section 4.4. The second step, conversionof the virtual address to a real address (RA), isdescribed in Section 4.5.

If the effective address cannot be translated, a storageexception (see Section 4.2.1) occurs.

Figure 19 gives an overview of the address translationprocess.

Figure 19. Address translation overview

Real Address

Lookup inPage Table

Virtual Address

Lookup in SLB

Effective Address


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4.4 Virtual Address Generation

Conversion of a 64-bit effective address to a virtualaddress is done by searching the Segment LookasideBuffer (SLB) as shown in Figure 20.

Figure 20. Translation of 64-bit effective address to80-bit virtual address

4.4.1 Segment Lookaside Buffer (SLB)

The Segment Lookaside Buffer (SLB) specifies themapping between Effective Segment IDs (ESIDs) andVirtual Segment IDs (VSIDs). The number of SLBentries is implementation-dependent, except that allimplementations provide at least 32 entries.

The contents of the SLB are managed by software,using the instructions described in Section 4.11.3.1,“SLB Management Instructions” on page 49. SeeChapter 7. “Synchronization Requirements for ContextAlterations” on page 85 for the rules that software mustfollow when updating the SLB.

SLB Entry

Each SLB entry (SLBE) maps one ESID to one VSID.Figure 21 shows the layout of an SLB entry.

Figure 21. SLB Entry

On implementations that support a virtual address sizeof only n bits, n<80, bits 0:79-n of the VSID field aretreated as reserved bits, and software must set them tozeros.

A No-execute segment (N=1) contains data that shouldnot be executed.

The L bit selects between two virtual page sizes, 4 KB(p=12) and “large”. The large page size is an imple-mentation-dependent value that is a power of 2 and isin the range 8 KB : 256 MB (13�p�28). Some imple-mentations may provide a means by which softwarecan select the large page size from a set of severalimplementation-dependent sizes during system initial-ization.

If “large page” is used in reference to real storage, itmeans the sequence of contiguous real (4 KB) pagesto which a large virtual page is mapped.

The Class field is used in conjunction with the slbieinstruction (see Section 4.11.3.1).

Software must ensure that the SLB contains at mostone entry that translates a given effective address (i.e.,that a given ESID is contained in no more than oneSLB entry).

Virtual Page Number (VPN)

64-bit Effective Address

ESID Page Byte36 28-p p

0 35 36 63-p 64-p 63

SLBE0

SLBEn

ESID V VSID KsKpNLC

0 35 37 88 89 93

Segment Lookaside Buffer (SLB)

VSID Page Byte52 28-p p

� � � � �

80-bit Virtual Address

ESID V VSID KsKpNLC0 36 37 89 93

Bit(s) Name Description0:35 ESID Effective Segment ID36 V Entry valid (V=1) or invalid (V=0)

37:88 VSID Virtual Segment ID89 Ks Supervisor (privileged) state stor-

age key90 Kp Problem state storage key91 N No-execute segment if N=192 L Virtual pages are large (L=1) or

4 KB (L=0)93 C Class


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4.4.2 SLB Search

When the hardware searches the SLB, all entries aretested for a match with the EA. For a match to exist,the following conditions must be satisfied.

� SLBEV = 1� SLBEESID = EA0:35

If the SLB search succeeds, the virtual address (VA) isformed by concatenating the VSID from the matchingSLB entry with bits 36:63 of the EA.

The Virtual Page Number (VPN) is bits 0:79-p of the vir-tual address.

If the SLB search fails, a segment fault occurs. This isan Instruction Segment exception or a Data Segmentexception, depending on whether the effective addressis for an instruction fetch or for a data access.


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4.5 Virtual to Real Translation

Conversion of an 80-bit virtual address to a realaddress is done by searching the Page Table as shownin Figure 22.

Figure 22. Translation of 80-bit virtual address to 62-bit real address

Virtual Page Number (VPN) Byte

0 13 51 52 79-p 80-p 79

80-bit Virtual Address

// xxx.......xx000.00 ///

0 2 1718 45 59 63

80-p p

44 13 5 28-p11+p

0 38

0 2728 38

Decode to Mask

0 27

3928

28

28

000000028 71116

PTE0 PTE7PTEG 0

PTEG n

62-bit Real Address of Page Table Entry Group (PTEG)

AVPN Real Page Number (RPN)HSW V // RAC C WIMG NL

0 56 6162 63 0 1 2 63-p52 54 55 56 57 60 61 63

p

ByteRPN

62-p

57 50

62-bit Real Address

2

0s

Page Table 16 bytes

128 bytes

Page Table Entry (PTE) 16 bytes

/ / PP

HTABORG HTABSIZE

Hash Function

AND

OR


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4.5.1 Page Table

The Hashed Page Table (HTAB) is a variable-sizeddata structure that specifies the mapping between Vir-tual Page Numbers and Real Page Numbers. TheHTAB’s size must be a multiple of 4 KB, its startingaddress must be a multiple of its size, and it must belocated in storage having the storage control attributesthat are used for implicit accesses to it (seeSection 4.2.6.3).

The HTAB contains Page Table Entry Groups (PTEGs).A PTEG contains 8 Page Table Entries (PTEs) of 16bytes each; each PTEG is thus 128 bytes long. PTEGsare entry points for searches of the Page Table.

See see Section 4.12, “Page Table Update Synchroni-zation Requirements” on page 57 for the rules that soft-ware must follow when updating the Page Table.

Page Table Entry

Each Page Table Entry (PTE) maps one VPN to oneRPN. Figure 23 shows the layout of a PTE.


Figure 23. Page Table Entry

If p�23, the Abbreviated Virtual Page Number (AVPN)field contains bits 0:56 of the VPN. Otherwise bits0:79-p of the AVPN field contain bits 0:79-p of the VPN,and bits 80-p:56 of the AVPN field must be zeros.

On implementations that support a virtual address sizeof only n bits, n<80, bits 0:79-n of the AVPN field mustbe zeros.

The RPN field contains the page number of the realpage that contains the first byte of the block of real stor-age to which the virtual page is mapped. If p>12, thelow-order p-12 bits of the RPN field (bits 64-p:51 ofdoubleword 1 of the PTE) must be 0. On implementa-tions that support a real address size of only m bits,m<62, bits 0:61-m of the RPN field must be zeros.

The Page Table must be treated as a hypervisorresource (see Section 1.7, “Logical Partitioning(LPAR)” on page 5), and therefore must be placedin real storage to which only the hypervisor haswrite access. Moreover, the contents of the PageTable must be such that non-hypervisor softwarecannot modify storage that contains hypervisor pro-grams or data.

Programming Note

0 57 61 62 63

AVPN SW L H V / / RPN // AC R C WIMG N PP

0 1 2 52 54 55 56 57 61 62 63

Dword Bit(s) Name Description0 0:56 AVPN Abbreviated Virtual Page

Number57:60 SW Available for software use61 L Virtual page is large (L=1)

or 4 KB (L=0)62 H Hash function identifier63 V Entry valid (V=1)or invalid

(V=0) 1 2:51 RPN Real Page Number 54 AC Address Compare bit 55 R Reference bit 56 C Change bit 57:60 WIMG Storage control bits 61 N No-execute page if N=1 62:63 PP Page protection bits

If p�23, the AVPN field omits the low-order 23-pbits of the VPN. These bits are not needed in thePTE, because the low-order 11 bits of the VPN arealways used in selecting the PTEGs to be searched(see Section 4.5.3).

Programming Note


Version 2.02

A No-execute page (N=1) contains data that should notbe executed.

Page Table Size

The number of entries in the Page Table directly affectsperformance because it influences the hit ratio in thePage Table and thus the rate of page faults. If the tableis too small, it is possible that not all the virtual pagesthat actually have real pages assigned can be mappedvia the Page Table. This can happen if too many hashcollisions occur and there are more than 16 entries forthe same primary/secondary pair of PTEGs. While thissituation cannot be guaranteed not to occur for any sizePage Table, making the Page Table larger than theminimum size (see Section 4.5.2) will reduce the fre-quency of occurrence of such collisions.

4.5.2 Storage DescriptionRegister 1

The SDR1 register is shown in Figure 24.


Figure 24. SDR1

SDR1 is a hypervisor resource; see Section 1.7, “Logi-cal Partitioning (LPAR)” on page 5.

The HTABORG field in SDR1 contains the high-order44 bits of the 62-bit real address of the Page Table.The Page Table is thus constrained to lie on a 218 byte(256 KB) boundary at a minimum. At least 11 bits fromthe hash function (see Figure 22) are used to indexinto the Page Table. The minimum size Page Table is256 KB (211 PTEGs of 128 bytes each).

The Page Table can be any size 2n bytes where18�n�46. As the table size is increased, more bits areused from the hash to index into the table and the valuein HTABORG must have more of its low-order bitsequal to 0.

The HTABSIZE field in SDR1 contains an integer givingthe number of bits (in addition to the minimum of 11bits) from the hash that are used in the Page Tableindex. This number must not exceed 28. HTABSIZE isused to generate a mask of the form 0b00...011...1,which is a string of 28 - HTABSIZE 0-bits followed by astring of HTABSIZE 1-bits. The 1-bits determine whichadditional bits (beyond the minimum of 11) from thehash are used in the index (see Figure 22). The num-ber of low-order 0 bits in HTABORG must be greaterthan or equal to the value in HTABSIZE.

On implementations that support a real address size ofonly m bits, m<62, bits 0:61-m of the HTABORG fieldare treated as reserved bits, and software must setthem to zeros.

For a large virtual page, the high-order 62-p bits ofthe RPN field (bits 0:61-p) comprise the large realpage number.

If large pages are not used, it is recommended thatthe number of PTEGs in the Page Table be at leasthalf the number of real pages to be accessed. Forexample, if the amount of real storage to beaccessed is 231 bytes (2 GB), then we have231-12=219 real pages. The minimum recom-mended Page Table size would be 218 PTEGs, or225 bytes (32 MB).

Programming Note

Programming Note

// HTABORG /// HTABSIZE0 2 46 59 63

Bits Name Description2:45 HTABORG Real address of Page Table59:63 HTABSIZE Encoded size of Page Table


Version 2.02

Example:

Suppose that the Page Table is 16,384 (214) 128-bytePTEGs, for a total size of 221 bytes (2 MB). A 14-bitindex is required. Eleven bits are provided from thehash to start with, so 3 additional bits from the hashmust be selected. Thus the value in HTABSIZE mustbe 3 and the value in HTABORG must have its low-order 3 bits (bits 43:45 of SDR1) equal to 0. Thismeans that the Page Table must begin on a 23+11+7 =221 = 2 MB boundary.

4.5.3 Page Table Search

When the hardware searches the Page Table, theaccesses are performed as described inSection 4.2.6.3, “Storage Control Attributes for RealAddressing Mode and for Implicit Storage Accesses” onpage 30.

An outline of the HTAB search process is shown inFigure 22. The detailed algorithm is as follows.

1. Primary Hash:A 39-bit hash value is computed by ExclusiveORing bits 13:51 of the VPN with a 39-bit valueformed by concatenating 11+p 0-bits with the low-order 28-p bits of the VPN. The 62-bit real addressof a PTEG is formed by concatenating the follow-ing values:

� Bits 2:17 of SDR1 (the high-order 16 bits ofHTABORG).

� Bits 0:27 of the 39-bit hash value ANDed withthe mask generated from bits 59:63 of SDR1(HTABSIZE) and then ORed with bits 18:45 ofSDR1 (the low-order 28 bits of HTABORG).

� Bits 28:38 of the 39-bit hash value.� Seven 0-bits.

This operation identifies a particular PTEG, calledthe “primary PTEG”, whose eight PTEs will betested.

2. Secondary Hash:A 39-bit hash value is computed by taking theone’s complement of the Exclusive OR of bits

13:51 of the VPN with a 39-bit value formed byconcatenating 11+p 0-bits with the low-order 28-pbits of the VPN. The 62-bit real address of aPTEG is formed by concatenating the followingvalues:

� Bits 2:17 of SDR1 (the high-order 16 bits ofHTABORG).

� Bits 0:27 of the 39-bit hash value ANDed withthe mask generated from bits 59:63 of SDR1(HTABSIZE) and then ORed with bits 18:45 ofSDR1 (the low-order 28 bits of HTABORG).

� Bits 28:38 of the 39-bit hash value.� Seven 0-bits.

This operation identifies the “secondary PTEG”.

3. As many as 16 PTEs in the two identified PTEGsare tested to determine if any translate the givenvirtual address. Let q = minimum(5, 28-p). For amatch to exist, the following conditions must besatisfied.

� PTEH=0 for the primary PTEG, 1 for the sec-ondary PTEG

� PTEV=1� PTEAVPN[0:51]=VA0:51� if p<28, PTEAVPN[52:51+q]=VA52:51+q� if EA is an SLS address

then PTEL = 0else PTEL = SLBEL

If one or more matches are found, the search issuccessful; otherwise it fails. If more than onematch is found, the matching entries must be iden-tical in all defined fields with the exception of SW,H, AC, R, and C. If they are, one of the matchingentries is used, for the translation, Data AddressCompare, and the setting of the R and C bits. Ifthey are not, the translation and Data AddressCompare are undefined, as is the setting of the Rand C bits in the matching entries, and the remain-der of this section does not apply.

If the Page Table search succeeds, the real address(RA) is formed by concatenating bits 0:61-p of the RPNfrom the matching PTE with bits 64-p:63 of the effectiveaddress (the byte offset).

RA=RPN0:61-p || EA64-p:63

The N (No-execute) value used for the storage accessis the result of ORing the N bit from the matching PTEwith the N bit from the SLB entry that was used totranslate the effective address.

If the Page Table search fails, a page fault occurs. Thisis an Instruction Storage exception or a Data Storageexception, depending on whether the effective addressis for an instruction fetch or for a data access.

Let n equal the virtual address size (in bits) sup-ported by the implementation. If n<67, softwareshould set the HTABSIZE field to a value that doesnot exceed n-39. Because the high-order 80-n bitsof the VSID are assumed to be zeros, the hashvalue used in the Page Table search will have thehigh-order 67-n bits either all 0s (primary hash; seeSection 4.5.3) or all 1s (secondary hash). If HTAB-SIZE > n-39, some of these hash value bits will beused to index into the Page Table, with the resultthat certain PTEGs will not be searched.

Programming Note


Version 2.02

Translation Lookaside Buffer

Conceptually, the Page Table is searched by theaddress relocation hardware to translate every refer-ence. For performance reasons, the hardware usuallykeeps a Translation Lookaside Buffer (TLB) that holdsPTEs that have recently been used. The TLB issearched prior to searching the Page Table. As a con-sequence, when software makes changes to the PageTable it must perform the appropriate TLB invalidateoperations to maintain the consistency of the TLB withthe Page Table (see Section 4.12).

4.6 Data Address CompareThe Data Address Compare mechanism provides ameans of detecting load and store accesses to a virtualpage.

The Data Address Compare mechanism is controlledby the Address Compare Control Register (ACCR), andby a bit in each Page Table Entry (PTEAC).


Figure 25. Address Compare Control Register

A Data Address Compare match occurs for a Load orStore instruction if for any byte accessed, the followingconditions are satisfied.

� PTEAC=1 for the PTE that translates the virtualaddress, and

� the instruction is a Store and ACCRDW=1, or theinstruction is a Load and ACCRDR=1.

If the match conditions are satisfied, a match alsooccurs for dcbz, eciwx, and ecowx. For the purposeof determining whether a match occurs, eciwx istreated as a Load, and dcbz and ecowx are treated asStores.

If the match conditions are satisfied, it is undefinedwhether a match occurs in the following cases.

� The instruction is Store Conditional but the store isnot performed.

� The instruction is a Load/Store String of zerolength.

The Cache Management instructions other than dcbznever cause a match.

A Data Address Compare match causes a Data Stor-age exception (see Section 5.5.3, “Data Storage Inter-rupt” on page 66). If a match occurs, some or all of thebytes of the storage operand may have beenaccessed; however, if a Store, dcbz, or ecowx instruc-tion causes the match, the bytes of the storage oper-and that are in a virtual page for which PTEAC=1 arenot modified.

To obtain the best performance, Page Table Entriesshould be allocated beginning with the first emptyentry in the primary PTEG, or with the first emptyentry in the secondary PTEG if the primary PTEG isfull.

1. Page Table entries may or may not be cachedin a TLB.

2. It is possible that the hardware implementsmore than one TLB, such as one for data andone for instructions. In this case the size andshape of the TLBs may differ, as may the val-ues contained therein.

3. Use the tlbie or tlbia instruction to ensure thatthe TLB no longer contains a mapping for aparticular virtual page.

Programming Note

Programming Notes

/// DW DR0 62 63

Bit Name Description62 DW Data Write63 DR Data Read


Version 2.02

4.7 Data Address BreakpointThe Data Address Breakpoint mechanism provides ameans of detecting load and store accesses to a desig-nated doubleword. The address comparison is doneon an effective address (EA).

The Data Address Breakpoint mechanism is controlledby the Data Address Breakpoint Register (DABR),shown in Figure 26, and the Data Address BreakpointRegister Extension (DABRX), shown in Figure 27.

Figure 26. Data Address Breakpoint Register


Figure 27. Data Address Breakpoint RegisterExtension

The DABR and DABRX are hypervisor resources; seeSection 1.7, “Logical Partitioning (LPAR)” on page 5.

The supported PRIVM values are 0b000, 0b001,0b010, 0b011, 0b100, and 0b111. If the PRIVM fielddoes not contain one of the supported values, thenwhether a match occurs for a given storage access isundefined. Elsewhere in this section it is assumed thatthe PRIVM field contains one of the supported values.

A Data Address Breakpoint match occurs for a Load orStore instruction if, for any byte accessed, all of the fol-lowing conditions are satisfied.

� EA0:60 = DABRDAB� (MSRDR = DABRBT) | DABRXBTI� if the processor is in

- hypervisor state and DABRXHYP = 1 or- privileged but non-hypervisor state and

DABRXPNH = 1 or- problem state and DABRXPR = 1

� the instruction is a Store and DABRDW = 1, or theinstruction is a Load and DABRDR = 1.

In 32-bit mode the high-order 32 bits of the EA aretreated as zeros for the purpose of detecting a match.

If the above conditions are satisfied, a match alsooccurs for eciwx and ecowx. For the purpose of deter-mining whether a match occurs, eciwx is treated as aLoad, and ecowx is treated as a Store.

If the above conditions are satisfied, it is undefinedwhether a match occurs in the following cases.

� The instruction is Store Conditional but the store isnot performed.

� The instruction is a Load/Store String of zerolength.

� The instruction is dcbz. (For the purpose of deter-mining whether a match occurs, dcbz is treated asa Store.)

The Cache Management instructions other than dcbznever cause a match.

A Data Address Breakpoint match causes a Data Stor-age exception (see Section 5.5.3, “Data Storage Inter-rupt” on page 66). If a match occurs, some or all of thebytes of the storage operand may have beenaccessed; however, if a Store or ecowx instructioncauses the match, the storage operand is not modifiedif the instruction is one of the following:

� any Store instruction that causes an atomic access� ecowx

The Data Address Compare mechanism does notapply to instruction fetches, or to data accesses inreal addressing mode (MSRDR=0).

DAB BT DW DR0 61 62 63

Bit(s) Name Description0:60 DAB Data Address Breakpoint61 BT Breakpoint Translation62 DW Data Write63 DR Data Read

/// BT PRIVM0 60 61 63

Bit(s) Name Description60 BTI Breakpoint Translation Ignore61:63 PRIVM Privilege Mask61 HYP Hypervisor state62 PNH Privileged but Non-Hypervisor state63 PRO Problem state

Programming Note

PRIVM value 0b000 causes matches not to occurregardless of the contents of other DABR andDABRX fields. PRIVM values 0b101 and 0b110 arenot supported because a storage location that isshared between the hypervisor and non-hypervisorsoftware is unlikely to be accessed using the sameEA by both the hypervisor and the non-hypervisorsoftware. (PRIVM value 0b111 is supported prima-rily for reasons of software compatibility, asdescribed in a subsequent Programming Note.)

Programming Note


Version 2.02

4.8 Storage Control BitsWhen address translation is enabled, each storageaccess is performed under the control of the PageTable Entry used to translate the effective address.Each Page Table Entry contains storage control bitsthat specify the presence or absence of the corre-sponding storage control attribute (see the section enti-tled “Storage Control Attributes” in Book II, PowerPCVirtual Environment Architecture) for all accessestranslated by the entry, as shown in Figure 28. The bitsare called W, I, M, and G.

Figure 28. Storage control bits

When address translation is enabled, instructions arenot fetched from storage for which the G bit in the PageTable Entry is set to 1 (see Section 4.10, “Storage Pro-tection” on page 45)

When address translation is disabled, the storage con-trol attributes are implicit; see Section 4.2.6.3, “StorageControl Attributes for Real Addressing Mode and forImplicit Storage Accesses” on page 30.

In Section 4.8.1 and 4.8.2, "access" includes accessesthat are performed out-of-order, and references to W, I,M, and G bits include the values of those bits that areimplied when address translation is disabled.

The Data Address Breakpoint mechanism does notapply to instruction fetches.

Before setting a breakpoint requested by the oper-ating system, the hypervisor must verify that therequested contents of the DABR and DABRX can-not cause the hypervisor to receive a Data Storageinterrupt that it is not prepared to handle, or that itintrinsically cannot handle (e.g., the EA is in therange of EAs at which the hypervisor's Data Stor-age interrupt handler saves registers, DABRBT ||DABRXBTI � 0b10, DABRDW = 1, and DABRXHYP =1).

Processors that comply with versions of the archi-tecture that precede Version 2.02 do not providethe DABRX. Forward compatibility for softwarethat was written for such processors (and uses theData Address Breakpoint facility) can be obtainedby setting DABRX60:63 to 0b0111.

Programming Note

Programming Note

Programming Note

Bit Storage Control Attribute

W1 0 - not Write Through Required1 - Write Through Required

I 0 - not Caching Inhibited1 - Caching Inhibited

M2 0 - not Memory Coherence Required1 - Memory Coherence Required

G 0 - not Guarded1 - Guarded

1. Support for the 1 value of the W bit is optional. Implementations that do not support the 1 value treat the bit as reserved and assume its value to be 0.

2. Support for the 0 value of the M bit is optional. Implementations that do not support the 0 value assume the value of the bit to be 1, and may either preserve the value of the bit or write it as 1.

In a uniprocessor system in which only the proces-sor has caches, correct coherent execution doesnot require the processor to access storage asMemory Coherence Required, and accessing stor-age as not Memory Coherence Required may givebetter performance.

Programming Note


Version 2.02

4.8.1 Storage Control Bit Restric-tions

All combinations of W, I, M, and G values are sup-ported except those for which both W and I are 1.

At any given time, the value of the I bit must be thesame for all accesses to a given real page.

At any given time, the value of the W bit must be thesame for all accesses to a given real page.

4.8.2 Altering the Storage Control Bits

When changing the value of the I bit for a given realpage from 0 to 1, software must set the I bit to 1 andthen flush all copies of locations in the page from thecaches using dcbf[l] and icbi before permitting anyother accesses to the page.

When changing the value of the W bit for a given realpage from 0 to 1, software must ensure that no proces-sor modifies any location in the page until after all cop-ies of locations in the page that are considered to bemodified in the data caches have been copied to mainstorage using dcbst or dcbf[l].

When changing the value of the M bit for a given realpage, software must ensure that all data caches areconsistent with main storage. The actions required todo this to are system-dependent.

Additional requirements for changing the storage con-trol bits in the Page Table are given in see Section 4.12,“Page Table Update Synchronization Requirements” onpage 57.

If an application program requests both the WriteThrough Required and the Caching Inhibitedattributes for a given storage location, the operatingsystem should set the I bit to 1 and the W bit to 0.

Programming Note

It is recommended that dcbf be used, rather thandcbfl, when changing the value of the I or W bitfrom 0 to 1. (dcbfl would have to be executed onall processors for which the contents of the datacache may be inconsistent with the new value ofthe bit, whereas, if the M bit for the page is 1, dcbfneed be executed on only one processor in thesystem.)

For example, when changing the M bit in somedirectory-based systems, software may be requiredto execute dcbf[l] instructions on each processor toflush all storage locations accessed with the old Mvalue before permitting the locations to beaccessed with the new M value.

Programming Note

Programming Note


Version 2.02

4.9 Reference and Change RecordingIf address translation is enabled, Reference (R) andChange (C) bits are maintained in the Page Table Entrythat is used to translate the virtual address. If the stor-age operand of a Load or Store instruction crosses avirtual page boundary, the accesses to the componentsof the operand in each page are treated as separateand independent accesses to each of the pages for thepurpose of setting the Reference and Change bits.

Reference and Change bits are set by the processor asdescribed below. Setting the bits need not be atomicwith respect to performing the access that caused thebits to be updated. An attempt to access storage maycause one or more of the bits to be set (as describedbelow) even if the access is not performed. The bitsare updated in the Page Table Entry if the new valuewould otherwise be different from the old, as deter-mined by examining either the Page Table Entry or anycorresponding lookaside information maintained by theprocessor (e.g., in a TLB).

Reference Bit

The Reference bit is set to 1 if the correspondingaccess (load, store, or instruction fetch) is requiredby the sequential execution model and is per-formed. Otherwise the Reference bit may be set to1 if the corresponding access is attempted, eitherin-order or out-of-order, even if the attempt causesan exception.

Change Bit

The Change bit is set to 1 if a Store instruction isexecuted and the store is performed. Otherwisethe Change bit may be set to 1 if a Store instruc-tion is executed and the store is permitted by thestorage protection mechanism and, if the Storeinstruction is executed out-of-order, the instructionwould be required by the sequential executionmodel in the absence of the following kinds ofinterrupts:

� system-caused interrupts (see Section 5.3)� Floating-Point Enabled Exception type Pro-

gram interrupts when the processor is in anImprecise mode

Figure 29 on page 44 summarizes the rules for settingthe Reference and Change bits. The table applies toeach atomic storage reference. It should be read fromthe top down; the first line matching a given situationapplies. For example, if stwcx. fails due to both a stor-age protection violation and the lack of a reservation,the Change bit is not altered.

In the figure, the “Load-type” instructions are the Loadinstructions described in Books I and II, eciwx, and theCache Management instructions that are treated asLoads. The “Store-type” instructions are the Storeinstructions described in Books I and II, ecowx, and theCache Management instructions that are treated asStores. The “ordinary” Load and Store instructions arethose described in Books I and II. “set” means “set to1”.

When the processor updates the Reference andChange bits in the Page Table Entry, the accesses areperformed as described in Section 4.2.6.3, “StorageControl Attributes for Real Addressing Mode and forImplicit Storage Accesses” on page 30. The accesses

Even though the execution of a Store instructioncauses the Change bit to be set to 1, the storemight not be performed or might be only partiallyperformed in cases such as the following.

� A Store Conditional instruction (stwcx. orstdcx.) is executed, but no store is performed.

� A Store String Word Indexed instruction(stswx) is executed, but the length is zero.

� The Store instruction causes a Data Storageexception (for which setting the Change bit isnot prohibited).

� The Store instruction causes an Alignmentexception.

� The Page Table Entry that translates the virtualaddress of the storage operand is altered suchthat the new contents of the Page Table Entrypreclude performing the store (e.g., the PTE ismade invalid, or the PP bits are changed).

For example, when executing a Store instruc-tion, the processor may search the Page Tablefor the purpose of setting the Change bit andthen reexecute the instruction. When reexecut-ing the instruction, the processor may searchthe Page Table a second time. If the PageTable Entry has meanwhile been altered, by aprogram executing on another processor, thesecond search may obtain the new contents,which may preclude the store.

� A system-caused interrupt occurs before thestore has been performed.

Programming Note


Version 2.02

may be performed using operations equivalent to astore to a byte, halfword, word, or doubleword, and arenot necessarily performed as an atomic read/modify/write of the affected bytes.

These Reference and Change bit updates are not nec-essarily immediately visible to software. Executing async instruction ensures that all Reference andChange bit updates associated with address transla-tions that were performed, by the processor executingthe sync instruction, before the sync instruction is exe-cuted will be performed with respect to that processorbefore the sync instruction’s memory barrier is created.There are additional requirements for synchronizingReference and Change bit updates in multiprocessorsystems; see Section 4.12, “Page Table Update Syn-chronization Requirements” on page 57.

If software refers to a Page Table Entry whenMSRDR=1, the Reference and Change bits in the asso-ciated Page Table Entry are set as for ordinary loadsand stores. See Section 4.12 for the rules softwaremust follow when updating Reference and Change bits.

Figure 29. Setting the Reference and Change bits

Because the sync instruction is execution synchro-nizing, the set of Reference and Change bitupdates that are performed with respect to the pro-cessor executing the sync instruction before thememory barrier is created includes all Referenceand Change bit updates associated with instruc-tions preceding the sync instruction.

Programming Note

Status of Access R CStorage protection violation Acc1 NoOut-of-order I-fetch or Load-type insn Acc NoOut-of-order Store-type insn Would be required by the sequential execution model in the absence of system-caused or imprecise interrupts3 Acc Acc1 2

All other cases Acc NoIn-order Load-type or Store-type insn, access not performed Load-type insn Acc No Store-type insn Acc Acc2

Other in-order access I-fetch Yes No Ordinary Load, eciwx Yes No Other ordinary Store, ecowx, dcbz Yes Yes icbi, dcbt, dcbtst, dcbst, dcbf[l] Acc No

“Acc” means that it is acceptable to set the bit.1 It is preferable not to set the bit.2 If C is set, R is also set unless it is already set.3 For Floating-Point Enabled Exception type Pro-

gram interrupts, “imprecise” refers to the exception mode controlled by MSRFE0 FE1.


Version 2.02

4.10 Storage ProtectionThe storage protection mechanism provides a meansfor selectively granting instruction fetch access, grant-ing read access, granting read/write access, and pro-hibiting access to areas of storage based on a numberof control criteria.

The operation of the protection mechanism depends onwhether address translation is enabled or disabled .

If an instruction fetch is not permitted by the protectionmechanism, an Instruction Storage exception is gener-ated. If a data access is not permitted by the protectionmechanism, a Data Storage exception is generated.(See Section 4.2.1, “Storage Exceptions” on page 26)

When address translation is enabled, a protectiondomain is a range of unmapped effective addresses, avirtual page, or a segment. When address translationis disabled and LPES1=1 there are two protectiondomains: the set of effective addresses that are lessthan the value specified by the RMLR, and all othereffective addresses. When address translation is dis-abled and LPES1=0 the entire effective address spacecomprises a single protection domain. A protectionboundary is a boundary between protection domains.

4.10.1 Storage Protection, Address Translation Enabled

When address translation is enabled , the protectionmechanism is controlled by the following.

� MSRPR, which distinguishes between supervisor(privileged) state and problem state

� Ks and Kp, the supervisor (privileged) state andproblem state storage key bits in the SLB entryused to translate the effective address

� PP, page protection bits in the Page Table Entryused to translate the effective address

� For instruction fetches only:- the N (No-execute) value used for the access

(see Section 4.5.3)- PTEG, the G (Guarded) bit in the Page Table

Entry used to translate the effective address

Using the above values, the following rules are applied.

1. For an instruction fetch, the access is not permit-ted if the N value is 1 or if PTEG=1.

2. For any access except an instruction fetch that isnot permitted by rule 1, a “Key” value is computedusing the following formula:

Key � (Kp & MSRPR) | (Ks & ¬MSRPR)

Using the computed Key, Figure 30 is applied. Aninstruction fetch is permitted for any entry in thefigure except “no access”. A load is permitted forany entry except “no access”. A store is permittedonly for entries with “read/write”.

Figure 30. PP bit protection states, address translation enabled

Key PP Access Authority

0 00 read/write

0 01 read/write

0 10 read/write

0 11 read only

1 00 no access

1 01 read only

1 10 read/write

1 11 read only


Version 2.02

4.10.2 Storage Protection, Address Translation Disabled

When address translation is disabled, the protectionmechanism is controlled by the following (seeSection 1.7, “Logical Partitioning (LPAR)” on page 5and Section 4.2.6, “Real Addressing Mode” onpage 29).

� LPES1, which distinguishes between the twomodes of accessing storage using the LPAR facil-ity

� MSRHV, which distinguishes between hypervisorstate and other privilege states

� RMLR, which specifies the real mode limit value

Using the above values, Figure 31 is applied. Theaccess is permitted for any entry in the figure except“no access”.

Figure 31. Protection states, address translation disabled

LPES1 HV Access Authority0 0 no access0 1 read/write1 0 read/write or no access1

1 1 read/write

1. If the effective address for the access is less than the value specified by the RMLR the access authority is read/write; otherwise the access is not permitted.

The comparison described in note 1 in Figure 31ignores bits 0:1 of the effective address and mayignore bits 2:63-m; see Section 4.2.6.

Programming Note


Version 2.02

4.11 Storage Control Instructions

4.11.1 Cache Management Instructions

This section describes aspects of cache managementthat are relevant only to privileged software program-mers.

For a dcbz instruction that causes the target block tobe newly established in the data cache without beingfetched from main storage, the processor need not ver-ify that the associated real address is valid. The exist-ence of a data cache block that is associated with aninvalid real address (see Section 4.2.8) can cause adelayed Machine Check interrupt or a delayed Check-stop.

Each implementation provides an efficient means bywhich software can ensure that all blocks that are con-sidered to be modified in the data cache have beencopied to main storage before the processor enters anypower conserving mode in which data cache contentsare not maintained. The means are described in theBook IV, PowerPC Implementation Features documentfor the implementation.

4.11.2 Synchronize Instruction

The Synchronize instruction is described in Book II,PowerPC Virtual Environment Architecture, but only atthe level required by an application programmer (syncwith L=0 or L=1). This section describes properties ofthe instruction that are relevant only to operating sys-tem and hypervisor software programmers. This vari-ant of the Synchronize instruction is designated thepage table entry sync and is specified by the extendedmnemonic ptesync (equivalent to sync with L=2).

The ptesync instruction has all of the properties ofsync with L=0 and also the following additional proper-ties.

� The memory barrier created by the ptesyncinstruction provides an ordering function for thestorage accesses associated with all instructionsthat are executed by the processor executing theptesync instruction and, as elements of set A, forall Reference and Change bit updates associatedwith additional address translations that were per-formed, by the processor executing the ptesyncinstruction, before the ptesync instruction is exe-cuted. The applicable pairs are all pairs ai,bj inwhich bj is a data access and ai is not an instruc-tion fetch.

� The ptesync instruction causes all Reference andChange bit updates associated with address trans-

lations that were performed, by the processor exe-cuting the ptesync instruction, before the ptesyncinstruction is executed, to be performed withrespect to that processor before the ptesyncinstruction’s memory barrier is created.

� The ptesync instruction provides an ordering func-tion for all stores to the Page Table caused byStore instructions preceding the ptesync instruc-tion with respect to searches of the Page Tablethat are performed, by the processor executing theptesync instruction, after the ptesync instructioncompletes. Executing a ptesync instructionensures that all such stores will be performed, withrespect to the processor executing the ptesyncinstruction, before any implicit accesses to theaffected Page Table Entries, by such Page Tablesearches, are performed with respect to that pro-cessor.

� In conjunction with the tlbie and tlbsync instruc-tions, the ptesync instruction provides an orderingfunction for TLB invalidations and related storageaccesses on other processors as described in thetlbsync instruction description on page 56.

4.11.3 Lookaside BufferManagement

All implementations have a Segment Lookaside Buffer(SLB), and provide the SLB Management instructionsdescribed in Section 4.11.3.1.

For performance reasons, most implementations havea Translation Lookaside Buffer (TLB), which is a cacheof recently used Page Table Entries (PTEs). The TLBis not necessarily kept consistent with the Page Table

For instructions following a ptesync instruc-tion, the memory barrier need not order implicitstorage accesses for purposes of addresstranslation and reference and change record-ing.

The functions performed by the ptesyncinstruction may take a significant amount oftime to complete, so this form of the instructionshould be used only if the functions listedabove are needed. Otherwise sync with L=0should be used (or sync with L=1 or eieio, ifappropriate).

Section 4.12, “Page Table Update Synchroni-zation Requirements” on page 57 gives exam-ples of uses of ptesync.

Programming Note


Version 2.02

in main storage. When software alters the contents ofa PTE, it must also invalidate all corresponding TLBentries.

Each implementation that has a TLB provides a meansby which software can do the following.

� Invalidate the TLB entry that translates a giveneffective address

� Invalidate all TLB entries

An implementation may provide one or more of the TLBManagement instructions described in Section 4.11.3.2in order to satisfy requirements in the preceding list.Alternatively, an algorithm may be given that performsone of the functions listed above (a loop invalidatingindividual TLB entries may be used to invalidate theentire TLB, for example), or different instructions maybe provided. Such algorithms or instructions aredescribed in Book IV, PowerPC Implementation Fea-tures. Because most implementations have a TLB andalso provide instructions similar or identical to the TLBManagement instructions described in Section4.11.3.2, other sections of the Books assume that theTLB exists and that the instructions described in Sec-tion 4.11.3.2 are provided.

An implementation that does not have a TLB treats thecorresponding instructions (tlbie, tlbiel, tlbia, and tlb-sync) either as no-ops or as illegal instructions.

For performance reasons, some implementations haveimplementation-specific lookaside information used inaddress translation, such as a set of recently-usedtranslations of effective addresses to real addresses.Because this information may include "translations"that apply in real addressing mode, and such "transla-tions" are affected by the contents of the LPCR,RMOR, and HRMOR, when software modifies the con-tents of these registers it must also invalidate the corre-

sponding implementation-specific lookasideinformation.

Each implementation that has such implementation-specific lookaside information provides a means bywhich software can do the following.

� Invalidate all implementation-specific lookasideinformation used in converting effective addressesto real addresses.

Because the presence, absence, and exactsemantics of the TLB Management instructions areimplementation-dependent, it is recommended thatsystem software “encapsulate” uses of theseinstructions into subroutines to minimize the impactof moving from one implementation to another.

The function of all the instructions described inSections 4.11.3.1 and 4.11.3.2 is independent ofwhether address translation is enabled or disabled.

For a discussion of software synchronizationrequirements when invalidating SLB and TLBentries, see Chapter 7. “Synchronization Require-ments for Context Alterations” on page 85.

Programming Note

Programming Note


Version 2.02

4.11.3.1 SLB Management Instructions

SLB Invalidate Entry X-form

slbie RB

esid � (RB)0:35class � (RB)36if class = SLBEC for SLB entry that translates or most recently translated esid then for SLB entry (if any) that translates esid SLBEV � 0 all other fields of SLBE � undefined else translation of esid � undefined

Let the Effective Segment ID (ESID) be (RB)0:35. Letthe class be (RB)36. The class value must be the sameas the Class value in the SLB entry that translates theESID, or the Class value that was in the SLB entry thatmost recently translated the ESID if the translation is nolonger in the SLB; if the class value is not the same, theresults of translating effective addresses for whichEA0:35=ESID are undefined, and the next paragraphneed not apply.

If the SLB contains an entry that translates the speci-fied ESID, the V bit in that entry is set to 0, making theentry invalid, and the remaining fields of the entry areset to undefined values.

(RB)37:63 must be zeroes.

If this instruction is executed in 32-bit mode, (RB)0:31must be zeros (i.e., the ESID must be in the range 0-15).



Accesses to a given SLB entry caused by theinstructions described in this section obey thesequential execution model with respect to the con-tents of the entry and with respect to data depen-dencies on those contents. That is, if an instructionsequence contains two or more of these instruc-tions, when the sequence has completed, the finalstate of the SLB entry and of General PurposeRegisters is as if the instructions had been exe-cuted in program order.

However, software synchronization is required inorder to ensure that any alterations of the entrytake effect correctly with respect to address trans-lation; see Chapter 7.

31 /// /// RB 434 / 0 6 11 16 21 31

Programming Note

The only SLB entry that is invalidated is the entry (ifany) that translates the specified ESID.

slbie does not affect SLBs on other processors.

The reason the class value specified by slbie mustbe the same as the Class value that is or was in therelevant SLB entry is that the processor may usethese values to optimize invalidation of implemen-tation-specific lookaside information used inaddress translation. If the value specified by slbiediffers from the value that is or was in the relevantSLB entry, these optimizations may produce incor-rect results. (An example of implementation-spe-cific address translation lookaside information isthe set of recently used translations of effectiveaddresses to real addresses that some processorsmaintain in an Effective to Real Address Transla-tion (ERAT) lookaside buffer.)

The recommended use of the Class field is to clas-sify SLB entries according to the expected longev-ity of the translations they contain, or a similarproperty such as whether the translations are usedby all programs or only by a single program. If thisis done and the processor invalidates certain imple-mentation-specific lookaside information basedonly on the specified class value, an slbie instruc-tion that invalidates a short-lived translation willpreserve such lookaside information for long-livedtranslations.

If the optional “Bridge” facility is implemented (seeSection 9.1), the Move To Segment Registerinstructions create SLB entries in which the Classvalue is 0.

Programming Note

Programming Note


Version 2.02


Version 2.02

SLB Move To Entry X-form

slbmte RS,RB

The SLB entry specified by bits 52:63 of register RB isloaded from register RS and from the remainder of reg-ister RB. The contents of these registers are inter-preted as shown in Figure 32.

RS

RB

RS0:51 VSIDRS52 KsRS53 KpRS54 NRS55 LRS56 CRS57:63 must be 0b000_0000

RB0:35 ESIDRB36 VRB37:51 must be 0b000 || 0x000RB52:63 index, which selects the SLB entry

Figure 32. GPR contents for slbmte

On implementations that support a virtual address sizeof only n bits, n<80, (RS)0:79-n must be zeros.

High-order bits of (RB)52:63 that correspond to SLBentries beyond the size of the SLB provided by theimplementation must be zeros.

If this instruction is executed in 32-bit mode, (RB)0:31must be zeros (i.e., the ESID must be in the range 0-15).

This instruction cannot be used to invalidate an SLBentry.



31 RS /// RB 402 / 0 6 11 16 21 31

VSID KsKpNLC 0s0 52 57 63

ESID V 0s index0 36 37 52 63

The reason slbmte cannot be used to invalidate anSLB entry is that it does not necessarily affectimplementation-specific address translation looka-side information. slbie (or slbia) must be used forthis purpose.

Programming Note


Version 2.02

SLB Move From Entry VSID X-form

slbmfev RT,RB

If the SLB entry specified by bits 52:63 of register RB isvalid (V=1), the contents of the VSID, Ks, Kp, N, L, andC fields of the entry are placed into register RT. Thecontents of these registers are interpreted as shown inFigure 33.

RT

RB

RT0:51 VSIDRT52 KsRT53 KpRT54 NRT55 LRT56 CRT57:63 set to 0b000_0000

RB0:51 must be 0x0_0000_0000_0000RB52:63 index, which selects the SLB entry

Figure 33. GPR contents for slbmfev

On implementations that support a virtual address sizeof only n bits, n<80, RT0:79-n are set to zeros.

If the SLB entry specified by bits 52:63 of register RB isinvalid (V=0), the contents of register RT are undefined.




SLB Move From Entry ESID X-form

slbmfee RT,RB

If the SLB entry specified by bits 52:63 of register RB isvalid (V=1), the contents of the ESID and V fields of theentry are placed into register RT. The contents of theseregisters are interpreted as shown in Figure 34.

RT

RB

RT0:35 ESIDRT36 VRT37:63 set to 0b000 || 0x00_0000

RB0:51 must be 0x0_0000_0000_0000RB52:63 index, which selects the SLB entry

Figure 34. GPR contents for slbmfee

If the SLB entry specified by bits 52:63 of register RB isinvalid (V=0), RT36 is set to 0 and the contents ofRT0:35 and RT37:63 are undefined.




31 RT /// RB 851 /0 6 11 16 21 31

VSID KsKpNLC 0s0 52 57 63

0s index0 52 63

31 RT /// RB 915 /0 6 11 16 21 31

ESID V 0s0 36 37 63

0s index0 52 63


Version 2.02

4.11.3.2 TLB Management Instructions (Optional)

TLB Invalidate Entry X-form

tlbie RB,L[POWER mnemonic: tlbi]

if L = 0 then pg_size � 4 KB else pg_size � large page sizep � log_base_2(pg_size)for each processor in the partition for each TLB entry if (entry_VPN32:79-p = (RB)16:63-p) & (entry_pg_size = pg_size) then TLB entry � invalid

The contents of (RB)0:15 must be 0x0000. If the L fieldof the instruction is 1 let the page size be large; other-wise let the page size be 4 KB.

All TLB entries that have all of the following propertiesare made invalid on all processors that are in the samepartition as the processor executing the tlbie instruc-tion.

� The entry translates a virtual address for whichVPN32:79-p is equal to (RB)16:63-p.

� The page size of the entry matches the page sizespecified by the L field of the instruction.

Additional TLB entries may also be made invalid on anyprocessor that is in the same partition as the processorexecuting the tlbie instruction.

MSRSF must be 1 when this instruction is executed;otherwise the results are undefined.

The operation performed by this instruction is orderedby the eieio (or sync or ptesync) instruction withrespect to a subsequent tlbsync instruction executedby the processor executing the tlbie instruction. Theoperations caused by tlbie and tlbsync are ordered byeieio as a fourth set of operations, which is indepen-dent of the other three sets that eieio orders.

This instruction is privileged, and can be executed onlyin hypervisor state. If it is executed in privileged butnon-hypervisor state either a Privileged Instruction typeProgram interrupt occurs or the results are boundedlyundefined.

This instruction is optional.

See Section 4.12, “Page Table Update SynchronizationRequirements” for a description of other requirementsassociated with the use of this instruction.


31 /// L /// RB 306 /0 6 10 11 16 21 31


Version 2.02

TLB Invalidate Entry Local X-form

tlbiel RB,L

if L = 0 then pg_size � 4 KB else pg_size � large page sizep � log_base_2(pg_size)for each TLB entry if (entry_VPN32:79-p = (RB)16:63-p) & (entry_pg_size = pg_size) then TLB entry � invalid

The contents of (RB)0:15 must be 0x0000. If the L fieldof the instruction is 1 let the page size be large; other-wise let the page size be 4 KB.

All TLB entries that have all of the following propertiesare made invalid on the processor executing the tlbielinstruction.

� The entry translates a virtual address for whichVPN32:79-p is equal to (RB)16:63-p.

� The page size of the entry matches the page sizespecified by the L field of the instruction.

Only TLB entries on the processor executing the tlbielinstruction are affected.

(RB)52:63 must be zero.

MSRSF must be 1 when this instruction is executed;otherwise the results are undefined.



See Section 4.12, “Page Table Update SynchronizationRequirements” on page 57 for a description of otherrequirements associated with the use of this instruction.


31 /// L /// RB 274 /0 6 10 11 16 21 31

The primary use of this instruction by hypervisorstate code is to invalidate TLB entries prior to reas-signing a processor to a new logical partition.

tlbiel may be executed on a given processor evenif the sequence of tlbie - sync - tlbsync - ptesyncis being concurrently executed on a different pro-cessor. In other words, no programmatic synchro-nization is required relative to the execution of tlbieor tlbiel.

To synchronize the completion of this processorlocal form of tlbie, only a ptesync is required (tlb-sync should not be used).

Programming Note


Version 2.02

TLB Invalidate All X-form

tlbia

all TLB entries � invalid

All TLB entries are made invalid on the processor exe-cuting the tlbia instruction.

This instruction is privileged, and can be executed onlyin hypervisor state. If it is executed in privileged butnon-hypervisor state either a Privileged instruction typeProgram interrupt occurs or the results are boundedlyundefined.



31 /// /// /// 370 /0 6 11 16 21 31

tlbia does not affect TLBs on other processors.

Programming Note


Version 2.02

TLB Synchronize X-form

tlbsync

The tlbsync instruction provides an ordering functionfor the effects of all tlbie instructions executed by theprocessor executing the tlbsync instruction, withrespect to the memory barrier created by a subsequentptesync instruction executed by the same processor.Executing a tlbsync instruction ensures that all of thefollowing will occur.

� All TLB invalidations caused by tlbie instructionspreceding the tlbsync instruction will have com-pleted on any other processor before any dataaccesses caused by instructions following the pte-sync instruction are performed with respect to thatprocessor.

� All storage accesses by other processors for whichthe address was translated using the translationsbeing invalidated, and all Reference and Changebit updates associated with address translationsthat were performed by other processors using thetranslations being invalidated, will have been per-formed with respect to the processor executing theptesync instruction, to the extent required by theassociated Memory Coherence Requiredattributes, before the ptesync instruction’s mem-ory barrier is created.

The operation performed by this instruction is orderedby the eieio (or sync or ptesync) instruction withrespect to preceding tlbie instructions executed by theprocessor executing the tlbsync instruction. The oper-ations caused by tlbie and tlbsync are ordered byeieio as a fourth set of operations, which is indepen-dent of the other three sets that eieio orders.

The tlbsync instruction may complete before opera-tions caused by tlbie instructions preceding the tlb-sync instruction have been performed.



See Section 4.12, “Page Table Update SynchronizationRequirements” on page 57 for a description of otherrequirements associated with the use of this instruction.


31 /// /// /// 566 /0 6 11 16 21 31

tlbsync should not be used to synchronize thecompletion of tlbiel.

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4.12 Page Table UpdateSynchronization RequirementsThis section describes rules that software should followwhen updating the Page Table, and includes suggestedsequences of operations for some representativecases.

In the sequences of operations shown in the followingsubsections, any alteration of a Page Table Entry (PTE)that corresponds to a single line in the sequence isassumed to be done using a Store instruction for whichthe access is atomic. Appropriate modifications mustbe made to these sequences if this assumption is notsatisfied (e.g., if a store doubleword operation is doneusing two Store Word instructions).

All of the sequences require a context synchronizingoperation after the sequence if the new contents of thePTE are to be used for address translations associatedwith subsequent instructions.

As noted in the description of the Synchronize instruc-tion in Book II, address translation associated withinstructions which occur in program order subsequentto the Synchronize (and this includes the ptesync vari-ant) may actually be performed prior to the completionof the Synchronize. To ensure that these instructionsand data which may have been speculatively fetchedare discarded, a context synchronizing operation isrequired.

Page Table Entries must not be changed in a mannerthat causes an implicit branch.

4.12.1 Page Table Updates

TLBs are non-coherent caches of the HTAB. TLBentries must be invalidated explicitly with one of theTLB Invalidate instructions.

Unsynchronized lookups in the HTAB continueeven while it is being modified. Any processor,including a processor on which software is modifyingthe HTAB, may look in the HTAB at any time in anattempt to translate a virtual address. When modifyinga PTE, software must ensure that the PTE’s Valid bit is0 if the PTE is inconsistent (e.g., if the RPN field is notcorrect for the current AVPN field).

Updates of Reference and Change bits by the pro-cessor are not synchronized with the accesses thatcause the updates. When modifying the low-orderhalf of a PTE, software must take care to avoid over-writing a processor update of these bits and to avoidhaving the value written by a Store instruction overwrit-ten by a processor update. The processor does notalter any other fields of the PTE.

Before permitting one or more tlbie instructions to beexecuted on a given processor in a given partition soft-ware must ensure that no other processor will executea “conflicting instruction” until after the followingsequence of instructions has been executed on thegiven processor.

the tlbie instruction(s)eieio tlbsync ptesync

The “conflicting instructions” in this case are the follow-ing.

� a tlbie or tlbsync instruction, if executed onanother processor in the given partition

� an mtspr instruction that modifies the LPIDR, if themodification has either of the following properties.

- The old LPID value (i.e., the contents of theLPIDR just before the mtspr instruction isexecuted) is the value that identifies the givenpartition

- The new LPID value (i.e., the value specifiedby the mtspr instruction) is the value thatidentifies the given partition

Other instructions (excluding mtspr instructions thatmodify the LPIDR as described above, and excludingtlbie instructions except as shown) may be interleavedwith the instruction sequence shown above, but theinstructions in the sequence must appear in the order

The context synchronizing operation after thesequence ensures that any address translationsassociated with instructions following the contextsynchronizing operation that were performed usingthe old contents of the PTE will be discarded, withthe result that these address translations will beperformed again using the values stored by thesequence (or values stored subsequently). Inmany cases this context synchronization will occurnaturally; for example, if the sequence is executedwithin an interrupt handler the rfid or hrfid instruc-tion that returns from the interrupt handler may pro-vide the required context synchronization.

No context synchronizing operation is neededbefore any of the sequences, because (a) eachsequence begins with a store to the PTE, (b) nocontext synchronizing operation is needed beforethe corresponding Store instruction (see Note 8 ofChapter 7 on page 87), and (c) each sequence(except the sequence for resetting the Referencebit) explicitly orders subsequent operations withrespect to the store. These properties ensure thatall address translations associated with instructionspreceding the sequence will be performed usingthe old contents of the PTE.

Programming Note


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shown. On uniprocessor systems, the eieio and tlb-sync instructions can be omitted. Other instructionsmay be interleaved with this sequence of instructions,but these instructions must appear in the order shown.

The requirements specified above for tlbie instructionsapply also to tlbsync instructions, except that the“sequence of instructions” consists solely of the tlb-sync instruction(s) followed by a ptesync instruction.

Before permitting an mtspr instruction that modifies theLPIDR to be executed on a given processor, softwaremust ensure that no other processor will execute a“conflicting instruction” until after the mtspr instructionfollowed by a context synchronizing instruction havebeen executed on the given processor (a context syn-chronizing event can be used instead of the contextsynchronizing instruction; see Chapter 7).

The “conflicting instructions” in this case are the follow-ing.

� a tlbie or tlbsync instruction, if executed on a pro-cessor in either of the following partitions

- the partition identified by the old LPID value

- the partition identified by the new LPID value

Similarly, when a tlbsync instruction has been exe-cuted by a processor in a given partition, a ptesyncinstruction must be executed by that processor beforea tlbie or tlbsync instruction is executed by anotherprocessor in that partition.

The sequences of operations shown in the followingsubsections assume a multiprocessor environment. Ina uniprocessor environment the tlbsync can be omit-ted, as can the eieio that separates the tlbie from thetlbsync. In a multiprocessor environment, when tlbielis used instead of tlbie in a Page Table update, thesynchronization requirements are the same as whentlbie is used in a uniprocessor environment.

4.12.1.1 Adding a Page Table Entry

This is the simplest Page Table case. The Valid bit ofthe old entry is assumed to be 0. The followingsequence can be used to create a PTE, maintain a con-sistent state, and ensure that a subsequent referenceto the virtual address translated by the new entry willuse the correct real address and associated attributes.

PTERPN,AC,R,C,WIMG,N,PP � new valueseieio /* order 1st update before 2nd */PTEAVPN,SW,L,H,V � new values (V=1)ptesync /* order updates before next

Page Table search and before next data access. */

4.12.1.2 Modifying a Page Table Entry

General Case

If a valid entry is to be modified and the translationinstantiated by the entry being modified is to be invali-dated, the following sequence can be used to modify

The eieio instruction prevents the reordering oftlbie instructions previously executed by the pro-cessor with respect to the subsequent tlbsyncinstruction. The tlbsync instruction and the subse-quent ptesync instruction together ensure that allstorage accesses for which the address was trans-lated using the translations being invalidated, andall Reference and Change bit updates associatedwith address translations that were performedusing the translations being invalidated, will be per-formed with respect to any processor or mecha-nism, to the extent required by the associatedMemory Coherence Required attributes, beforeany data accesses caused by instructions followingthe ptesync instruction are performed with respectto that processor or mechanism.

The restrictions specified above regarding modify-ing the LPIDR apply even on uniprocessor sys-tems, and even if the new LPID value is equal tothe old LPID value.

Programming Note

Programming Note

For all of the sequences shown in the followingsubsections, if it is necessary to communicate com-pletion of the sequence to software running onanother processor, the ptesync instruction at theend of the sequence should be followed by a Storeinstruction that stores a chosen value to some cho-sen storage location X. The memory barrier cre-ated by the ptesync instruction ensures that if aLoad instruction executed by another processorreturns the chosen value from location X, thesequence’s stores to the Page Table have beenperformed with respect to that other processor. TheLoad instruction that returns the chosen valueshould be followed by a context synchronizinginstruction in order to ensure that all instructionsfollowing the context synchronizing instruction willbe fetched and executed using the values storedby the sequence (or values stored subsequently).(These instructions may have been fetched or exe-cuted out-of-order using the old contents of thePTE.)

This Note assumes that the Page Table and loca-tion X are in storage that is Memory CoherenceRequired.

Programming Note


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the PTE, maintain a consistent state, ensure that thetranslation instantiated by the old entry is no longeravailable, and ensure that a subsequent reference tothe virtual address translated by the new entry will usethe correct real address and associated attributes.(The sequence is equivalent to deleting the PTE andthen adding a new one; see Sections 4.12.1.3 and4.12.1.1.)

PTEV � 0 /* (other fields don’t matter)*/ptesync /* order update before tlbie and

before next Page Table search */tlbie(old_VPN32:79-p,old_L) /*invalidate old

translation */eieio /* order tlbie before tlbsync */tlbsync /* order tlbie before ptesync */ptesync /* order tlbie, tlbsync and 1st

update before 2nd update */PTERPN,AC,R,C,WIMG,N,PP � new valueseieio /* order 2nd update before 3rd */PTEAVPN,SW,L,H,V � new values (V=1)ptesync /* order 2nd and 3rd updates before

next Page Table search and before next data access */

Resetting the Reference Bit

If the only change being made to a valid entry is to setthe Reference bit to 0, a simpler sequence sufficesbecause the Reference bit need not be maintainedexactly.oldR � PTER /* get old R */if oldR = 1 then PTER � 0 /* store byte (R=0, other bits

unchanged) */ tlbie(VPN32:79-p,L) /* invalidate entry */ eieio /* order tlbie before tlbsync */ tlbsync /* order tlbie before ptesync */ ptesync /* order tlbie, tlbsync, and update

before next Page Table search and before next data access */

Modifying the Virtual Address

If the virtual address translated by a valid PTE is to bemodified and the new virtual address hashes to thesame two PTEGs as does the old virtual address, thefollowing sequence can be used to modify the PTE,maintain a consistent state, ensure that the translationinstantiated by the old entry is no longer available, andensure that a subsequent reference to the virtualaddress translated by the new entry will use the correctreal address and associated attributes.

PTEAVPN,SW,L,H,V � new values (V=1)ptesync /* order update before tlbie and

before next Page Table search */tlbie(old_VPN32:79-p,old_L) /* invalidate old

translation */eieio /* order tlbie before tlbsync */tlbsync /* order tlbie before ptesync */ptesync /* order tlbie, tlbsync, and update

before next data access */

To modify the AC, N, or PP bits without overwriting aReference or Change bit update being performed bythe processor or by some other processor, a sequencesimilar to that shown above can be used except thatthe first line would be replaced by a ptesync instructionfollowed by a loop containing a ldarx/stdcx. pair thatemulates an atomic “Compare and Swap” of the low-order doubleword of the PTE. (See the section entitled“Atomic Update Primitives” in Book II, PowerPC VirtualEnvironment Architecture for a description of “Com-pare and Swap”.)

4.12.1.3 Deleting a Page Table Entry

The following sequence can be used to ensure that thetranslation instantiated by an existing entry is no longeravailable.

PTEV � 0 /* (other fields don’t matter) */ptesync /* order update before tlbie and

before next Page Table search */tlbie(old_VPN32:79-p,old_L) /* invalidate old

translation */eieio /* order tlbie before tlbsync */tlbsync /* order tlbie before ptesync */ptesync /* order tlbie, tlbsync, and update

before next data access */


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Chapter 5. Interrupts

5.1 Overview. . . . . . . . . . . . . . . . . . . . . 615.2 Interrupt Synchronization . . . . . . . . 615.3 Interrupt Classes . . . . . . . . . . . . . . 625.3.1 Precise Interrupt . . . . . . . . . . . . . 625.3.2 Imprecise Interrupt. . . . . . . . . . . . 625.4 Interrupt Processing . . . . . . . . . . . . 625.4.1 Hypervisor Interrupts . . . . . . . . . . 635.5 Interrupt Definitions . . . . . . . . . . . . 655.5.1 System Reset Interrupt . . . . . . . . 665.5.2 Machine Check Interrupt . . . . . . . 665.5.3 Data Storage Interrupt . . . . . . . . . 665.5.4 Data Segment Interrupt . . . . . . . . 685.5.5 Instruction Storage Interrupt . . . . 685.5.6 Instruction Segment

Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . 695.5.7 External Interrupt . . . . . . . . . . . . . 695.5.8 Alignment Interrupt . . . . . . . . . . . 69

5.5.9 Program Interrupt . . . . . . . . . . . . . 705.5.10 Floating-Point Unavailable

Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 725.5.11 Decrementer Interrupt . . . . . . . . 725.5.12 Hypervisor Decrementer

Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 725.5.13 System Call Interrupt . . . . . . . . . 735.5.14 Trace Interrupt . . . . . . . . . . . . . . 735.5.15 Performance Monitor

Interrupt (Optional) . . . . . . . . . . . . . . . . 735.6 Partially Executed

Instructions . . . . . . . . . . . . . . . . . . . . . . 735.7 Exception Ordering . . . . . . . . . . . . . 745.7.1 Unordered Exceptions . . . . . . . . . 745.7.2 Ordered Exceptions . . . . . . . . . . . 745.8 Interrupt Priorities . . . . . . . . . . . . . . 76

5.1 OverviewThe PowerPC Architecture provides an interrupt mech-anism to allow the processor to change state as a resultof external signals, errors, or unusual conditions arisingin the execution of instructions.

System Reset and Machine Check interrupts are notordered. All other interrupts are ordered such that onlyone interrupt is reported, and when it is processed(taken) no program state is lost. Since Save/RestoreRegisters SRR0 and SRR1 are serially reusableresources used by most interrupts, program state maybe lost when an unordered interrupt is taken.

5.2 Interrupt SynchronizationWhen an interrupt occurs, SRR0 or HSRR0 is set topoint to an instruction such that all preceding instruc-tions have completed execution, no subsequentinstruction has begun execution, and the instructionaddressed by SRR0 or HSRR0 may or may not havecompleted execution, depending on the interrupt type.

With the exception of System Reset and MachineCheck interrupts, all interrupts are context synchroniz-ing as defined in Section 1.6.1, “Context Synchroniza-tion” on page 4. System Reset and Machine Checkinterrupts are context synchronizing if they are recover-able (i.e., if bit 62 of SRR1 is set to 1 by the interrupt).If a System Reset or Machine Check interrupt is notrecoverable (i.e., if bit 62 of SRR1 is set to 0 by theinterrupt), it acts like a context synchronizing operationwith respect to subsequent instructions. That is, a non-recoverable System Reset or Machine Check interruptneed not satisfy items 1 through 3 of Section 1.6.1, butdoes satisfy items 4 and 5.

Chapter 5. Interrupts 61

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5.3 Interrupt ClassesInterrupts are classified by whether they are directlycaused by the execution of an instruction or are causedby some other system exception. Those that are “sys-tem-caused” are:

� System Reset� Machine Check� External� Decrementer� Hypervisor Decrementer

External, Decrementer, and Hypervisor Decrementerinterrupts are maskable interrupts. Therefore, softwaremay delay the generation of these interrupts. SystemReset and Machine Check interrupts are not maskable.

“Instruction-caused” interrupts are further divided intotwo classes, precise and imprecise.

5.3.1 Precise Interrupt

Except for the Imprecise Mode Floating-Point EnabledException type Program interrupt, all instruction-caused interrupts are precise.

When the fetching or execution of an instruction causesa precise interrupt, the following conditions exist at theinterrupt point.

1. SRR0 addresses either the instruction causing theexception or the immediately following instruction.Which instruction is addressed can be determinedfrom the interrupt type and status bits.

2. An interrupt is generated such that all instructionspreceding the instruction causing the exceptionappear to have completed with respect to the exe-cuting processor.

3. The instruction causing the exception may appearnot to have begun execution (except for causingthe exception), may have been partially executed,or may have completed, depending on the inter-rupt type.

4. Architecturally, no subsequent instruction hasbegun execution.

5.3.2 Imprecise Interrupt

This architecture defines one imprecise interrupt, theImprecise Mode Floating-Point Enabled Exception typeProgram interrupt.

When an Imprecise Mode Floating-Point EnabledException type Program interrupt occurs, the followingconditions exist at the interrupt point.

1. SRR0 addresses either the instruction causing theexception or some instruction following thatinstruction; see Section 5.5.9, “Program Interrupt”on page 70.

2. An interrupt is generated such that all instructionspreceding the instruction addressed by SRR0appear to have completed with respect to the exe-cuting processor.

3. The instruction addressed by SRR0 may appearnot to have begun execution (except, in somecases, for causing the interrupt to occur), mayhave been partially executed, or may have com-pleted; see Section 5.5.9.

4. No instruction following the instruction addressedby SRR0 appears to have begun execution.

All Floating-Point Enabled Exception type Programinterrupts are maskable using the MSR bits FE0 andFE1. Although these interrupts are maskable, they dif-fer significantly from the other maskable interrupts inthat the masking of these interrupts is usually controlledby the application program, whereas the masking of allother maskable interrupts is controlled by either theoperating system or the hypervisor.

5.4 Interrupt ProcessingAssociated with each kind of interrupt is an interruptvector, which contains the initial sequence of instruc-tions that is executed when the corresponding interruptoccurs.

Interrupt processing consists of saving a small part ofthe processor’s state in certain registers, identifying thecause of the interrupt in other registers, and continuingexecution at the corresponding interrupt vector loca-tion. When an exception exists that will cause an inter-rupt to be generated and it has been determined thatthe interrupt will occur, the following actions are per-formed. The handling of Machine Check interrupts(see Section 5.5.2) differs from the description givenbelow in several respects.

1. SRR0 or HSRR0 is loaded with an instructionaddress that depends on the type of interrupt; seethe specific interrupt description for details.

2. Bits 33:36 and 42:47 of SRR1 or HSRR1 areloaded with information specific to the interrupttype.

3. Bits 0:32, 37:41, and 48:63 of SRR1 or HSRR1 areloaded with a copy of the corresponding bits of theMSR.

4. The MSR is set as shown in Figure 35 on page 65.In particular, MSR bits IR and DR are set to 0, dis-abling relocation, and MSR bit SF is set to 1,selecting 64-bit mode. The new values take effect


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beginning with the first instruction executed follow-ing the interrupt.

5. Instruction fetch and execution resumes, using thenew MSR value, at the effective address specific tothe interrupt type. These effective addresses areshown in Figure 36 on page 65.

Interrupts do not clear reservations obtained with lwarxor ldarx.

5.4.1 Hypervisor Interrupts

The execution of some of the more complex instruc-tions may alter the content of HSRR0 and HSRR1 as aside effect of executing the instruction. For hypervisorinterrupts, interrupts that use HSRR0 and HSRR1 tosave and restore the state of the interrupted program,the following list identifies the set of instruction thatwhen executed will not alter the content of HSRR0 andHSRR1. Any omission of instruction suffixes is signifi-cant; e.g., add is listed but add. is excluded.

In general, when an interrupt occurs, the followinginstructions should be executed by the operatingsystem before dispatching a “new” program.

� stwcx. or stdcx., to clear the reservation ifone is outstanding, to ensure that a lwarx orldarx in the interrupted program is not pairedwith a stwcx. or stdcx. in the “new” program.

� sync, to ensure that all storage accessescaused by the interrupted program will be per-formed with respect to another processorbefore the program is resumed on that otherprocessor.

� isync or rfid, to ensure that the instructions inthe “new” program execute in the “new” con-text.

If a program modifies an instruction that it oranother program will subsequently execute and theexecution of the instruction causes an interrupt, thestate of storage and the content of some processorregisters may appear to be inconsistent to the inter-rupt handler program. For example, this could bethe result of one program executing an instructionthat causes an Illegal Instruction type Programinterrupt just before another instance of the sameprogram stores an Add Immediate instruction inthat storage location. To the interrupt handlercode, it would appear that a processor generatedthe Program interrupt as the result of executing avalid instruction.

Programming Note

Programming Note

In order to handle Machine Check and SystemReset interrupts correctly, the operating systemshould manage MSRRI as follows.

� In the Machine Check and System Reset inter-rupt handlers, interpret SRR1 bit 62 (whereMSRRI is placed) as:

- 0: interrupt is not recoverable- 1: interrupt is recoverable

� In each interrupt handler, when enough statehas been saved that a Machine Check or Sys-tem Reset interrupt can be recovered from, setMSRRI to 1.

� In each interrupt handler, do the following (inorder) just before returning.

1. Set MSRRI to 0.2. Set SRR0 and SRR1 to the values to be

used by rfid. The new value of SRR1should have bit 62 set to 1 (which will hap-pen naturally if SRR1 is restored to thevalue saved there by the interrupt,because the interrupt handler will not beexecuting this sequence unless the inter-rupt is recoverable).

3. Execute rfid.

For interrupts that set the SRRs other thanMachine Check or System Reset, MSRRI can bemanaged similarly when these interrupts occurwithin interrupt handlers for other interrupts that setthe SRRs.

This Note does not apply to interrupts that set theHSRRs because these interrupts put the processorinto hypervisor state, and either do not occur or canbe prevented from occurring within interrupt han-dlers for other interrupts that set the HSRRs.

Programming Note


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1. Branch Instructions

b[l][a], bc[l][a], bclr[l], bcctr[l]

2. Fixed-Point Load and Store Instructions

lbz, lbzx, lhz, lhzx, lwz, lwzx, ld, ldx, stb, stbx,sth, sthx, stw, stwx, std, stdx

Storage operands must be aligned and MSRIR DRmust be 0b00 (translation disabled). Accessing anunaligned storage operand or translating a virtualaddress may have the side effect of alteringHSRR0 and HSRR1.

3. Arithmetic Instructions

addi, addis, add, subf, neg

4. Compare Instructions

cmpi, cmp, cmpli, cmpl

5. Logical and Extend Sign Instructions

ori, oris, xori, xoris, and, or, xor, nand, nor, eqv,andc, orc, extsb, extsh, extsw

6. Rotate and Shift Instructions

rldicl, rldicr, rldic, rlwinm, rldcl, rldcr, rlwnm,rldimi, rlwimi, sld, slw, srd, srw

7. Other instructions

isync

rfid, hrfid

mtspr, mfspr, mtmsrd, mfmsr

Instructions not listed below may be used after thecontents of HSSR0 and HSRR1 have been savedon entry to the interrupt and before they arerestored on return to the interrupted program.

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5.5 Interrupt DefinitionsFigure 35 shows all the types of interrupts and the val-ues assigned to the MSR for each. Figure 36 showsthe effective address of the interrupt vector for eachinterrupt type. (Section 4.2.7 on page 31 summarizesall architecturally defined uses of effective addresses,including those implied by Figure 36.)

Figure 35. MSR setting due to interrupt

Figure 36. Effective address of interrupt vector by interrupt type

Interrupt Type MSR Bit IR DR FE0 FE1 EE RI ME HV

System Reset 0 0 0 0 0 0 - 1

Machine Check 0 0 0 0 0 0 0 1

Data Storage 0 0 0 0 0 0 - m

Data Segment 0 0 0 0 0 0 - m

Instruction Storage 0 0 0 0 0 0 - m

Instruction Segment 0 0 0 0 0 0 - m

External 0 0 0 0 0 0 - e

Alignment 0 0 0 0 0 0 - m

Program 0 0 0 0 0 0 - m

FP Unavailable 0 0 0 0 0 0 - m

Decrementer 0 0 0 0 0 0 - m

Hypervisor Decrem’er 0 0 0 0 0 - - 1

System Call 0 0 0 0 0 0 - s

Trace 0 0 0 0 0 0 - m

Performance Monitor 0 0 0 0 0 0 - m

0 bit is set to 01 bit is set to 1- bit is not alteredm if LPES1=0, set to 1; otherwise not alterede if LPES0=0, set to 1; otherwise not altereds if LEV=1 or LPES/LPES1=0, set to 1; other-

wise not altered

Settings for Other Bits

Bits BE, FP, PMM, PR, and SE are set to 0.

If the optional Little-Endian facility is implemented(see the section entitled “Little-Endian” in Book I), thebits associated with the facility are set as follows. Ifthe interrupt sets HV to 1, LE is set to 0; otherwisethe LE bit is copied from the LPCRILE bit

Bit SF is set to 1.

Reserved bits are set as if written as 0.

Effective Address1

Interrupt Type

00..0000_0100 System Reset 00..0000_0200 Machine Check 00..0000_0300 Data Storage 00..0000_0380 Data Segment 00..0000_0400 Instruction Storage 00..0000_0480 Instruction Segment 00..0000_0500 External 00..0000_0600 Alignment 00..0000_0700 Program 00..0000_0800 Floating-Point Unavailable 00..0000_0900 Decrementer 00..0000_0980 Hypervisor Decrementer 00..0000_0A00 Reserved 00..0000_0B00 Reserved 00..0000_0C00 System Call 00..0000_0D00 Trace 00..0000_0E00 Reserved 00..0000_0E10 Reserved . . . . . . 00..0000_0EFF Reserved 00..0000_0F00 Performance Monitor 00..0000_0F10 Reserved . . . . . . 00..0000_0FFF Reserved1 The values in the Effective Address column are

interpreted as follows.� 00...0000_nnnn means

0x0000_0000_0000_nnnn2 Effective addresses 0x0000_0000_0000_0000

through 0x0000_0000_0000_00FF are used by software and will not be assigned as interrupt vectors.

When address translation is disabled, use of any ofthe effective addresses that are shown as reservedin Figure 36 risks incompatibility with future imple-mentations.

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5.5.1 System Reset Interrupt

If a System Reset exception causes an interrupt that isnot context synchronizing or causes the loss of aMachine Check exception or an External exception, orif the state of the processor has been corrupted, theinterrupt is not recoverable.

The following registers are set:

SRR0 Set to the effective address of the instruc-tion that the processor would haveattempted to execute next if no interruptconditions were present.

SRR133:36 Set to 0.42:44 See the Book IV, PowerPC Implementation

Features document for the implementation.45:47 Set to 0.62 Loaded from bit 62 of the MSR if the pro-

cessor is in a recoverable state; otherwiseset to 0.

Others Loaded from the MSR.

MSR See Figure 35 on page 65.

Execution resumes at effective address0x0000_0000_0000_0100.

Each implementation provides a means for software todistinguish power-on Reset from other types of SystemReset, and describes it in the Book IV.

5.5.2 Machine Check Interrupt

The causes of Machine Check interrupts are implemen-tation-dependent. For example, a Machine Check inter-rupt may be caused by a reference to a storagelocation that contains an uncorrectable error or doesnot exist (see Section 4.2.8, “Invalid Real Address” onpage 31), or by an error in the storage subsystem.

Machine Check interrupts are enabled whenMSRME=1. If MSRME=0 and a Machine Check occurs,the processor enters the Checkstop state. The Check-stop state may also be entered if an access isattempted to a storage location that does not exist (seeSection 4.2.8).

Disabled Machine Check (Checkstop State)

When a processor is in Checkstop state, instructionprocessing is suspended and generally cannot berestarted without resetting the processor. Some imple-mentations may preserve some or all of the internalstate of the processor when entering Checkstop state,so that the state can be analyzed as an aid in problemdetermination.

Enabled Machine Check

If a Machine Check exception causes an interrupt thatis not context synchronizing or causes the loss of anExternal exception, or if the state of the processor hasbeen corrupted, the interrupt is not recoverable.

In some systems, the operating system may attempt toidentify and log the cause of the Machine Check.


SRR0 Set on a “best effort” basis to the effectiveaddress of some instruction that was exe-cuting or was about to be executed whenthe Machine Check exception occurred.For further details see the Book IV, Pow-erPC Implementation Features documentfor the implementation.

SRR162 Loaded from bit 62 of the MSR if the pro-

cessor is in a recoverable state; otherwiseset to 0.

Others See Book IV.

MSR See Figure 35.

DSISR See Book IV.

DAR See Book IV.


5.5.3 Data Storage Interrupt

A Data Storage interrupt occurs when no higher priorityexception exists and a data access cannot be per-formed for any of the following reasons.

� Data address translation is enabled (MSRDR=1)and the virtual address of any byte of the storagelocation specified by a Load, Store, icbi, dcbz,dcbst, dcbf[l], eciwx, or ecowx instruction cannotbe translated to a real address.

� The effective address specified by a lwarx, ldarx,stwcx., or stdcx. instruction refers to storage thatis Write Through Required or Caching Inhibited.

� The access violates storage protection.� A Data Address Compare match or a Data

Address Breakpoint match occurs.� Execution of an eciwx or ecowx instruction is dis-

allowed because EARE=0.

If a Machine Check interrupt is caused by an errorin the storage subsystem, the storage subsystemmay return incorrect data, which may be placedinto registers. This corruption of register contentsmay occur even if the interrupt is recoverable.

Programming Note


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If a stwcx. or stdcx. would not perform its store in theabsence of a Data Storage interrupt, and either (a) thespecified effective address refers to storage that isWrite Through Required or Caching Inhibited, or (b) anon-conditional Store to the specified effective addresswould cause a Data Storage interrupt, it is implementa-tion-dependent whether a Data Storage interruptoccurs.

If the contents of the XER specifies a length of zerobytes for a Move Assist instruction, a Data Storageinterrupt does not occur for reasons of address transla-tion, or storage protection. If such an instructioncauses a Data Storage interrupt for other reasons, thesetting of the DSISR and DAR reflects only these otherreasons listed in the preceding sentence. (E.g., if suchan instruction causes a storage protection violationand a Data Address Breakpoint match, the DSISR andDAR are set as if the storage protection violation didnot occur.)


SRR0 Set to the effective address of the instruc-tion that caused the interrupt.

SRR133:36 Set to 0.42:47 Set to 0.Others Loaded from the MSR.

MSR See Figure 35.

DSISR0 Set to 0.1 Set to 1 if MSRDR=1 and the translation for

an attempted access is not found in the pri-mary PTEG or in the secondary PTEG; oth-erwise set to 0.

2:3 Set to 0.4 Set to 1 if the access is not permitted by the

storage protection mechanism; otherwiseset to 0.

5 Set to 1 if the access is due to a lwarx,ldarx, stwcx., or stdcx. instruction thataddresses storage that is Write ThroughRequired or Caching Inhibited; otherwiseset to 0.

6 Set to 1 for a Store, dcbz, or ecowxinstruction; otherwise set to 0.

7:8 Set to 0.

9 Set to 1 if a Data Address Compare matchor a Data Address Breakpoint matchoccurs; otherwise set to 0.

10 Set to 0.11 Set to 1 if execution of an eciwx or ecowx

instruction is attempted when EARE=0; oth-erwise set to 0.

12:14 Set to 0.15 Set to an undefined value.

16:31 Set to 0.

DAR Set to the effective address of a storageelement as described in the following list.The list should be read from the top down;the DAR is set as described by the first itemthat corresponds to an exception that isreported in the DSISR. For example, if aLoad instruction causes a storage protec-tion violation and a Data Address Break-point match (and both are reported in theDSISR), the DAR is set to the effectiveaddress of a byte in the first aligned double-word for which access was attempted in thepage that caused the exception.� a Data Storage exception occurs for

reasons other than a Data AddressBreakpoint match or, for eciwx andecowx, EARE=0- a byte in the block that caused the

exception, for a Cache Manage-ment instruction

- a byte in the first aligned double-word for which access wasattempted in the page that causedthe exception, for a Load, Store,eciwx, or ecowx instruction (“first”refers to address order; seeSection 5.7)

� undefined, for a Data Address Break-point match, or if eciwx or ecowx isexecuted when EARE=0

For the cases in which the DAR is specifiedabove to be set to a defined value, if theinterrupt occurs in 32-bit mode the high-order 32 bits of the DAR are set to 0.

If multiple Data Storage exceptions occur for a giveneffective address, any one or more of the bits corre-sponding to these exceptions may be set to 1 in theDSISR.

The only cases in which DSISR4 canbe set to 1 for an access that occurswhen MSRDR=0 are those described inFigure 31. These cases can be distin-guished from other causes of data stor-age protection violations by examiningSRR159 (the bit in which MSRDR wassaved by the interrupt).

Programming Note

Warning: This setting of DSISR15 isbeing phased out of the architecture.Future versions of the architecture willspecify that the Data Storage interruptsets DSISR15 to 0.

Programming Note


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5.5.4 Data Segment Interrupt

A Data Segment interrupt occurs when no higher prior-ity exception exists and a data access cannot be per-formed because data address translation is enabledand the effective address of any byte of the storagelocation specified by a Load, Store, icbi, dcbz, dcbst,dcbf[l] eciwx, or ecowx instruction cannot be trans-lated to a virtual address.

If a stwcx. or stdcx. would not perform its store in theabsence of a Data Segment interrupt, and a non-condi-tional Store to the specified effective address wouldcause a Data Segment interrupt, it is implementation-dependent whether a Data Segment interrupt occurs.

If a Move Assist instruction has a length of zero (in theXER), a Data Segment interrupt does not occur,regardless of the effective address.




MSR See Figure 35.

DSISR Set to an undefined value.

DAR Set to the effective address of a storageelement as described in the following list.� a byte in the block that caused the

Data Segment interrupt, for a CacheManagement instruction

� a byte in the first aligned doublewordfor which access was attempted in thesegment that caused the Data Seg-ment interrupt, for a Load, Store,eciwx, or ecowx instruction (“first”

refers to address order; seeSection 5.7)

If the interrupt occurs in 32-bit mode, thehigh-order 32 bits of the DAR are set to 0.


5.5.5 Instruction Storage Interrupt

An Instruction Storage interrupt occurs when no higherpriority exception exists and the next instruction to beexecuted cannot be fetched for any of the following rea-sons.

� Instruction address translation is enabled and thevirtual address cannot be translated to a realaddress.

� The fetch access violates storage protection.


SRR0 Set to the effective address of the instructionthat the processor would have attempted toexecute next if no interrupt conditions werepresent (if the interrupt occurs on attemptingto fetch a branch target, SRR0 is set to thebranch target address).

SRR133 Set to 1 if MSRIR=1 and the translation for

an attempted access is not found in the pri-mary PTEG or in the secondary PTEG; oth-erwise set to 0.

34 Set to 0.35 Set to 1 if the access occurs when

MSRIR=1 and is to No-execute storage orto Guarded storage; otherwise set to 0.

36 Set to 1 if the access is not permitted byFigure 30 or 31, as appropriate; otherwiseset to 0.

More than one bit may be set to 1 in the DSISR inthe following combinations.

1, {s+}1, 15, {s+}4, {s+}4, 5, {s}5, {s}{s+}

In this list, “{s}” represents any combination of theset of bits {6, 9} and “{s+}” adds bit 11 to this set.

Programming Note

A Data Segment interrupt occurs if MSRDR=1 andthe translation of the effective address of any byteof the specified storage location is not found in theSLB.

The only cases in which SRR136 canbe set to 1 for an access that occurswhen MSRIR=0 are those described inFigure 31. These cases can be distin-guished from other causes of instruc-tion storage protection violations thatset SRR136 to 1 by examining SRR158(the bit in which MSRIR was saved bythe interrupt).

Programming Note

Programming Note


Version 2.02

42:46 Set to 0.47 Set to an undefined value.


MSR See Figure 35.

If multiple Instruction Storage exceptions occur due toattempting to fetch a single instruction, any one or moreof the bits corresponding to these exceptions may beset to 1 in SRR1.


5.5.6 Instruction SegmentInterrupt

An Instruction Segment interrupt occurs when nohigher priority exception exists and the next instructionto be executed cannot be fetched because instructionaddress translation is enabled and the effectiveaddress cannot be translated to a virtual address.


SRR0 Set to the effective address of the instructionthat the processor would have attempted toexecute next if no interrupt conditions werepresent (if the interrupt occurs on attempting

to fetch a branch target, SRR0 is set to thebranch target address).




5.5.7 External Interrupt

An External interrupt occurs when no higher priorityexception exists, an External exception exists, andMSREE=1. The occurrence of the interrupt does notcause the exception to cease to exist.


SRR0 Set to the effective address of the instructionthat the processor would have attempted toexecute next if no interrupt conditions werepresent.


MSR See Figure 35.


5.5.8 Alignment Interrupt

An Alignment interrupt occurs when no higher priorityexception exists and a data access cannot be per-formed for any of the following reasons.

� The operand of a floating-point Load or Store is notword-aligned, or crosses a virtual page boundary.

� The operand of lmw, stmw, lwarx, ldarx, stwcx.,stdcx., eciwx, or ecowx is not aligned.

� The operand of a single-register Load or Store isnot aligned and the processor is in Little-Endianmode.

� The instruction is lmw, stmw, lswi, lswx, stswi, orstswx, and the operand is in storage that is Write

Warning: This setting of SRR147 isbeing phased out of the architecture.Future versions of the architecture willspecify that the Instruction Storageinterrupt sets SRR147 to 0. New soft-ware should not depend on the settingdescribed above, and any such depen-dency in existing software should beremoved. (In distinction from the corre-sponding case for DSISR15 as set bythe Data Storage interrupt, implementa-tions of future versions of the architec-ture cannot treat SRR147 as reserved,because SRR147 is set to a meaningfulvalue by other interrupts, e.g., the Pro-gram interrupt.)

More than one bit may be set to 1 in SRR1 in thefollowing combinations.

33, 3533, 4733, 35, 4735, 36

Programming Note

Programming Note

An Instruction Segment interrupt occurs ifMSRIR=1 and the translation of the effectiveaddress of the next instruction to be executed is notfound in the SLB.

Programming Note


Version 2.02

Through Required or Caching Inhibited, or the pro-cessor is in Little-Endian mode.

� The operand of a Load or Store crosses a segmentboundary, or crosses a boundary between virtualpages that have different storage control attributes.

� The operand of a Load or Store is not aligned andis in storage that is Write Through Required orCaching Inhibited.

� The operand of dcbz, lwarx, ldarx, stwcx., orstdcx. is in storage that is Write Through Requiredor Caching Inhibited.

If a stwcx. or stdcx. would not perform its store in theabsence of an Alignment interrupt and the specifiedeffective address refers to storage that is WriteThrough Required or Caching Inhibited, it is implemen-tation-dependent whether an Alignment interruptoccurs.

Setting the DSISR and DAR as described below isoptional for implementations on which Alignment inter-rupts occur rarely, if ever, for cases that the Alignmentinterrupt handler emulates. For such implementations,if the DSISR and DAR are not set as described belowthey are set to undefined values.


SRR0 Set to the effective address of the instructionthat caused the interrupt.


MSR See Figure 35.

DSISR0:11 Set to 0.12:13 Set to bits 30:31 of the instruction if DS-

form. Set to 0b00 if D-, or X-form.14 Set to 0.15:16 Set to bits 29:30 of the instruction if X-form.

Set to 0b00 if D- or DS-form.17 Set to bit 25 of the instruction if X-form. Set

to bit 5 of the instruction if D- or DS-form.18:21 Set to bits 21:24 of the instruction if X-form.

Set to bits 1:4 of the instruction if D- or DS-form.

22:26 Set to bits 6:10 of the instruction (RT/RS/FRT/FRS), except undefined for dcbz.

27:31 Set to bits 11:15 of the instruction (RA) forupdate form instructions; set to either bits11:15 of the instruction or to any registernumber not in the range of registers to beloaded for a valid form lmw, a valid formlswi, or a valid form lswx for which neitherRA nor RB is in the range of registers to beloaded; otherwise undefined.

DAR Set to the effective address computed bythe instruction, except that if the interruptoccurs in 32-bit mode the high-order 32 bitsof the DAR are set to 0.

For an X-form Load or Store, it is acceptable for theprocessor to set the DSISR to the same value thatwould have resulted if the corresponding D- or DS-forminstruction had caused the interrupt. Similarly, for a D-or DS-form Load or Store, it is acceptable for the pro-cessor to set the DSISR to the value that would haveresulted for the corresponding X-form instruction. Forexample, an unaligned lwax (that crosses a protectionboundary) would normally, following the descriptionabove, cause the DSISR to be set to binary:

000000000000 00 0 01 0 0101 ttttt ?????

where “ttttt” denotes the RT field, and “?????” denotesan undefined 5-bit value. However, it is acceptable if itcauses the DSISR to be set as for lwa, which is

000000000000 10 0 00 0 1101 ttttt ?????

If there is no corresponding alternative form instruction(e.g., for lwaux), the value described above is set inthe DSISR.

The instruction pairs that may use the same DSISRvalue are.


5.5.9 Program Interrupt

A Program interrupt occurs when no higher priorityexception exists and one of the following exceptionsarises during execution of an instruction:

lhz/lhzx lhzu/lhzux lha/lhax lhau/lhaux

lwz/lwzx lwzu/lwzux lwa/lwax

ld/ldx ldu/ldux

lsth/sthx sthu/sthux stw/stwx stwu/stwux

std/stdx stdu/stdux

lfs/lfsx lfsu/lfsux lfd/lfdx lfdu/lfdux

stfs/stfsx stfsu/stfsux stfd/stfdx stfdu/stfdux

The architecture does not support the use of anunaligned effective address by lwarx, ldarx,stwcx., stdcx., eciwx, and ecowx. If an Align-ment interrupt occurs because one of these instruc-tions specifies an unaligned effective address, theAlignment interrupt handler must not attempt tosimulate the instruction, but instead should treatthe instruction as a programming error.

Programming Note


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Floating-Point Enabled Exception

A Floating-Point Enabled Exception type Programinterrupt is generated when the value of theexpression

(MSRFE0 | MSRFE1) & FPSCRFEX

is 1. FPSCRFEX is set to 1 by the execution of afloating-point instruction that causes an enabledexception, including the case of a Move To FPSCRinstruction that causes an exception bit and thecorresponding enable bit both to be 1.

Illegal Instruction

An Illegal Instruction type Program interrupt is gen-erated when execution is attempted of an illegalinstruction, or of a reserved or optional instructionthat is not provided by the implementation.

An Illegal Instruction type Program interrupt maybe generated when execution is attempted of anyof the following kinds of instruction.

� an instruction that is in invalid form

� an lswx instruction for which RA or RB is inthe range of registers to be loaded

� an mtspr or mfspr instruction with an SPRfield that does not contain one of the definedvalues, or an mftb instruction with a TBR fieldthat does not contain one of the defined val-ues

Privileged Instruction

The following applies if the instruction is executedwhen MSRPR = 1.

A Privileged Instruction type Program interruptis generated when execution is attempted of aprivileged instruction, or of an mtspr ormfspr instruction with an SPR field that con-tains one of the defined values having spr0=1.It may be generated when execution isattempted of an mtspr or mfspr instructionwith an SPR field that does not contain one ofthe defined values but has spr0=1, or whenexecution is attempted of an mftb instructionwith a TBR field that does not contain one ofthe defined values but has tbr0=1.

The following applies if the instruction is executedwhen MSRHV PR = 0b00.

A Privileged Instruction type Program interruptmay be generated when execution isattempted of an mtspr instruction with anSPR field that designates a hypervisorresource, or when execution of a tlbie or tlb-sync instruction is attempted.

Trap

A Trap type Program interrupt is generated whenany of the conditions specified in a Trap instructionis met.


SRR0 For all Program interrupts except a Floating-Point Enabled Exception type Program inter-rupt, set to the effective address of the instruc-tion that caused the corresponding exception.

For a Floating-Point Enabled Exception typeProgram interrupt, set as described in the fol-lowing list.- If MSRFE0 FE1 = 0b00, FPSCRFEX = 1,

and an instruction is executed thatchanges MSRFE0 FE1 to a nonzero value,set to the effective address of the instruc-tion that the processor would haveattempted to execute next if no interruptconditions were present.

- If MSRFE0 FE = 0b11, set to the effectiveaddress of the instruction that caused theFloating-Point Enabled Exception.

- If MSRFE0 FE = 0b01 or 0b10, set to theeffective address of the first instructionthat caused a Floating-Point EnabledException since the most recent time

These are the only cases in which a Privi-leged Instruction type Program interruptcan be generated when MSRPR=0. Theycan be distinguished from other causes ofPrivileged Instruction type Program inter-rupts by examining SRR149 (the bit inwhich MSRPR was saved by the interrupt).

Recall that all instructions that can alterMSRFE0 FE1 are context synchroniz-ing, and therefore are not initiated untilall preceding instructions have reportedall exceptions they will cause.

Programming Note

Programming Note


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FPSCRFEX was changed from 1 to 0 or ofsome subsequent instruction.

SRR133:36 Set to 0.42 Set to 0.43 Set to 1 for a Floating-Point Enabled

Exception type Program interrupt; other-wise set to 0.

44 Set to 1 for an Illegal Instruction type Pro-gram interrupt; otherwise set to 0.

45 Set to 1 for a Privileged Instruction typeProgram interrupt; otherwise set to 0.

46 Set to 1 for a Trap type Program interrupt;otherwise set to 0.

47 Set to 0 if SRR0 contains the address ofthe instruction causing the exception andthere is only one such instruction; other-wise set to 1.


Only one of bits 43:46 can be set to 1.



5.5.10 Floating-Point Unavailable Interrupt

A Floating-Point Unavailable interrupt occurs when nohigher priority exception exists, an attempt is made toexecute a floating-point instruction (including floating-point loads, stores, and moves), and MSRFP=0.






5.5.11 Decrementer Interrupt

A Decrementer interrupt occurs when no higher priorityexception exists, a Decrementer exception exists, andMSREE=1.






5.5.12 Hypervisor Decrementer Interrupt

A Hypervisor Decrementer interrupt occurs when nohigher priority exception exists, a Hypervisor Decre-menter exception exists, and the value of the followingexpression is 1.

(MSREE | ¬(MSRHV) | MSRPR) & HDICE


HSRR0 Set to the effective address of the instruc-tion that the processor would haveattempted to execute next if no interruptconditions were present.

If SRR0 is set to the effective addressof a subsequent instruction, thatinstruction will not be beyond the firstsuch instruction at which synchroniza-tion of floating-point instructionsoccurs. (Recall that such synchroniza-tion is caused by Floating-Point Statusand Control Register instructions, aswell as by execution synchronizinginstructions and events.)

SRR147 can be set to 1 only if theexception is a Floating-Point EnabledException and either MSRFE0 FE1 =0b01 or 0b10 or MSRFE0 FE1 has justbeen changed from 0b00 to a nonzerovalue. (SRR147 is always set to 1 inthe last case.)

Programming Note

Programming Note

On processors prior to POWER4+, the occurrenceof the interrupt caused the exception to cease toexist.

Programming Note


Version 2.02

HSRR133:36 Set to 0.42:47 Set to 0.Others Loaded from the MSR.



5.5.13 System Call Interrupt

A System Call interrupt occurs when a System Callinstruction is executed.


SRR0 Set to the effective address of the instruc-tion following the System Call instruction.



Execution resumes at effective address0x0000_0000_0000_0C00.

5.5.14 Trace Interrupt

A Trace interrupt occurs when no higher priority excep-tion exists and either MSRSE=1 and any instructionexcept rfid or hrifd, is successfully completed, orMSRBE=1 and a Branch instruction is completed. Suc-cessful completion means that the instruction causedno other interrupt. Thus a Trace interrupt never occursfor a System Call instruction, or for a Trap instruction

that traps. The instruction that causes a Trace interruptis called the “traced instruction”.

When a Trace interrupt occurs, the following registersare set:


SRR133:36 and 42:47 See the Book IV, PowerPC Imple-

mentation Features document for theimplementation.



Execution resumes at effective address0x0000_0000_0000_0D00.

Extensions to the Trace facility are described inAppendix F, “Example Trace Extensions (Optional)” onpage 117.

5.5.15 Performance MonitorInterrupt (Optional)

The Performance Monitor interrupt is part of theoptional Performance Monitor facility; see Appendix E.If the Performance Monitor facility is not implementedor does not use this interrupt, the corresponding inter-rupt vector (see Figure 36 on page 65) is treated asreserved.

5.6 Partially ExecutedInstructionsIf a Data Storage, Data Segment, Alignment, system-caused, or imprecise exception occurs while a Load orStore instruction is executing, the instruction may beaborted. In such cases the instruction is not completed,

Because the value of MSREE is always 1 when theprocessor is in problem state, the simpler expres-sion

(MSREE | ¬(MSRHV)) & HDICE

is equivalent to the expression given above.

On processors prior to POWER4+, the HypervisorDecrementer was not implemented.

An attempt to execute an sc instruction with LEV=1in problem state should be treated as a program-ming error.

Programming Note

Programming Note

Programming Note

The following instructions are not traced.

� rfid � hrfid � sc, and Trap instructions that trap� other instructions that cause interrupts (other

than Trace interrupts)� the first instructions of any interrupt handler� instructions that are emulated by software

In general, interrupt handlers can achieve the effectof tracing these instructions.

Programming Note


Version 2.02

but may have been partially executed in the followingrespects.

� Some of the bytes of the storage operand mayhave been accessed, except that if access to agiven byte of the storage operand would violatestorage protection, that byte is neither copied to aregister by a Load instruction nor modified by aStore instruction. Also, the rules for storageaccesses given in Section 4.2.4.1, “Guarded Stor-age” on page 28 and in the section entitled“Instruction Restart” in Book II are obeyed.

� Some registers may have been altered asdescribed in the Book II section cited above.

� Reference and Change bits may have beenupdated as described in Section 4.9.

� For a stwcx. or stdcx. instruction that is executedin-order, CR0 may have been set to an undefinedvalue and the reservation may have been cleared.

The architecture does not support continuation of anaborted instruction but intends that the aborted instruc-tion be re-executed if appropriate.

5.7 Exception OrderingSince multiple exceptions can exist at the same timeand the architecture does not provide for reportingmore than one interrupt at a time, the generation ofmore than one interrupt is prohibited. Some excep-tions, such as the External exception, persist and canbe deferred. However, other exceptions would be lost if

they were not recognized and handled when theyoccur. For example, if an External interrupt was gener-ated when a Data Storage exception existed, the DataStorage exception would be lost. If the Data Storageexception was caused by a Store Multiple instructionfor which the storage operand crosses a virtual pageboundary and the exception was a result of attemptingto access the second virtual page, the store could havemodified locations in the first virtual page even though itappeared that the Store Multiple instruction was neverexecuted.

For the above reasons, all exceptions are prioritizedwith respect to other exceptions that may exist at thesame instant to prevent the loss of any exception that isnot persistent. Some exceptions cannot exist at thesame instant as some others.

Data Storage, Data Segment, and Alignment excep-tions occur as if the storage operand were accessedone byte at a time in order of increasing effectiveaddress (with the obvious caveat if the operandincludes both the maximum effective address andeffective address 0).

5.7.1 Unordered Exceptions

The exceptions listed here are unordered, meaning thatthey may occur at any time regardless of the state ofthe interrupt processing mechanism. These exceptionsare recognized and processed when presented.

1. System Reset

2. Machine Check

5.7.2 Ordered Exceptions

The exceptions listed here are ordered with respect tothe state of the interrupt processing mechanism.

System-Caused or Imprecise

1. Program - Imprecise Mode Floating-Point Enabled Exception2. External, Decrementer, and Hypervisor Decrementer

Instruction-Caused and Precise

1. Instruction Segment2. Instruction Storage3. Program - Illegal Instruction - Privileged Instruction4. Function-Dependent 4.a Fixed-Point and Branch 1a Program - Trap

An exception may result in the partial execution ofa Load or Store instruction. For example, if thePage Table Entry that translates the address of thestorage operand is altered, by a program runningon another processor, such that the new contentsof the Page Table Entry preclude performing theaccess, the alteration could cause the Load orStore instruction to be aborted after having beenpartially executed.

As stated in the Book II section cited above, if aninstruction is partially executed the contents of reg-isters are preserved to the extent that the instruc-tion can be re-executed correctly. The consequentpreservation is described in the following list. Forany given instruction, zero or one item in the listapplies.

� For a fixed-point Load instruction that is not amultiple or string form, or for an eciwx instruc-tion, if RT = RA or RT = RB then the contentsof register RT are not altered.

� For an update form Load or Store instruction,the contents of register RA are not altered.

Programming Note


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1b System Call 1c Data Storage, Data Segment, or Alignment 2 Trace 4.b Floating-Point 1 FP Unavailable 2a Program - Precise Mode Floating-Pt Enabled Excep’n 2b Data Storage, Data Segment, or Alignment 3 Trace

For implementations that execute multiple instruc-tions in parallel using pipeline or superscalar tech-niques, or combinations of these, it can be difficult tounderstand the ordering of exceptions. To under-stand this ordering it is useful to consider a model inwhich each instruction is fetched, then decoded, thenexecuted, all before the next instruction is fetched.In this model, the exceptions a single instruction wouldgenerate are in the order shown in the list of instruc-tion-caused exceptions. Exceptions with differentnumbers have different ordering. Exceptions with thesame numbering but different lettering are mutuallyexclusive and cannot be caused by the same instruc-tion. The External, Decrementer, and HypervisorDecrementer interrupts have equal ordering. Simi-larly, where Data Storage, Data Segment, and Align-ment exceptions are listed in the same item they haveequal ordering.

Even on processors that are capable of executing sev-eral instructions simultaneously, or out of order,instruction-caused interrupts (precise and imprecise)occur in program order.


Version 2.02

5.8 Interrupt PrioritiesThis section describes the relationship of non-maskable, maskable, precise, and imprecise interrupts.In the following descriptions, the interrupt mechanismwaiting for all possible exceptions to be reportedincludes only exceptions caused by previously initiatedinstructions (e.g., it does not include waiting for theDecrementer to step through zero). The exceptionsare listed in order of highest to lowest priority.

1. System Reset

System Reset exception has the highest priority ofall exceptions. If this exception exists, the inter-rupt mechanism ignores all other exceptions andgenerates a System Reset interrupt.

Once the System Reset interrupt is generated,no nonmaskable interrupts are generated due toexceptions caused by instructions issued prior tothe generation of this interrupt.

2. Machine Check

Machine Check exception is the second highestpriority exception. If this exception exists and aSystem Reset exception does not exist, theinterrupt mechanism ignores all other exceptionsand generates a Machine Check interrupt.

Once the Machine Check interrupt is generated,no nonmaskable interrupts are generated due toexceptions caused by instructions issued prior tothe generation of this interrupt.

3. Instruction-Dependent

This exception is the third highest priority excep-tion. When this exception is created, the inter-rupt mechanism waits for all possible Impreciseexceptions to be reported. It then generates theappropriate ordered interrupt if no higher priorityexception exists when the interrupt is to begenerated. Within this category a particularinstruction may present more than a singleexception. When this occurs, those exceptionsare ordered in priority as indicated in the followinglists. Where Data Storage, Data Segment, andAlignment exceptions are listed in the same itemthey have equal priority (i.e., the processor maygenerate any one of the three interrupts for whichan exception exists).

A. Fixed-Point Loads and Stores

a.Program - Illegal Instructionb.Data Storage, Data Segment, or Alignmentc. Trace

B. Floating-Point Loads and Stores

a.Program - Illegal Instructionb.Floating-Point Unavailablec. Data Storage, Data Segment, or Alignment

d.Trace

C. Other Floating-Point Instructions

a.Floating-Point Unavailableb.Program - Precise Mode Floating-Point

Enabled Exceptionc. Trace

D. rfid, hrfid and mtmsr[d]

a.Program - Privileged Instructionb.Program - Floating-Point Enabled Exceptionc. Trace, for mtmsr[d] only

E. Other Instructions a.These exceptions are mutually exclusive

and have the same priority:� Program - Trap� System Call� Program - Privileged Instruction� Program - Illegal Instruction

b.Trace

F. Instruction Storage and Instruction Segment

These exceptions have the lowest priority inthis category. They are recognized only whenall instructions prior to the instruction caus-ing one of these exceptions appear to havecompleted and that instruction is the nextinstruction to be executed. The two excep-tions are mutually exclusive.

The priority of these exceptions is specified forcompleteness and to ensure that they arenot given more favorable treatment. It isacceptable for an implementation to treatthese exceptions as though they had a lowerpriority.

4. Program - Imprecise Mode Floating-Point EnabledException

This exception is the fourth highest priority excep-tion. When this exception is created, the interruptmechanism waits for all other possible exceptionsto be reported. It then generates this interrupt if nohigher priority exception exists when the interruptis to be generated.

5. External, Decrementer, and Hypervisor Decre-menter

These exceptions are the lowest priority excep-tions. All have equal priority (i.e., the processormay generate any one of these interrupts for whichan exception exists). When one of these excep-tions is created, the interrupt processing mecha-nism waits for all other possible exceptions to bereported. It then generates the correspondinginterrupt if no higher priority exception exists whenthe interrupt is to be generated.


Version 2.02

If a Hypervisor Decrementer exception exists andthe Hypervisor Decrementer interrupt is enabled,and each attempt to execute an instruction causesan exception (see the Programming Note below),the Hypervisor Decrementer interrupt is notdelayed indefinitely.

An incorrect or malicious operating systemcould corrupt the first instruction in theinterrupt vector location for an instruction-caused interrupt such that the attempt to exe-cute the instruction causes the same excep-tion that caused the interrupt (a loopinginterrupt; e.g., illegal instruction and Programinterrupt). Similarly, the first instruction of theinterrupt vector for one instruction-causedinterrupt could cause a different instruction-caused interrupt, and the first instruction ofthe interrupt vector for the secondinstruction-caused interrupt could causethe first instruction-caused interrupt (e.g.,Program interrupt and Floating-PointUnavailable interrupt). The looping caused bythese and similar cases is terminated by theoccurrence of a System Reset or HypervisorDecrementer interrupt.

Programming Note


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Chapter 6. Timer Facilities

6.1 Overview. . . . . . . . . . . . . . . . . . . . . 796.2 Time Base. . . . . . . . . . . . . . . . . . . . 796.2.1 Writing the Time Base . . . . . . . . . 806.3 Decrementer . . . . . . . . . . . . . . . . . . 806.3.1 Writing and Reading the Decre-

menter . . . . . . . . . . . . . . . . . . . . . . . . . . 81

6.4 Hypervisor Decrementer . . . . . . . . . 816.5 Processor Utilization of Resources

Register (PURR) . . . . . . . . . . . . . . . . . . 82

6.1 OverviewThe Time Base, Decrementer, Hypervisor Decre-menter, and the Processor Utilization of Resources reg-isters provide timing functions for the system. All arevolatile resources and must be initialized during star-tup. The mftb instruction is used to read the TimeBase; the mtspr and mfspr instructions are used towrite the Time Base and Decrementer(s) and to readthe Decrementer(s).

Time Base (TB)

The Time Base provides a long-period counterdriven by an implementation-dependent frequency.

Decrementer (DEC)

The Decrementer, a counter that is updated at thesame rate as the Time Base, provides a means ofsignaling an interrupt after a specified amount oftime has elapsed unless

� the Decrementer is altered by software in theinterim, or

� the Time Base update frequency changes.

Hypervisor Decrementer (HDEC)

The Hypervisor Decrementer provides a means forthe hypervisor to manage timing functions inde-pendently of the Decrementer, which is managedby virtual partitions. Similar to the Decrementer,the HDEC is a counter that is updated at the samerate as the Time Base, and it provides a means ofsignaling an interrupt after a specified amount oftime has elapsed. Software must have hypervisorprivilege to update the HDEC.

6.2 Time BaseThe Time Base (TB) is a 64-bit register (see Figure 37)containing a 64-bit unsigned integer that is incrementedperiodically. Each increment adds 1 to the low-order bit(bit 63). The frequency at which the integer is updatedis implementation-dependent.

Figure 37. Time Base

The Time Base is a hypervisor resource; seeSection 1.7, “Logical Partitioning (LPAR)” on page 5.

The Time Base increments until its value becomes0xFFFF_FFFF_FFFF_FFFF (264 - 1). At the nextincrement, its value becomes0x0000_0000_0000_0000. There is no interrupt orother indication when this occurs.

The period of the Time Base depends on the drivingfrequency. As an order of magnitude example, sup-pose that the CPU clock is 1 GHz and that the TimeBase is driven by this frequency divided by 32. Thenthe period of the Time Base would be

TTB = = 5.90 � 1011 seconds

TBU TBL0 32 63

Field DescriptionTBU Upper 32 bits of Time BaseTBL Lower 32 bits of Time Base

264 32×1 GHz

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which is approximately 18,700 years.

The Time Base is implemented such that:

1. Loading a GPR from the Time Base has no effecton the accuracy of the Time Base.

2. Copying the contents of a GPR to the Time Basereplaces the contents of the Time Base with thecontents of the GPR.

The PowerPC Architecture does not specify a relation-ship between the frequency at which the Time Base isupdated and other frequencies, such as the CPU clockor bus clock in a PowerPC system. The Time Baseupdate frequency is not required to be constant. Whatis required, so that system software can keep time ofday and operate interval timers, is one of the following.

� The system provides an (implementation-depen-dent) interrupt to software whenever the updatefrequency of the Time Base changes, and a meansto determine what the current update frequency is.

� The update frequency of the Time Base is underthe control of the system software.

Implementations must provide a means for either pre-venting the Time Base from incrementing or preventingit from being read in problem state (MSRPR=1). If themeans is under software control, it must be accessibleonly in hypervisor state (MSRHV PR = 0b10). Theremust be a method for getting all processors’ TimeBases to start incrementing with values that are identi-cal or almost identical in all processors.

6.2.1 Writing the Time Base

Writing the Time Base is privileged, and can be doneonly in hypervisor state. Reading the Time Base is notprivileged; it is discussed in Book II, PowerPC VirtualEnvironment Architecture.

It is not possible to write the entire 64-bit Time Baseusing a single instruction. The mttbl and mttbuextended mnemonics write the lower and upper halvesof the Time Base (TBL and TBU), respectively, preserv-ing the other half. These are extended mnemonics forthe mtspr instruction; see page 98.

The Time Base can be written by a sequence such as:

lwz Rx,upper # load 64-bit value forlwz Ry,lower # TB into Rx and Ryli Rz,0mttbl Rz # set TBL to 0mttbu Rx # set TBUmttbl Ry # set TBL

Provided that no interrupts occur while the last threeinstructions are being executed, loading 0 into TBL pre-vents the possibility of a carry from TBL to TBU whilethe Time Base is being initialized.

6.3 DecrementerThe Decrementer (DEC) is a 32-bit decrementingcounter that provides a mechanism for causing a Dec-rementer interrupt after a programmable delay. Thecontents of the Decrementer are treated as a signedinteger.

Figure 38. Decrementer

The Decrementer is driven by the same frequency asthe Time Base. The period of the Decrementer willdepend on the driving frequency, but if the same valuesare used as given above for the Time Base (see Sec-tion 6.2), and if the Time Base update frequency is con-stant, the period would be

TDEC = = 137 seconds.

If the hypervisor initializes the Time Base onpower-on to some reasonable value and theupdate frequency of the Time Base is constant, theTime Base can be used as a source of values thatincrease at a constant rate, such as for time stampsin trace entries.

Even if the update frequency is not constant, val-ues read from the Time Base are monotonicallyincreasing (except when the Time Base wraps from264-1 to 0). If a trace entry is recorded each timethe update frequency changes, the sequence ofTime Base values can be post-processed tobecome actual time values.

Successive readings of the Time Base may returnidentical values.

See the description of the Time Base in Book II,PowerPC Virtual Environment Architecture forways to compute time of day in POSIX format fromthe Time Base.

Programming Note

The instructions for writing the Time Base aremode-independent. Thus code written to set theTime Base will work correctly in either 64-bit or 32-bit mode.

DEC0 31

Programming Note

232 32×1 GHz

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The Decrementer counts down.

The exception effects of the Decrementer are said tobe consistent with the contents of the Decrementer ifone of the following statements is true.

� DEC0=0 and a Decrementer exception does notexist.

� DEC0=1 and a Decrementer exception exists.

If DEC0=0, a context synchronizing instruction or eventensures that the exception effects of the Decrementerare consistent with the contents of the Decrementer.Otherwise, when the contents of DEC0 change, theexception effects of the Decrementer become consis-tent with the new contents of the Decrementer reason-ably soon after the change.

The preceding paragraph applies regardless of whetherthe change in the contents of DEC0 is the result of dec-rementation of the Decrementer by the processor or ofmodification of the Decrementer caused by executionof an mtspr instruction.

The operation of the Decrementer satisfies the follow-ing constraints.

1. The operation of the Time Base and the Decre-menter is coherent, i.e., the counters are driven bythe same fundamental time base.

2. Loading a GPR from the Decrementer has noeffect on the accuracy of the Time Base.

3. Copying the contents of a GPR to the Decrementerreplaces the contents of the Decrementer with thecontents of the GPR.

6.3.1 Writing and Reading the Decrementer

The contents of the Decrementer can be read or writtenusing the mfspr and mtspr instructions, both of whichare privileged when they refer to the Decrementer.

Using an extended mnemonic (see page 98), the Dec-rementer can be written from GPR Rx using:

mtdec Rx

The Decrementer can be read into GPR Rx using:

mfdec Rx

Copying the Decrementer to a GPR has no effect onthe Decrementer contents or on the interrupt mecha-nism.

6.4 Hypervisor Decrementer The Hypervisor Decrementer (HDEC) is a 32-bit decre-menting counter that provides a mechanism for causinga Hypervisor Decrementer interrupt after a programma-ble delay. The contents of the Decrementer are treatedas a signed integer.

Figure 39. Hypervisor Decrementer

The Hypervisor Decrementer is a hypervisor resource;see Section 1.7, “Logical Partitioning (LPAR)” onpage 5.

The Hypervisor Decrementer is driven by the same fre-quency as the Time Base. The period of the Hypervi-sor Decrementer will depend on the driving frequency,but if the same values are used as given above for theTime Base (see Section 6.2), and if the Time Baseupdate frequency is constant, the period would be

TDEC = = 137 seconds.

The exception effects of the Hypervisor Decrementerare said to be consistent with the contents of the Hyper-visor Decrementer if one of the following statements istrue.

� HDEC0=0 and a Hypervisor Decrementer excep-tion does not exist.

� HDEC0=1 and a Hypervisor Decrementer excep-tion exists.

If HDEC0=0, a context synchronizing instruction orevent ensures that the exception effects of the Hypervi-

On processors prior to POWER4+, the Decre-menter exception was hidden state that wascleared when the Decrementer interrupt was taken.

In systems that change the Time Base update fre-quency for purposes such as power management,the Decrementer input frequency will also change.Software must be aware of this in order to set inter-val timers.

Programming Note

Programming Note

On processors prior to POWER4+, if the executionof the mtdec instruction causes bit 0 of the Decre-menter to change from 0 to 1, an interrupt requestis signaled.

HDEC0 31

Programming Note

232 32×1 GHz

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sor Decrementer are consistent with the contents of theHypervisor Decrementer. Otherwise, when the contentsof HDEC0 change, the exception effects of the Hypervi-sor Decrementer become consistent with the new con-tents of the Hypervisor Decrementer reasonably soonafter the change.

The preceding paragraph applies regardless of whetherthe change in the contents of HDEC0 is the result ofdecrementation of the Hypervisor Decrementer by theprocessor or of modification of the Hypervisor Decre-menter caused by execution of an mtspr instruction.

The operation of the Hypervisor Decrementer satisfiesthe following constraints.

1. The operation of the Time Base and the Hypervi-sor Decrementer is coherent, i.e., the counters aredriven by the same fundamental time base.

2. Loading a GPR from the Hypervisor Decrementerhas no effect on the accuracy of the HypervisorDecrementer.

3. Copying the contents of a GPR to the HypervisorDecrementer replaces the contents of the Hypervi-sor Decrementer with the contents of the GPR.

6.5 Processor Utilization of Resources Register (PURR)The Processor Utilization of Resources Register(PURR) is a 64-bit counter, the contents of which pro-vide an estimate of the resources used by the proces-sor. The contents of the PURR are treated as a 64-bitunsigned integer.

Figure 40. Processor Utilization of ResourcesRegister

The PURR is a hypervisor resource; see Section 1.7,Logical Partitioning (LPAR) on p. 4.

The contents of the PURR increase monotonically,unless altered by software, until the sum of the con-tents plus the amount by which it is to be increasedexceed 0xFFFF_FFFF_FFFF_FFFF (264 - 1) at whichpoint the contents are replaced by that sum modulo264. There is no interrupt or other indication when thisoccurs.

The rate at which the value represented by the con-tents of the PURR increases is an estimate of the por-tion of resources used by the processor with respect toother processors that share those resources monitoredby the PURR.

Let the difference between the value represented bythe contents of the Time Base at times Ta and Tb beTab. Let the difference between the value representedby the contents of the PURR at time Ta and Tb be thevalue Pab. The ratio of Pab/Tab is an estimate of the per-centage of shared resources used by the processorduring the interval Tab. For the set {S} of processorsthat share the resources monitored by the PURR, thesum of the usage estimates for all the processors in theset is 1.0.

The definition of the set of processors S, the sharedresources corresponding to the set S, and specifics ofthe algorithm for incrementing the PURR are imple-mentation-specific. See Book IV, PowerPC Implemen-tation Features for details on each implementation.

The PURR is implemented such that:

1. Loading a GPR from the PURR has no effect onthe accuracy of the PURR.

2. Copying the contents of a GPR to the PURRreplaces the contents of the PURR with the con-tents of the GPR.

In systems that change the Time Base update fre-quency for purposes such as power management,the Hypervisor Decrementer update frequency willalso change. Software must be aware of this inorder to set interval timers.

Programming Note

PURR0 63


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Estimates computed as described above may beuseful for purposes of resource use accounting,program dispatching, etc.

Because the rate at which the PURR accumulatesresource usage estimates is dependent on the fre-quency at which the Time Base is incremented, theinterpretation of the contents of the PURR must beadjusted if the frequency at which the Time Base isincremented is altered.

Programming Note


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Chapter 7. Synchronization Requirements for Context Alterations

Changing the contents of certain System Registers andof SLB entries and Page Table Entries, and invalidatingSLB and TLB entries, can have the side effect of alter-ing the context in which data addresses and instructionaddresses are interpreted, and in which instructions areexecuted and data accesses are performed. For exam-ple, changing MSRIR from 0 to 1 has the side effect ofenabling translation of instruction addresses. Theseside effects need not occur in program order, andtherefore may require explicit synchronization by soft-ware. (Program order is defined in Book II, PowerPCVirtual Environment Architecture.)

An instruction that alters the context in which dataaddresses or instruction addresses are interpreted, orin which instructions are executed or data accesses areperformed, is called a context-altering instruction. Thischapter covers all the context-altering instructions. Thesoftware synchronization required for them is shown inTable 1 (for data access) and Table 2 (for instructionfetch and execution).

The notation “CSI” in the tables means any contextsynchronizing instruction (e.g., sc, isync, or rfid). Acontext synchronizing interrupt (i.e., any interruptexcept non-recoverable System Reset or non-recover-able Machine Check) can be used instead of a contextsynchronizing instruction. If it is, phrases like “the syn-chronizing instruction”, below, should be interpreted asmeaning the instruction at which the interrupt occurs. Ifno software synchronization is required before (after) acontext-altering instruction, “the synchronizing instruc-tion before (after) the context-altering instruction”should be interpreted as meaning the context-alteringinstruction itself.

The synchronizing instruction before the context-alter-ing instruction ensures that all instructions up to andincluding that synchronizing instruction are fetched andexecuted in the context that existed before the alter-ation. The synchronizing instruction after the context-altering instruction ensures that all instructions afterthat synchronizing instruction are fetched and executedin the context established by the alteration. Instructionsafter the first synchronizing instruction, up to andincluding the second synchronizing instruction, may befetched or executed in either context.

If a sequence of instructions contains context-alteringinstructions and contains no instructions that areaffected by any of the context alterations, no softwaresynchronization is required within the sequence.

No software synchronization is required before or aftera context-altering instruction that is also context syn-chronizing (e.g., rfid, mtmsr[d] with L=0), except per-haps when altering the LE bit (see the tables). Nosoftware synchronization is required before most of theother alterations shown in Table 2, because all instruc-tions preceding the context-altering instruction arefetched and decoded before the context-alteringinstruction is executed (the processor must determinewhether any of these preceding instructions are contextsynchronizing).

Unless otherwise stated, the material in this chapterassumes a uniprocessor environment.

Sometimes advantage can be taken of the fact thatcertain events, such as interrupts, and certaininstructions that occur naturally in the program,such as the rfid that returns from an interrupt han-dler, provide the required synchronization.

Programming Note

Chapter 7. Synchronization Requirements for Context Alterations 85

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Notes:

1. Synchronization requirements for changing fromone Endian mode to the other using the mtmsr[d] instruction are implementation-depen-dent, and are specified in the Book IV, PowerPCImplementation Features document for the imple-mentation.

2. The effect of changing the EE bit is immediate,even if the mtmsr[d] instruction is not context syn-chronizing (i.e., even if L=1).

� If an mtmsr[d] instruction sets the EE bit to 0,neither an External interrupt nor a Decre-menter interrupt occurs after the mtmsr[d] isexecuted.

� If an mtmsr[d] instruction changes the EE bitfrom 0 to 1 when an External, Decrementer, orhigher priority exception exists, the corre-sponding interrupt occurs immediately after

the mtmsr[d] is executed, and before the nextinstruction is executed in the program that setEE to 1.

� If a hypervisor executes the mtmsr[d] instruc-tion that sets the EE bit to 0, a HypervisorDecrementer interrupt does not occur aftermtmsr[d] is executed as long as the proces-sor remains in hypervisor state.

� If the hypervisor executes an mtmsr[d]instruction that changes the EE bit from 0 to 1when a Hypervisor Decrementer or higher pri-ority exception exists, the corresponding inter-rupt occurs immediately after the mtmsr[d]instruction is executed, and before the nextinstruction is executed, provided HDICE is 1.

3. For software that will run on processors that com-ply with versions of the architecture that precedeVersion 2.01, a context synchronizing instruction is

Instruction or Event

Required Before

Required After

Notes

interrupt none nonerfid none nonehrfid none nonesc none noneTrap none nonemtmsrd (SF) none none 3mtmsr[d] (PR) none none 3mtmsr[d] (DR) none none 3mtmsr[d] (LE) -- -- 1, 3mtsr[in] CSI CSImtspr (ACCR) CSI CSImtspr (SDR1) ptesync CSI 5, 6mtspr (DABR) -- -- 4mtspr (DABRX) -- -- 4mtspr (EAR) CSI CSImtspr (RMOR) CSI CSI 15mtspr (HRMOR) CSI CSI 15mtspr (LPCR) CSI CSI 15slbie CSI CSIslbia CSI CSIslbmte CSI CSI 13tlbie CSI CSI 7, 9tlbiel CSI ptesync 7 tlbia CSI CSI 7Store(PTE) none {ptesync, CSI} 8, 9

Table 1: Synchronization requirements for data access

Instruction or Event

Required Before

Required After

Notes

interrupt none nonerfid none nonehrfid none nonesc none noneTrap none nonemtmsrd (SF) none none 3, 10mtmsr[d] (EE) none none 2, 3mtmsr[d] (PR) none none 3, 11mtmsr[d] (FP) none none 3mtmsr[d](FE0,FE1) none none 3mtmsr[d] (SE, BE) none none 3mtmsr[d] (IR) none none 3, 11mtmsr[d] (RI) none none 3mtmsr[d] (LE) -- -- 1, 3mtsr[in] none CSI 11mtspr (SDR1) ptesync CSI 5, 6mtspr (DEC) none none 12mtspr (HDEC) none none 12mtspr (LPIDR) CSI CSI 9, 14mtspr (CTRL) none nonemtspr (RMOR) none CSI 15mtspr (HRMOR) none CSI 11,15mtspr (LPCR) none CSI 15slbie none CSIslbia none CSIslbmte none CSI 11, 13tlbie none CSI 7, 9tlbiel none CSI 7 tlbia none CSI 7Store(PTE) none {ptesync, CSI} 8, 9

Table 2: Synchronization requirements for instruction fetch and/or execution


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required after the mtmsr[d] instruction; see thefirst Programming Note in the descriptions of theseinstructions on pages 22 and 91.

4. Synchronization requirements for changing theDABR and DABRX are implementation-depen-dent, and are specified in the Book IV, PowerPCImplementation Features document for the imple-mentation.

5. SDR1 must not be altered when MSRDR=1 orMSRIR=1; if it is, the results are undefined.

6. A ptesync instruction is required before the mtsprinstruction because (a) SDR1 identifies the PageTable and thereby the location of Reference andChange bits, and (b) on some implementations,use of SDR1 to update Reference and Change bitsmay be independent of translating the virtualaddress. (For example, an implementation mightidentify the PTE in which to update the Referenceand Change bits in terms of its offset in the PageTable, instead of its real address, and then add thePage Table address from SDR1 to the offset todetermine the real address at which to update thebits.) To ensure that Reference and Change bitsare updated in the correct Page Table, SDR1 mustnot be altered until all Reference and Change bitsare updated in the correct Page Table, SDR1 mustnot be altered until all Reference and Change bitupdates associated with address translations thatwere performed, by the processor executing themtspr instruction, before the mtspr instruction isexecuted have been performed with respect to thatprocessor. A ptesync instruction guarantees thissynchronization of Reference and Change bitupdates, while neither a context synchronizingoperation nor the instruction fetching mechanismdoes so.

7. For data accesses, the context synchronizinginstruction before the tlbie, tlbiel, or tlbia instruc-tion ensures that all preceding instructions thataccess data storage have completed to a point atwhich they have reported all exceptions they willcause.

The context synchronizing instruction after thetlbie, tlbiel, or tlbia instruction ensures that stor-age accesses associated with instructions follow-ing the context synchronizing instruction will notuse the TLB entry(s) being invalidated.

(If it is necessary to order storage accesses asso-ciated with preceding instructions, or Referenceand Change bit updates associated with precedingaddress translations, with respect to subsequentdata accesses, a ptesync instruction must also beused, either before or after the tlbie, tlbiel, or tlbiainstruction. These effects of the ptesync instruc-tion are described in the last paragraph of Note 8.)

8. The notation “{ptesync,CSI}” denotes an instruc-tion sequence. Other instructions may be inter-

leaved with this sequence, but these instructionsmust appear in the order shown.

No software synchronization is required before theStore instruction because (a) stores are not per-formed out-of-order and (b) address translationsassociated with instructions preceding the Storeinstruction are not performed again after the storehas been performed (see Section 4.2.4). Theseproperties ensure that all address translationsassociated with instructions preceding the Storeinstruction will be performed using the old contentsof the PTE.

The ptesync instruction after the Store instructionensures that all searches of the Page Table thatare performed after the ptesync instruction com-pletes will use the value stored (or a value storedsubsequently). The context synchronizing instruc-tion after the ptesync instruction ensures that anyaddress translations associated with instructionsfollowing the context synchronizing instruction thatwere performed using the old contents of the PTEwill be discarded, with the result that theseaddress translations will be performed again and, ifthere is no corresponding TLB entry, will use thevalue stored (or a value stored subsequently).

The ptesync instruction also ensures that all stor-age accesses associated with instructions preced-ing the ptesync instruction, and all Reference andChange bit updates associated with additionaladdress translations that were performed, by theprocessor executing the ptesync instruction,before the ptesync instruction is executed, will beperformed with respect to any processor or mech-anism, to the extent required by the associatedMemory Coherence Required attributes, beforeany data accesses caused by instructions follow-ing the ptesync instruction are performed withrespect to that processor or mechanism.

9. There are additional software synchronizationrequirements for the tlbie instruction in multipro-cessor environments; see Section 4.12, “PageTable Update Synchronization Requirements” onpage 57.

Section 4.12 also gives examples of using tlbie,Store, and related instructions to maintain thePage Table, in both multiprocessor and uniproces-sor environments.

Chapter 7. Synchronization Requirements for Context Alterations 87

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10. The alteration must not cause an implicit branch ineffective address space. Thus, when changingMSRSF from 1 to 0, the mtmsrd instruction musthave an effective address that is less than 232 - 4.Furthermore, when changing MSRSF from 0 to 1,the mtmsrd instruction must not be at effectiveaddress 232 - 4 (see Section 4.2.2.2 on page 27).

11. The alteration must not cause an implicit branch inreal address space. Thus the real address of thecontext-altering instruction and of each subse-quent instruction, up to and including the next con-text synchronizing instruction, must beindependent of whether the alteration has takeneffect.

12. The elapsed time between the contents of the Dec-rementer or Hypervisor Decrementer becomingnegative and the signaling of the correspondingexception is not defined.

13. If an slbmte instruction alters the mapping, orassociated attributes, of a currently mapped ESID,the slbmte must be preceded by an slbie (orslbia) instruction that invalidates the existingtranslation. This applies even if the correspondingentry is no longer in the SLB (the translation maystill be in implementation-specific address transla-tion lookaside information). No software synchro-nization is needed between the slbie and theslbmte, regardless of whether the index of theSLB entry (if any) containing the current translationis the same as the SLB index specified by the slb-mte.

No slbie (or slbia) is needed if the slbmte instruc-tion replaces a valid SLB entry with a mapping of adifferent ESID (e.g., to satisfy an SLB miss). How-ever, the slbie is needed later if and when thetranslation that was contained in the replaced SLBentry is to be invalidated.

14. The context synchronizing instruction before themtspr instruction ensures that the LPIDR is notaltered out-of-order. (Out-of-order alteration of theLPIDR could permit the requirements described inSection 4.12.1 to be violated. For the same rea-son, such a context synchronizing instruction maybe needed even if the new LPID value is equal tothe old LPID value.)

See also Section 1.7, “Logical Partitioning (LPAR)”on page 5 regarding moving a processor from onepartition to another.

15. When the RMOR or HRMOR is modified, or theRMLS, LPES1, or RMI fields of the LPCR are mod-ified, software must invalidate all implementation-specific lookaside information used in addresstranslation that depends on values stored in theseregisters. All implementations provide a means bywhich software can do this.

In a multiprocessor system, if software lockingis used to help ensure that the requirementsdescribed in Section 4.12 are satisfied, theisync instruction near the end of the lockacquisition sequence (see the section entitled“Acquire Lock and Import Shared Storage” inBook II, PowerPC Virtual Environment Archi-tecture) may naturally provide the context syn-chronization that is required before thealteration.

Programming Note


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Chapter 8. Optional Facilities and Instructions

8.1 External Control . . . . . . . . . . . . . . . 898.1.1 External Access Register. . . . . . . 898.1.2 External Access Instructions . . . . 908.2 Real Mode Storage Control . . . . . . 90

8.3 Move to Machine State Register Instruction . . . . . . . . . . . . . . . . . . . . . . . 91

8.4 Fixed-Point Storage Access Instruc-tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

The facilities and instructions described in this chapterare optional. An implementation may provide all, some,or none of them.

8.1 External ControlThe External Control facility permits a program to com-municate with a special-purpose device. The facilityconsists of a Special Purpose Register, called EAR,and two instructions, called External Control In WordIndexed (eciwx) and External Control Out WordIndexed (ecowx).

This facility must provide a means of synchronizing thedevices with the processor to prevent the use of anaddress by the device when the translation that pro-duced that address is being invalidated.

8.1.1 External Access Register

This 32-bit Special Purpose Register controls access tothe External Control facility and, for external controloperations that are permitted, identifies the targetdevice.


Figure 41. External Access Register

The EAR is a hypervisor resource; see Section 1.7,“Logical Partitioning (LPAR)” on page 5.

The high-order bits of the RID field that correspond tobits of the Resource ID beyond the width of theResource ID supported by the implementation aretreated as reserved bits.

E /// RID0 1 26 31

Bit(s) Name Description0 E Enable bit26:31 RID Resource ID

The hypervisor can use the EAR to control whichprograms are allowed to execute External Accessinstructions, when they are allowed to do so, andwhich devices they are allowed to communicatewith using these instructions.

Programming Note

Chapter 8. Optional Facilities and Instructions 89

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8.1.2 External Access Instruc-tions

The External Access instructions, External Control InWord Indexed (eciwx) and External Control Out WordIndexed (ecowx), are described in Book II, PowerPCVirtual Environment Architecture. Additional informa-tion about them is given below.

If attempt is made to execute either of these instruc-tions when EARE=0, a Data Storage interrupt occurswith bit 11 of the DSISR set to 1.

The instructions are supported whenever MSRDR=1. Ifeither instruction is executed when MSRDR=0 (realaddressing mode), the results are boundedly unde-fined.

8.2 Real Mode Storage ControlThe Real Mode Storage Control facility provides ameans of specifying portions of real storage that aretreated as non-Guarded in hypervisor real addressingmode (MSRHV PR=0b10, and MSRIR=0 or MSRDR=0,as appropriate for the type of access). The remainingportions are treated as Guarded in hypervisor realaddressing mode (as is all of storage on implementa-tions that do not provide this means). The means is ahypervisor resource (see Section 1.7, “Logical Parti-tioning (LPAR)” on page 5), and may also be system-specific.

If the Real Mode Caching Inhibited (RMI) bit is set to 1,it is undefined whether a given data access to a storagelocation that is treated as non-Guarded in hypervisorreal addressing mode is treated as Caching Inhibited oras not Caching Inhibited. If the access is treated asCaching Inhibited and is performed out-of-order, theaccess cannot cause a Machine Check or Checkstopto occur out-of-order due to violation of the require-ments given in Section 4.8.2, “Altering the StorageControl Bits” on page 42 for changing the value of theeffective I bit. (Recall that software must ensure thatRMI = 0 when the processor is not in hypervisor realaddressing mode; see Section 4.2.6.3, “Storage Con-trol Attributes for Real Addressing Mode and for ImplicitStorage Accesses” on page 30.)

The facility does not apply to implicit accesses to thePage Table by the processor in performing addresstranslation or in recording reference and change infor-mation. These accesses are performed as describedin Section 4.2.6.3 on page 30.

The preceding capability can be used to improvethe performance of hypervisor software that runs inhypervisor real addressing mode, by causingaccesses to instructions and data that occupy well-behaved storage to be treated as non-Guarded.See also the second paragraph of the Program-ming Note in Section 4.2.6.3.

If RMI=1, the statement in Section 4.2.4, “Perform-ing Operations Out-of-Order” on page 27, that non-Guarded storage locations may be fetched out-of-order into a cache only if they could be fetched intothat cache by in-order execution does not precludethe out-of-order fetching into the data cache of stor-age locations that are treated as non-Guarded inhypervisor real addressing mode, because theeffective RMI value that could be used for an in-order data access to such a storage location isundefined and hence could be 0.

Programming Note


Version 2.02

8.3 Move to Machine State Register Instruction

Move To Machine State Register X-form

mtmsr RS,L

if L = 0 then MSR48 � (RS)48 | (RS)49 MSR58 � (RS)58 | (RS)49 MSR59 � (RS)59 | (RS)49 MSR32:47 49:50 52:57 60:63 �(RS)32:47 49:50 52:57 60:63else MSR48 62 � (RS)48 62

The MSR is set based on the contents of register RSand of the L field.

L=0:

The result of ORing bits 48 and 49 of register RS isplaced into MSR48. The result of ORing bits 58and 49 of register RS is placed into MSR58. Theresult of ORing bits 59 and 49 of register RS isplaced into MSR59. Bits 32:47, 49:50, 52:57, and60:63 of register RS are placed into the corre-sponding bits of the MSR.

L=1:

Bits 48 and 62 of register RS are placed into thecorresponding bits of the MSR. The remaining bitsof the MSR are unchanged.


If L=0 this instruction is context synchronizing exceptwith respect to alterations to the LE bit; see Chapter7. “Synchronization Requirements for Context Alter-ations” on page 85. If L=1 this instruction is executionsynchronizing; in addition, the alterations of the EE andRI bits take effect as soon as the instruction completes.


Except in the mtmsr instruction description in this sec-tion, references to “mtmsr” in Books I - III imply either Lvalue unless otherwise stated or obvious from context(e.g., a reference to an mtmsr instruction that modifiesan MSR bit other than the EE or RI bit implies L=0).

31 RS /// L /// 146 /0 6 11 15 16 21 31

Warning: The first Programming Note in the mtm-srd instruction description applies to mtmsr as wellas to mtmsrd. Therefore software that usesmtmsr and will run on such processors must obeythe rules given in that Programming Note.

Programming Note

If this instruction sets MSRPR to 1, it also setsMSREE, MSRIR, and MSRDR to 1. On processorsprior to POWER4+, the setting of MSRPR does notaffect the setting of MSREE.

This instruction does not alter MSRME. (Thisinstruction does not alter MSRHV because it doesnot alter any of the high-order 32 bits of the MSR.)

If the only MSR bits to be altered are MSREE RI, toobtain the best performance L=1 should be used.

If MSREE=0 and an External or Decrementerexception is pending, executing an mtmsr instruc-tion that sets MSREE to 1 will cause the External orDecrementer interrupt to occur before the nextinstruction is executed, if no higher priority excep-tion exists (see Section 5.8, “Interrupt Priorities” onpage 76). Similarly, if a Hypervisor Decrementerinterrupt is pending, execution of the instruction bythe hypervisor causes a Hypervisor Decrementerinterrupt to occur if HDICE=1.

For a discussion of software synchronizationrequirements when altering certain MSR bits, seeChapter 7.

mtmsr serves as both a basic and an extendedmnemonic. The Assembler will recognize anmtmsr mnemonic with two operands as the basicform, and an mtmsr mnemonic with one operandas the extended form. In the extended form the Loperand is omitted and assumed to be 0.

There is no need for an analogous version of themfmsr instruction, because the existing instructioncopies the entire contents of the MSR to theselected GPR.

Programming Note

Programming Note

Programming Note

Programming Note

Chapter 8. Optional Facilities and Instructions 91

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8.4 Fixed-Point Storage Access Instructions

WARNING: These instructions are optional. They are not implemented in all processors. These instructions should be used only in code contained in a Programming Abstraction Layer (PAL) (i.e., code that is used only on an implementation-dependent basis).

Load Quadword DQ-form

lq RT,DQ(RA)

if RA = 0 then b � 0else b � (RA)EA � b + EXTS(DQ || 0b0000)RT � MEM(EA, 8)GPR(RT+1) � MEM(EA+8, 8)

Let the effective address (EA) be the sum (RA|0)+(DQ||0b0000). The quadword in storage addressed byEA is loaded into registers RT and RT+1, in increasingorder of storage address and register number.

EA must be a multiple of 16. If it is not, the systemalignment error handler is invoked.

If RT is odd or RT=RA, the instruction form is invalid. IfRT=RA, an attempt to execute this instruction willinvoke the system illegal instruction error handler. (TheRT=RA case includes the case of RT=RA=0.)




Store Quadword DS-form

stq RS,DS(RA)

if RA = 0 then b � 0else b � (RA)EA � b + EXTS(DS || 0b00)MEM(EA, 8) � RSMEM(EA+8, 8) � GPR(RS+1)

Let the effective address (EA) be the sum (RA|0)+(DS||0b00). (RS) and (RS+1) are stored into the quad-word in storage addressed by EA, in increasing order ofstorage address and register number.

EA must be a multiple of 16. If it is not, the systemalignment error handler is invoked.

If RS is odd, the instruction form is invalid.




Additional Notes

The following descriptions are additions to the architec-ture associated with the lq and stq instructions and notreplacements for existing descriptions.

Data Storage Interrupt

The effective address specified by a lq or stq instruc-tion refers to storage that is Write Through Required orCaching Inhibited. DSISR5: Set to 1 if the access wascaused by the execution of a lq or stq instruction.

Alignment Interrupt

The operand of a lq or stq instruction is not aligned.The instruction is a lq or stq and the operand is in stor-age that is Write Through Required or Caching Inhib-ited.

Note: lq and stq instructions may cause either a DataStorage or Alignment interrupt if the operand is in stor-age that is Write Through Required or Caching Inhib-ited.

56 RT RA DQ //0 6 11 16 28 31

62 RS RA DS 20 6 11 16 30 31


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Chapter 9. Optional Facilities and Instructions that are being Phased Out

9.1 Bridge to SLB Architecture . . . . . . . 939.1.1 Segment Register

Manipulation Instructions . . . . . . . . . . . 93

The facilities and instructions described in this chapterare optional. An implementation may provide all, some,or none of them.

Warning: These facilities and instructions are beingphased out of the architecture.

The facilities and instructions described in this chapterare generally not mentioned elsewhere in Books I - III.Any conflict between this chapter and other parts of theBooks is deemed to be resolved in favor of this chapter.

9.1 Bridge to SLB ArchitectureThe facility described in this section can be used toease the transition to the current PowerPC software-managed Segment Lookaside Buffer (SLB) architec-ture, from the Segment Register architecture providedby 32-bit PowerPC implementations.

The facility permits the operating system to continue touse the 32-bit PowerPC implementation’s SegmentRegister Manipulation instructions.

9.1.1 Segment RegisterManipulation Instructions

The instructions described in this section -- mtsr,mtsrin, mfsr, and mfsrin -- allow software to associateeffective segments 0 through 15 with any of virtual seg-ments 0 through 227-1. SLB entries 0:15 serve as vir-tual Segment Registers, with SLB entry i used toemulate Segment Register i. The mtsr and mtsrininstructions move 32 bits from a selected GPR to aselected SLB entry. The mfsr and mfsrin instructionsmove 32 bits from a selected SLB entry to a selectedGPR.

The contents of the GPRs used by the instructionsdescribed in this section are shown in Figure 42. Fieldsshown as zeros must be zero for the Move To SegmentRegister instructions. Fields shown as hyphens areignored. Fields shown as periods are ignored by theMove To Segment Register instructions and set to zeroby the Move From Segment Register instructions.Fields shown as colons are ignored by the Move ToSegment Register instructions and set to undefined val-ues by the Move From Segment Register instructions.

RS/RT

RB

Figure 42. GPR contents for mtsr, mtsrin, mfsr, and mfsrin

Warning: This facility is being phased out of thearchitecture. It is likely not to be supported onfuture implementations. New programs should notuse it.

Programming Note

: : : . KsKpN 0 VSID25:510 32 33 36 37 63

- - - ESID - - -0 32 36 63

Chapter 9. Optional Facilities and Instructions that are being Phased Out 93

Version 2.02

The “Segment Register” format used by the instruc-tions described in this section corresponds to thelow-order 32 bits of RS and RT shown in the figure.This format is essentially the same as that for theSegment Registers of 32-bit PowerPC implementa-tions. The only differences are the following.

� Bit 36 corresponds to a reserved bit in Seg-ment Registers. Software must supply 0 for thebit because it corresponds to the L bit in SLBentries, and large pages are not supported forSLB entries created by the Move To SegmentRegister instructions.

� VSID bits 25:27 correspond to reserved bits inSegment Registers. Software can use theseextra VSID bits to create VSIDs that are largerthan those supported by the Segment RegisterManipulation instructions of 32-bit PowerPCimplementations.

Bit 32 of RS and RT corresponds to the T (direct-store) bit of early 32-bit PowerPC implementations.No corresponding bit exists in SLB entries.

The Programming Note in the introduction toSection 4.11.3.1, “SLB Management Instructions”on page 49 applies also to the Segment RegisterManipulation instructions described in this section,and to any combination of the instructionsdescribed in the two sections, except as specifiedbelow for mfsr and mfsrin.

The requirement that the SLB contain at most oneentry that translates a given effective address (seeSection 4.4.1, “Segment Lookaside Buffer (SLB)”on page 33) applies to SLB entries created by mtsrand mtsrin. This requirement is satisfied naturallyif only mtsr and mtsrin are used to create SLBentries for a given ESID, because for these instruc-tions the association between SLB entries andESID values is fixed (SLB entry i is used for ESIDi). However, care must be taken if slbmte is alsoused to create SLB entries for the ESID, becausefor slbmte the association between SLB entriesand ESID values is specified by software.

Programming Note

Programming Note


Version 2.02

Move To Segment Register X-form

mtsr SR,RS

The SLB entry specified by SR is loaded from registerRS, as follows.

MSRSF must be 0 when this instruction is executed;otherwise the results are boundedly undefined.



Move To Segment Register Indirect X-form

mtsrin RS,RB[POWER mnemonic: mtsri]

The SLB entry specified by (RB)32:35 is loaded fromregister RS, as follows.




31 RS / SR /// 210 /0 6 11 12 16 21 31

SLBE Bit(s) Set to SLB Field(s)0:31 0x0000_0000 ESID0:3132:35 SR ESID32:3536 0b1 V37:61 0x00_0000||0b0 VSID0:2462:88 (RS)37:63 VSID25:5189:91 (RS)33:35 KsKpN92 (RS)36 L ((RS)36 must be 0b0)93 0b0 C

31 RS /// RB 242 / 0 6 11 16 21 31

SLBE Bit(s) Set to SLB Field(s)0:31 0x0000_0000 ESID0:3132:35 (RB)32:35 ESID32:3536 0b1 V37:61 0x00_0000||0b0 VSID0:2462:88 (RS)37:63 VSID25:5189:91 (RS)33:35 KsKpN92 (RS)36 L ((RS)36 must be 0b0)93 0b0 C

Chapter 9. Optional Facilities and Instructions that are being Phased Out 95

Version 2.02

Move From Segment Register X-form

mfsr RT,SR

The contents of the low-order 27 bits of the VSID field,and the contents of the Ks, Kp, N, and L fields, of theSLB entry specified by SR are placed into register RT,as follows.

RT32 is set to 0. The contents of RT0:31 are undefined.


This instruction must be used only to read an SLB entrythat was, or could have been, created by mtsr ormtsrin and has not subsequently been invalidated (i.e.,an SLB entry in which ESID<16, V=1, VSID<227, L=0,and C=0). Otherwise the contents of register RT areundefined.



Move From Segment Register IndirectX-form

mfsrin RT,RB

The contents of the low-order 27 bits of the VSID field,and the contents of the Ks, Kp, N, and L fields, of theSLB entry specified by (RB)32:35 are placed into regis-ter RT, as follows.

RT32 is set to 0. The contents of RT0:31 are undefined.


This instruction must be used only to read an SLB entrythat was, or could have been, created by mtsr ormtsrin and has not subsequently been invalidated (i.e.,an SLB entry in which ESID<16, V=1, VSID<227, L=0,and C=0). Otherwise the contents of register RT areundefined.



31 RT / SR /// 595 /0 6 11 12 16 21 31

SLBE Bit(s) Copied to SLB Field(s)62:88 RT37:63 VSID25:5189:91 RT33:35 KsKpN92 RT36 L (SLBEL must be 0b0)

31 RT /// RB 659 /0 6 11 16 21 31

SLBE Bit(s) Copied to SLB Field(s)62:88 RT37:63 VSID25:5189:91 RT33:35 KsKpN92 RT36 L (SLBEL must be 0b0)


Version 2.02

Appendix A. Assembler Extended Mnemonics

In order to make assembler language programs simplerto write and easier to understand, a set of extendedmnemonics and symbols is provided for certain instruc-tions. This appendix defines extended mnemonics andsymbols related to instructions defined in Book III.

Assemblers should provide the extended mnemonicsand symbols listed here, and may provide others.

Appendix A. Assembler Extended Mnemonics 97

Version 2.02

A.1 Move To/From Special Purpose Register Mnemonics

This section defines extended mnemonics for themtspr and mfspr instructions, including the SpecialPurpose Registers (SPRs) defined in Book I and cer-tain privileged SPRs, and for the Move From TimeBase instruction defined in Book II.

The mtspr and mfspr instructions specify an SPR as anumeric operand; extended mnemonics are providedthat represent the SPR in the mnemonic rather thanrequiring it to be coded as an operand. Similarextended mnemonics are provided for the Move FromTime Base instruction, which specifies the portion ofthe Time Base as a numeric operand.

Note: mftb serves as both a basic and an extendedmnemonic. The Assembler will recognize an mftbmnemonic with two operands as the basic form, and anmftb mnemonic with one operand as the extendedform. In the extended form the TBR operand is omittedand assumed to be 268 (the value that corresponds toTB).

The extended mnemonics in Table 3 for SPRsassociated with the Performance Monitor facilityare based on the definitions in Appendix E.

Other versions of Performance Monitor facilitiesused different sets of SPR numbers (all 32-bit Pow-erPC processors used a different set, and someearly PowerPC processors used yet a differentset).

Programming Note


Version 2.02

Table 3: Extended mnemonics for moving to/from an SPR

Special Purpose RegisterMove To SPR Move From SPR1

Extended Equivalent to Extended Equivalent to

Fixed-Point Exception Register mtxer Rx mtspr 1,Rx mfxer Rx mfspr Rx,1

Link Register mtlr Rx mtspr 8,Rx mflr Rx mfspr Rx,8

Count Register mtctr Rx mtspr 9,Rx mfctr Rx mfspr Rx,9

Data Storage Interrupt Status Register

mtdsisr Rx mtspr 18,Rx mfdsisr Rx mfspr Rx,18

Data Address Register mtdar Rx mtspr 19,Rx mfdar Rx mfspr Rx,19

Decrementer mtdec Rx mtspr 22,Rx mfdec Rx mfspr Rx,22

Storage Description Register 1 mtsdr1 Rx mtspr 25,Rx mfsdr1 Rx mfspr Rx,25

Save/Restore Register 0 mtsrr0 Rx mtspr 26,Rx mfsrr0 Rx mfspr Rx,26

Save/Restore Register 1 mtsrr1 Rx mtspr 27,Rx mfsrr1 Rx mfspr Rx,27

ACCR mtaccr Rx mtspr 29,Rx mfaccr Rx mfspr Rx,29

CTRL mtctrl Rx mtspr 152,Rx mfctrl Rx mfspr Rx,136

Special Purpose Registers G0 through G3

mtsprg n,Rx mtspr 272+n,Rx mfsprg Rx,n mfspr Rx,272+n

Time Base [Lower] mttbl Rx mtspr 284,Rx mftb Rx mftb Rx,268

Time Base Upper mttbu Rx mtspr 285,Rx mftbu Rx mftb Rx,269

Processor Version Register - - mfpvr Rx mfspr Rx,287

MMCRA mtmmcra Rx mtspr 786,Rx mfmmcra Rx mfspr Rx,770

PMC1 mtpmc1 Rx mtspr 787,Rx mfpmc1 Rx mfspr Rx,771






MMCR0 mtmmcr0 Rx mtspr 795,Rx mfmmcr0 Rx mfspr Rx,779

MMCR1 mtmmcr1 Rx mtspr 798,Rx mfmmcr1 Rx mfspr Rx,782

Processor Identification Register - - mfpir Rx mfspr Rx,10231 Except for mftb and mftbu.

Appendix A. Assembler Extended Mnemonics 99

Version 2.02


Version 2.02

Appendix B. Cross-Reference for Changed POWER Mnemonics

The following table lists the POWER instruction mne-monics that have been changed in the PowerPC Oper-ating Environment Architecture, sorted by POWERmnemonic.

To determine the PowerPC mnemonic for one of thesePOWER mnemonics, find the POWER mnemonic inthe second column of the table: the remainder

of the line gives the PowerPC mnemonic and the pageon which the instruction is described, as well as theinstruction names.

POWER mnemonics that have not changed are notlisted. POWER instruction names that are the same inPowerPC are not repeated: i.e., for these, the last col-umn of the table is blank.

PagePOWER PowerPC

Mnemonic Instruction Mnemonic Instruction95 mtsri Move To Segment Register Indirect mtsrin12 svca Supervisor Call sc System Call53 tlbi TLB Invalidate Entry tlbie

Appendix B. Cross-Reference for Changed POWER Mnemonics 101

Version 2.02


Version 2.02

Appendix C. New and Newly Optional Instructions

The following instructions in the PowerPC OperatingEnvironment Architecture are new; they are not in thePOWER Architecture. The tlbia, tlbsync, and mtmsrinstructions are optional. In addition, the mfsr, mfsrin,mtsr, and mtsrin instructions may optionally be pro-vided as part of a “bridge” facility as described inSection 9.1, “Bridge to SLB Architecture” on page 93.

hrfid Hypervisor Return From Interrupt Double-word

mfsrin Move From Segment Register Indirectmtmsrd Move To Machine State Register Double-

wordrfid Return From Interrupt Doublewordslbia SLB Invalidate Allslbie SLB Invalidate Entryslbmfee SLB Move From Entry ESIDslbmfev SLB Move From Entry VSIDslbmte SLB Move To Entrytlbia TLB Invalidate Alltlbsync TLB Synchronize

Appendix C. New and Newly Optional Instructions 103

Version 2.02


Version 2.02

Appendix D. Interpretation of the DSISR as Set by an Alignment Interrupt

For most causes of Alignment interrupt, the interrupthandler will emulate the interrupting instruction. To dothis, it needs the following characteristics of the inter-rupting instruction:

Load or storeLength (halfword, word, doubleword)String, multiple, or elementaryFixed-point or floating-pointUpdate or non-updateByte reverse or notIs it dcbz?

The PowerPC Architecture optionally provides thisinformation by setting bits in the DSISR that identify theinterrupting instruction type. It is not necessary for theinterrupt handler to load the interrupting instructionfrom storage. The mapping is unique except for a fewexceptions that are discussed below. The near-unique-ness depends on the fact that many instructions, suchas the fixed- and floating-point arithmetic instructionsand the one-byte loads and stores, cannot cause anAlignment interrupt.

See Section 5.5.8, “Alignment Interrupt” on page 69 fora description of how the opcode and extended opcodeare mapped to a DSISR value for an X-, D-, or DS-forminstruction that causes an Alignment interrupt.

The table on the next page shows the inverse mapping:how the DSISR bits identify the interrupting instruc-tion. The following notes are cited in the table.

(1) The instructions lwz and lwarx give the sameDSISR bits (all zero). But if lwarx causes an Align-ment interrupt, it should not be emulated. It is ade-quate for the Alignment interrupt handler simply totreat the instruction as if it were lwz. The emulatormust use the address in the DAR, rather than com-pute it from RA/RB/D, because lwz and lwarxhave different instruction formats.

If opcode 0 (“Illegal or Reserved”) can cause anAlignment interrupt, it will be indistinguishable tothe interrupt handler from lwarx and lwz.

(2) These are distinguished by DSISR bits 12:13,which are not shown in the table.

The interrupt handler has no need to distinguishbetween an X-form instruction and the correspondingD- or DS-form instruction if one exists, and vice versa.Therefore two such instructions may yield the sameDSISR value (all 32 bits). For example, stw and stwxmay both yield either the DSISR value shown in the fol-lowing table for stw, or that shown for stwx.

Appendix D. Interpretation of the DSISR as Set by an Alignment Interrupt 105

Version 2.02

If DSISR 15:21 is:

then it is either X-form opcode:

or D/DS-form opcode: so the instruction is:

00 0 0000 00000xxx00 x00000 lwarx, lwz, reserved (1)

00 0 0001 00010xxx00 x00010 ldarx00 0 0010 00100xxx00 x00100 stw00 0 0011 00110xxx00 x00110 -00 0 0100 01000xxx00 x01000 lhz00 0 0101 01010xxx00 x01010 lha00 0 0110 01100xxx00 x01100 sth00 0 0111 01110xxx00 x01110 lmw00 0 1000 10000xxx00 x10000 lfs00 0 1001 10010xxx00 x10010 lfd00 0 1010 10100xxx00 x10100 stfs00 0 1011 10110xxx00 x10110 stfd00 0 1100 11000xxx00 x11000 -00 0 1101 11010xxx00 x11010 ld, ldu, lwa (2)00 0 1110 11100xxx00 x11100 -00 0 1111 11110xxx00 x11110 std, stdu (2)00 1 0000 00001xxx00 x00001 lwzu00 1 0001 00011xxx00 x00011 -00 1 0010 00101xxx00 x00101 stwu00 1 0011 00111xxx00 x00111 -00 1 0100 01001xxx00 x01001 lhzu00 1 0101 01011xxx00 x01011 lhau00 1 0110 01101xxx00 x01101 sthu00 1 0111 01111xxx00 x01111 stmw00 1 1000 10001xxx00 x10001 lfsu00 1 1001 10011xxx00 x10011 lfdu00 1 1010 10101xxx00 x10101 stfsu00 1 1011 10111xxx00 x10111 stfdu00 1 1100 11001xxx00 x11001 -00 1 1101 11011xxx00 x11011 -00 1 1110 11101xxx00 x11101 -00 1 1111 11111xxx00 x11111 -01 0 0000 00000xxx01 ldx01 0 0001 00010xxx01 -01 0 0010 00100xxx01 stdx01 0 0011 00110xxx01 -01 0 0100 01000xxx01 -01 0 0101 01010xxx01 lwax01 0 0110 01100xxx01 -01 0 0111 01110xxx01 -01 0 1000 10000xxx01 lswx01 0 1001 10010xxx01 lswi01 0 1010 10100xxx01 stswx01 0 1011 10110xxx01 stswi01 0 1100 11000xxx01 -01 0 1101 11010xxx01 -01 0 1110 11100xxx01 -01 0 1111 11110xxx01 -01 1 0000 00001xxx01 ldux01 1 0001 00011xxx01 -01 1 0010 00101xxx01 stdux01 1 0011 00111xxx01 -01 1 0100 01001xxx01 -01 1 0101 01011xxx01 lwaux01 1 0110 01101xxx01 -01 1 0111 01111xxx01 -01 1 1000 10001xxx01 -01 1 1001 10011xxx01 -01 1 1010 10101xxx01 -01 1 1011 10111xxx01 -01 1 1100 11001xxx01 -01 1 1101 11011xxx01 -01 1 1110 11101xxx01 -01 1 1111 11111xxx01 -

10 0 0000 00000xxx10 -10 0 0001 00010xxx10 -10 0 0010 00100xxx10 stwcx.10 0 0011 00110xxx10 stdcx.10 0 0100 01000xxx10 -10 0 0101 01010xxx10 -10 0 0110 01100xxx10 -10 0 0111 01110xxx10 -10 0 1000 10000xxx10 lwbrx10 0 1001 10010xxx10 -10 0 1010 10100xxx10 stwbrx10 0 1011 10110xxx10 -10 0 1100 11000xxx10 lhbrx10 0 1101 11010xxx10 -10 0 1110 11100xxx10 sthbrx10 0 1111 11110xxx10 -10 1 0000 00001xxx10 -10 1 0001 00011xxx10 -10 1 0010 00101xxx10 -10 1 0011 00111xxx10 -10 1 0100 01001xxx10 eciwx10 1 0101 01011xxx10 -10 1 0110 01101xxx10 ecowx10 1 0111 01111xxx10 -10 1 1000 10001xxx10 -10 1 1001 10011xxx10 -10 1 1010 10101xxx10 -10 1 1011 10111xxx10 -10 1 1100 11001xxx10 -10 1 1101 11011xxx10 -10 1 1110 11101xxx10 -10 1 1111 11111xxx10 dcbz11 0 0000 00000xxx11 lwzx11 0 0001 00010xxx11 -11 0 0010 00100xxx11 stwx11 0 0011 00110xxx11 -11 0 0100 01000xxx11 lhzx11 0 0101 01010xxx11 lhax11 0 0110 01100xxx11 sthx11 0 0111 01110xxx11 -11 0 1000 10000xxx11 lfsx11 0 1001 10010xxx11 lfdx11 0 1010 10100xxx11 stfsx11 0 1011 10110xxx11 stfdx11 0 1100 11000xxx11 -11 0 1101 11010xxx11 -11 0 1110 11100xxx11 -11 0 1111 11110xxx11 stfiwx11 1 0000 00001xxx11 lwzux11 1 0001 00011xxx11 -11 1 0010 00101xxx11 stwux11 1 0011 00111xxx11 -11 1 0100 01001xxx11 lhzux11 1 0101 01011xxx11 lhaux11 1 0110 01101xxx11 sthux11 1 0111 01111xxx11 -11 1 1000 10001xxx11 lfsux11 1 1001 10011xxx11 lfdux11 1 1010 10101xxx11 stfsux11 1 1011 10111xxx11 stfdux11 1 1100 11001xxx11 -11 1 1101 11011xxx11 -11 1 1110 11101xxx11 -11 1 1111 11111xxx11 -

If DSISR 15:21 is:

then it is either X-form opcode:

or D/DS-form opcode: so the instruction is:


Version 2.02

Appendix E. Example Performance Monitor (Optional)

A Performance Monitor facility provides a means of col-lecting information about program and system perfor-mance.

The resources (e.g., SPR numbers) that a PerformanceMonitor facility may use are identified elsewhere in thisBook. All other aspects of any Performance Monitorfacility are implementation-dependent, and aredescribed in the Book IV, PowerPC ImplementationFeatures document for the implementation.

This appendix provides an example of a PerformanceMonitor facility. It is only an example; implementationsmay provide all, some, or none of the featuresdescribed here, or may provide features that are similarto those described here but differ in detail.

The example Performance Monitor facility consists ofthe following features (described in detail in subse-quent sections).

� one MSR bit

- PMM (Performance Monitor Mark), which canbe used to select one or more programs formonitoring

� SPRs

- PMC1 - PMC6 (Performance Monitor Counterregisters 1 - 6), which count events

- MMCR0, MMCR1, and MMCRA (MonitorMode Control Registers 0, 1, and A), whichcontrol the Performance Monitor facility

- SIAR and SDAR (Sampled InstructionAddress Register and Sampled Data AddressRegister), which contain the address of the“sampled instruction” and of the “sampleddata”

� the Performance Monitor interrupt, which can becaused by monitored conditions and events

The minimal subset of the features that makes theresulting Performance Monitor useful to software con-sists of MSRPMM, PMC1, PMC2, PMC3, PMC4,MMCR0, MMCR1, and MMCRA and certain bits andfields of these three Monitor Mode Control Registers,and the Performance Monitor Interrupt. These featuresare identified as the “basic” features below. Theremaining features (the remaining SPRs, and theremaining bits and fields in the three Monitor ModeControl Registers) are considered “extensions”.

The events that can be counted in the PMCs are imple-mentation-dependent. The Book IV, PowerPC Imple-mentation Features document for the implementationdescribes the events that are available for each PMC,and also the code that identifies each event. Theevents and codes may vary between PMCs, as well asbetween implementations. For the programmablePMCs, the event to be counted is selected by specify-ing the appropriate code in the MMCR “Selector” fieldfor the PMC. As described in Book IV, some eventsmay include operations that are performed out-of-order.

Many aspects of the operation of the PerformanceMonitor are summarized by the following hierarchy,which is described starting at the lowest level.

� A “counter negative condition” exists when thevalue in a PMC is negative (i.e., when bit 0 of thePMC is 1). A “Time Base transition event” occurswhen a selected bit of the Time Base changesfrom 0 to 1 (the bit is selected by an MMCR field).The term “condition or event” is used as an abbre-viation for “counter negative condition or TimeBase transition event”. A condition or event can becaused implicitly by the processor (e.g., increment-ing a PMC) or explicitly by software (mtspr).

� A condition or event is enabled if the correspond-ing “Enable” bit in an MMCR is 1. The occurrenceof an enabled condition or event can have sideeffects within the Performance Monitor, such ascausing the PMCs to cease counting.

� An enabled condition or event causes a Perfor-mance Monitor alert if Performance Monitor eventsare enabled by the corresponding “Enable” bit inan MMCR. A single Performance Monitor alert

Because the features provided by a PerformanceMonitor facility are implementation-dependent,operating systems should provide services thatsupport the useful performance monitoring func-tions in a generic fashion. Application programsshould use these services, and should not dependon the features provided by a particular implemen-tation.

Programming Note

Appendix E. Example Performance Monitor (Optional) 107

Version 2.02

may reflect multiple enabled conditions andevents.

� A Performance Monitor alert causes a Perfor-mance Monitor exception.

The exception effects of the Performance Monitorare said to be consistent with the contents ofMMCR0PMAO if one of the following statements istrue. (MMCR0PMAO reflects the occurrence of Per-formance Monitor events; see the definition of thatbit in Section E.2.1.1.)- MMCR0PMAO=0 and a Performance Monitor

exception does not exist.- MMCR0PMAO=1 and a Performance Monitor

exception exists.

A context synchronizing instruction or event thatoccurs when MMCR0PMAO=0 ensures that theexception effects of the Performance Monitor areconsistent with the contents of MMCR0PMAO.

Even without software synchronization, when thecontents of MMCR0PMAO change, the exceptioneffects of the Performance Monitor become con-sistent with the new contents of MMCR0PMAO suf-ficiently soon that the Performance Monitor facilityis useful to software for its intended purposes.

� A Performance Monitor exception causes a Perfor-mance Monitor interrupt when MSREE=1.

E.1 PMM Bit of the Machine State RegisterThe Performance Monitor uses MSR bit PMM, which isdefined as follows.

Bit Description

61 Performance Monitor Mark (PMM)

This bit is a basic feature.

This bit contains the Performance Monitor“mark” (0 or 1).

The Performance Monitor can be effectively dis-abled (i.e., put into a state in which PerformanceMonitor SPRs are not altered and PerformanceMonitor interrupts do not occur) by setting MMCR0to 0x0000_0000_8000_0000.

Programming Note

Software can use this bit as a process-specificmarker which, in conjunction with MMCR0FCM0

FCM1 (see Section E.2.1.1), permits events to becounted on a process-specific basis. (The bit issaved by interrupts and restored by rfid.)

Common uses of the PMM bit include the following.

� Count events for a few selected processes.This use requires the following bit settings.- MSRPMM=1 for the selected processes,

MSRPMM=0 for all other processes- MMCR0FCM0=1- MMCR0FCM1=0

� Count events for all but a few selected pro-cesses. This use requires the following bit set-tings.- MSRPMM=1 for the selected processes,

MSRPMM=0 for all other processes- MMCR0FCM0=0- MMCR0FCM1=1

Notice that for both of these uses a mark value of 1identifies the “few” processes and a mark value of 0identifies the remaining “many” processes.Because the PMM bit is set to 0 when an interruptoccurs (see Figure 35 on page 65), interrupt han-dlers are treated as one of the “many”. If it isdesired to treat interrupt handlers as one of the“few”, the mark value convention just describedwould be reversed.

Programming Note


Version 2.02

E.2 Special Purpose RegistersThe Performance Monitor SPRs count events, controlthe operation of the Performance Monitor, and provideassociated information.

The Performance Monitor SPRs can be read and writ-ten using the mfspr and mtspr instructions (seeSection 3.4.2, “Move To/From System Register Instruc-tions” on page 18). The Performance Monitor SPRnumbers are shown in Figure 43. Writing any of thePerformance Monitor SPRs is privileged. Reading anyof the Performance Monitor SPRs is not privileged(however, the privileged SPR numbers used to writethe SPRs can also be used to read them; see the fig-ure).

The elapsed time between the execution of an instruc-tion and the time at which events due to that instructionhave been reflected in Performance Monitor SPRs isnot defined. No means are provided by which softwarecan ensure that all events due to preceding instructionshave been reflected in Performance Monitor SPRs.Similarly, if the events being monitored may be causedby operations that are performed out-of-order, nomeans are provided by which software can preventsuch events due to subsequent instructions from beingreflected in Performance Monitor SPRs. Thus the con-tents obtained by reading a Performance Monitor SPRmay not be precise: it may fail to reflect some eventsdue to instructions that precede the mfspr and mayreflect some events due to instructions that follow themfspr. This lack of precision applies regardless ofwhether the state of the processor is such that the SPRis subject to change by the processor at the time themfspr is executed. Similarly, if an mtspr instruction isexecuted that changes the contents of the Time Base,the change is not guaranteed to have taken effect withrespect to causing Time Base transition events untilafter a subsequent context synchronizing instructionhas been executed.

If an mtspr instruction is executed that changes thevalue of a Performance Monitor SPR other than SIARor SDAR, the change is not guaranteed to have takeneffect until after a subsequent context synchronizinginstruction has been executed (see Chapter7. “Synchronization Requirements for Context Alter-ations” on page 85).

Figure 43. Performance Monitor SPR encodings formtspr and mfspr

E.2.1 Performance Monitor Counter Registers

The six Performance Monitor Counter registers, PMC1through PMC6, are 32-bit registers that count events.

Figure 44. Performance Monitor Counter registers

PMC1, PMC2, PMC3, and PMC4 are basic features.PMC5 and PMC6 are not programmable. PMC5counts instructions completed and PMC6 countscycles, see Book IV for more detail.

Normally each PMC is incremented each processorcycle by the number of times the corresponding eventoccurred in that cycle. Other modes of incrementingmay also be provided (e.g., see the description ofMMCR1 bits PMC1HIST and PMCjHIST).

“PMCj” is used as an abbreviation for “PMCi, i > 1”.

Depending on the events being monitored, the con-tents of Performance Monitor SPRs may beaffected by aspects of the runtime environment(e.g., cache contents) that are not directly attribut-able to the programs being monitored.

Programming Note

SPR1,2

decimal spr5:9 spr0:4

Register Name

Privi-leged

770,786 11000 n0010 MMCRA no,yes771,787 11000 n0011 PMC1 no,yes772,788 11000 n0100 PMC2 no,yes773,789 11000 n0101 PMC3 no,yes774,790 11000 n0110 PMC4 no,yes775,791 11000 n0111 PMC5 no,yes776,792 11000 n1000 PMC6 no,yes

779,795 11000 n1011 MMCR0 no,yes780,796 11000 n1100 SIAR no,yes781,797 11000 n1101 SDAR no,yes782,798 11000 n1110 MMCR1 no,yes


2 For mtspr, n must be 1. For mfspr, reading the SPR is privileged if and only if n=1.

PMC1PMC2PMC3

PMC4PMC5PMC6

0 31


Version 2.02

E.2.1.1 Monitor Mode Control Register 0

Monitor Mode Control Register 0 (MMCR0) is a 64-bitregister. This register, along with MMCR1 andMMCRA, controls the operation of the PerformanceMonitor.

Figure 45. Monitor Mode Control Register 0

MMCR0 is a basic feature. Within MMCR0, some ofthe bits and fields are basic features and some areextensions. The basic bits and fields are identified assuch, below.

Some bits of MMCR0 are altered by the processorwhen various events occur, as described below.

The bit definitions of MMCR0 are as follows. MMCR0bits that are not implemented are treated as reserved.

Bit(s) Description

0:31 Reserved

32 Freeze Counters (FC)

This bit is a basic feature.0 The PMCs are incremented (if permitted

by other MMCR bits).1 The PMCs are not incremented.

The processor sets this bit to 1 when anenabled condition or event occurs andMMCR0FCECE=1.

33 Freeze Counters in Supervisor State (FCS)


0 The PMCs are incremented (if permittedby other MMCR bits).

1 The PMCs are not incremented ifMSRHV PR=0b00.

34 Freeze Counters in Problem State (FCP)



1 The PMCs are not incremented ifMSRPR=1.

35 Freeze Counters while Mark = 1 (FCM1)



1 The PMCs are not incremented ifMSRPMM=1.

36 Freeze Counters while Mark = 0 (FCM0)



1 The PMCs are not incremented ifMSRPMM=0.

37 Performance Monitor Alert Enable (PMAE)


0 Performance Monitor events are disabled.1 Performance Monitor events are enabled

until a Performance Monitor eventoccurs, at which time:� MMCR0PMAE is set to 0� MMCR0PMAO is set to 1

38 Freeze Counters on Enabled Condition orEvent (FCECE)


1 The PMCs are incremented (if permittedby other MMCR bits) until an enabledcondition or event occurs whenMMCR0TRIGGER=0, at which time:� MMCR0FC is set to 1

If the enabled condition or event occurs whenMMCR0TRIGGER=1, the FCECE bit is treatedas if it were 0.

PMC5 and PMC6 are defined to facilitate calculat-ing basic performance metrics such as cycles perinstruction (CPI).

Software can use a PMC to “pace” the collection ofPerformance Monitor data. For example, if it isdesired to collect event counts every n cycles, soft-ware can specify that a particular PMC countcycles and set that PMC to 0x8000_0000 - n. Theevents of interest would be counted in other PMCs.The counter negative condition that will occur aftern cycles can, with the appropriate setting of MMCRbits, cause counter values to become frozen, causea Performance Monitor interrupt to occur, etc.

MMCR00 63

Programming Note

Programming Note

Software can set this bit andMMCR0PMAO to 0 to prevent PerformanceMonitor interrupts.

Software can set this bit to 1 and then pollthe bit to determine whether an enabledcondition or event has occurred. This isespecially useful for software that runswith MSREE=0.

Programming Note


Version 2.02

39:40 Time Base Selector (TBSEL)

This field selects the Time Base bit that cancause a Time Base transition event (the eventoccurs when the selected bit changes from 0to 1).

00 Time Base bit 63 is selected.01 Time Base bit 55 is selected.10 Time Base bit 51 is selected.11 Time Base bit 47 is selected.

41 Time Base Event Enable (TBEE)

0 Time Base transition events are disabled.1 Time Base transition events are enabled.

42:47 Reserved

48 PMC1 Condition Enable (PMC1CE)

This bit controls whether counter negativeconditions due to a negative value in PMC1are enabled.

0 Counter negative conditions for PMC1 aredisabled.

1 Counter negative conditions for PMC1 areenabled.

49 PMCj Condition Enable (PMCjCE)

This bit controls whether counter negativeconditions due to a negative value in anyPMCj (i.e., in any PMC except PMC1) areenabled.

0 Counter negative conditions for all PMCjsare disabled.

1 Counter negative conditions for all PMCjsare enabled.

50 Trigger (TRIGGER)


1 PMC1 is incremented (if permitted byother MMCR bits). The PMCjs are notincremented until PMC1 is negative or anenabled condition or event occurs, atwhich time:� the PMCjs resume incrementing (if

permitted by other MMCR bits)� MMCR0TRIGGER is set to 0

See the description of the FCECE bit, above,regarding the interaction between TRIGGERand FCECE.

51:52 Setting is implementation-dependent; seeBook IV.

53:55 Reserved

56 Performance Monitor Alert Occurred(PMAO)

Time Base transition events can be usedto collect information about processoractivity, as revealed by event counts inPMCs and by addresses in SIAR andSDAR, at periodic intervals.

In multiprocessor systems in which theTime Base registers are synchronizedamong the processors, Time Base transi-tion events can be used to correlate thePerformance Monitor data obtained by theseveral processors. For this use, softwaremust specify the same TBSEL value for allthe processors in the system.

Because the frequency of the Time Baseis implementation-dependent, softwareshould invoke a system service programto obtain the frequency before choosing avalue for TBSEL.

Programming Note

Uses of TRIGGER include the following.

� Resume counting in the PMCjs whenPMC1 becomes negative, withoutcausing a Performance Monitor inter-rupt. Then freeze all PMCs (andoptionally cause a Performance Mon-itor interrupt) when a PMCj becomesnegative. The PMCjs then reflect theevents that occurred between thetime PMC1 became negative and thetime a PMCj becomes negative. Thisuse requires the following MMCR0 bitsettings.

- TRIGGER=1- PMC1CE=0- PMCjCE=1- TBEE=0- FCECE=1- PMAE=1 (if a Performance Moni-

tor interrupt is desired)

� Resume counting in the PMCjs whenPMC1 becomes negative, and causea Performance Monitor interrupt with-out freezing any PMCs. The PMCjsthen reflect the events that occurredbetween the time PMC1 becamenegative and the time the interrupthandler reads them. This userequires the following MMCR0 bit set-tings.

- TRIGGER=1- PMC1CE=1- TBEE=0- FCECE=0- PMAE=1

Programming Note


Version 2.02


0 A Performance Monitor event has notoccurred since the last time software setthis bit to 0.

1 A Performance Monitor event hasoccurred since the last time software setthis bit to 0.

This bit is set to 1 by the processor when aPerformance Monitor event occurs. This bitcan be set to 0 only by the mtspr instruction.

57 Setting is implementation-dependent; seeBook IV.

58 Freeze Counters 1-4 (FC1-4)

0 PMC1 - PMC4 are incremented (if permit-ted by other MMCR bits).

1 PMC1 - PMC4 are not incremented.

59 Freeze Counters 5-6 (FC5-6)

0 PMC5 - PMC6 are incremented (if permit-ted by other MMCR bits).

1 PMC5 - PMC6 are not incremented.

60:61 Reserved

62 Freeze Counters in Wait State (FCWAIT)



1 The PMCs are not incremented ifCTRL31=0. Software is expected to setCTRL31=0 when it is in a “wait state”, i.e,when there is no process ready to run.

Only Branch Unit type of events do not incre-ment if CTRL31=0. Other units continue tocount.

63 Freeze Counters in Hypervisor State (FCH)



1 The PMCs are not incremented ifMSRHV PR=0b10.

E.2.2 Monitor Mode Control Register 1

Monitor Mode Control Register 1 (MMCR1) is a 64-bitregister. This register, along with MMCR0 andMMCRA, controls the operation of the PerformanceMonitor.

Figure 46. Monitor Mode Control Register 1

MMCR1 is a basic feature. Within MMCR1, some ofthe bits and fields are basic features and some areextensions. The basic bits and fields are identified assuch, below.

Some bits of MMCR1 are altered by the processorwhen various events occur, as described below.

The bit definitions of MMCR1 are as follows. MMCR1bits that are not implemented are treated as reserved.

Bit(s) Description

0:31 Implementation-Dependent Use

These bits have implementation-dependentuses (e.g., extended event selection).

32:39 PMC1 Selector (PMC3SEL)40:47 PMC2 Selector (PMC4SEL)48:55 PMC3 Selector (PMC5SEL)56:63 PMC4 Selector (PMC6SEL)

Each of these fields contains a code that iden-tifies the event to be counted by PMCs 1through 4 respectively; see Book IV.

PMC Selectors are basic features.

Software can set this bit to 1 to simulatethe occurrence of a Performance Monitorevent.

Software should set this bit to 0 after han-dling the Performance Monitor event.

This bit was first implemented in thePOWER4+ processor.

Programming Note

MMCR10 63

In versions of the architecture that pre-cede Version 2.02 the PMC SelectorFields were six bits long, and were splitbetween MMCR0 and MMCR1. PMC1-8were all programmable.

If more programmable PMCs are imple-mented in the future, additional MMCRsmay be defined to cover the additionalselectors.

Compatibility Note


Version 2.02

E.2.3 Monitor Mode Control Register A

Monitor Mode Control Register A (MMCRA) is a 64-bitregister. This register, along with MMCR0 andMMCR1, controls the operation of the PerformanceMonitor.

Figure 47. Monitor Mode Control Register A

MMCRA is a basic feature. Within MMCRA, some ofthe bits and fields are basic features and some areextensions. The basic bits and fields are identified assuch, below.

Some bits of MMCRA are altered by the processorwhen various events occur, as described below.

The bit definitions of MMCRA are as follows. MMCRAbits that are not implemented are treated as reserved.

Bit(s) Description

0:31 Reserved

32 Contents of SIAR and SDAR Are Related(CSSR)

Set to 1 by the processor if the contents ofSIAR and SDAR are associated with the sameinstruction; otherwise set to 0.


35 Sampled MSRHV (SAMPHV)

Value of MSRHV when the Performance Moni-tor Alert occurred.

36 Sampled MSRPR (SAMPPR)

Value of MSRPR when the Performance Moni-tor Alert occurred.


48:53 Threshold (THRESHOLD)

This field contains a “threshold value”, whichis a value such that only events that exceedthe value are counted. The events to which athreshold value can apply are implementation-dependent, as are the dimension of thethreshold (e.g., duration in cycles) and thegranularity with which the threshold value isinterpreted. See the Book IV, PowerPCImplementation Features document for theimplementation.

54:59 Reserved for implementation-specific use.

60:62 Reserved

63 Setting is implementation-dependent; seeBook IV.

E.2.4 Sampled Instruction Address Register

The Sampled Instruction Address Register (SIAR) is a64-bit register. It contains the address of the “sampledinstruction” when a Performance Monitor alert occurs.

Figure 48. Sampled Instruction Address Register

When a Performance Monitor alert occurs, SIAR is setto the effective address of an instruction that was beingexecuted, possibly out-of-order, at or around the timethat the Performance Monitor alert occurred. Thisinstruction is called the “sampled instruction”.

The contents of SIAR may be altered by the processorif and only if MMCR0PMAE=1. Thus after the Perfor-mance Monitor alert occurs, the contents of SIAR arenot altered by the processor until software setsMMCR0PMAE to 1. After software sets MMCR0PMAE to1, the contents of SIAR are undefined until the nextPerformance Monitor alert occurs.

See Section E.4 regarding the effects of the Trace facil-ity on SIAR.

MMCRA0 63

By varying the threshold value, softwarecan obtain a profile of the characteristicsof the events subject to the threshold. Forexample, if PMC1 counts the number ofcache misses for which the durationexceeds the threshold value, then soft-ware can obtain the distribution of cachemiss durations for a given program bymonitoring the program repeatedly usinga different threshold value each time.

SIAR0 63

If the Performance Monitor alert causes a Perfor-mance Monitor interrupt, the value of MSRHV PRthat was in effect when the sampled instruction wasbeing executed is reported in MMCRA.

Programming Note

Programming Note


Version 2.02

E.2.5 Sampled Data Address Reg-ister

The Sampled Data Address Register (SDAR) is a 64-bitregister. It contains the address of the “sampled data”when a Performance Monitor alert occurs.

Figure 49. Sampled Data Address Register

When a Performance Monitor alert occurs, SDAR is setto the effective address of the storage operand of aninstruction that was being executed, possibly out-of-order, at or around the time that the Performance Moni-tor alert occurred. This storage operand is called the“sampled data”. The sampled data may be, but neednot be, the storage operand (if any) of the sampledinstruction (see Section E.2.4).

The contents of SDAR may be altered by the processorif and only if MMCR0PMAE=1. Thus after the Perfor-mance Monitor alert occurs, the contents of SDAR arenot altered by the processor until software setsMMCR0PMAE to 1. After software sets MMCR0PMAE to1, the contents of SDAR are undefined until the nextPerformance Monitor alert occurs.

See Section E.4 regarding the effects of the Trace facil-ity on SDAR.

E.3 Performance MonitorInterruptThe Performance Monitor interrupt is a system-causedinterrupt (see Section 5.3, “Interrupt Classes” onpage 62). It is masked by MSREE in the same mannerthat External and Decrementer interrupts are.

The Performance Monitor interrupt is a basic feature.

A Performance Monitor interrupt occurs when no higherpriority exception exists, a Performance Monitor excep-tion exists, and MSREE=1.

If multiple Performance Monitor exceptions occurbefore the first causes a Performance Monitor interrupt,the interrupt reflects the most recent Performance Mon-

itor exception and the preceding Performance Monitorexceptions are lost.



SRR133:36 and 42:47 See the Book IV, PowerPC Imple-

mentation Features document for theimplementation.



SIAR Set to the effective address of the “sampledinstruction” (see Section E.2.4).

SDAR Set to the effective address of the “sampleddata” (see Section E.2.5).

Execution resumes at effective address0x0000_0000_0000_0F00.

In general, statements about External and Decre-menter interrupts elsewhere in this Book apply also tothe Performance Monitor interrupt; for example, if aPerformance Monitor exception exists when an mtm-srd[d] instruction is executed that changes MSREEfrom 0 to 1, the Performance Monitor interrupt willoccur before the next instruction is executed (if nohigher priority exception exists).

The priority of the Performance Monitor exception isequal to that of the External, Decrementer, and Hyper-visor Decrementer exceptions (i.e., the processor maygenerate any one of the four interrupts for which anexception exists) (see Section 5.7.2, “Ordered Excep-tions” on page 74 and Section 5.8, “Interrupt Priorities”on page 76).

E.4 Interaction with the Trace FacilityIf the Trace facility includes setting SIAR and SDAR(see Appendix F, “Example Trace Extensions(Optional)” on page 117), and tracing is active(MSRSE=1 or MSRBE=1), the contents of SIAR andSDAR as used by the Performance Monitor facility areundefined and may change even whenMMCR0PMAE=0.

SDAR0 63

If the Performance Monitor alert causes a Perfor-mance Monitor interrupt, MMCRA indicateswhether the sampled data is the storage operandof the sampled instruction.

Programming Note

A potential combined use of the Trace and Perfor-mance Monitor facilities is to trace the control flowof a program and simultaneously count events forthat program.

Programming Note


Version 2.02


Version 2.02


Version 2.02

Appendix F. Example Trace Extensions (Optional)

This appendix provides an example of extensions thatmay be added to the Trace facility described inSection 5.5.14, “Trace Interrupt” on page 73. It is onlyan example; implementations may provide all, some, ornone of the features described here, or may providefeatures that are similar to those described here but dif-fer in detail. See the Book IV, PowerPC Implementa-tion Features document for the implementation.

The extensions consist of the following features(described in detail below).

� use of MSRSE BE=0b11 to specify new causes ofTrace interrupts

� specification of how certain SRR1 bits are setwhen a Trace interrupt occurs

� setting of SIAR and SDAR (see Appendix E) whena Trace interrupt occurs

MSRSE BE = 0b11

If MSRSE BE=0b11, the processor generates a Traceexception under the conditions described in Section5.5.14 for MSRSE BE=0b01, and also after successfullycompleting the execution of any instruction that wouldcause at least one of SRR1 bits 33:36, 42, and 44:46 tobe set to 1 (see below) if the instruction were executedwhen MSRSE BE=0b10.

This overrides the implicit statement in Section 5.5.14that the effects of MSRSE BE=0b11 are the same asthose of MSRSE BE=0b10.

SRR1

When a Trace interrupt occurs, the SRR1 bits that arenot loaded from the MSR are set as follows instead ofas described in Section 5.5.14.

33 Set to 1 if the traced instruction is icbi; oth-erwise set to 0.

34 Set to 1 if the traced instruction is dcbt,dcbtst, dcbz, dcbst, dcbf[l]; otherwise setto 0.

35 Set to 1 if the traced instruction is a Loadinstruction or eciwx; may be set to 1 if thetraced instruction is icbi, dcbt, dcbtst,dcbst, dcbf[l]; otherwise set to 0.

36 Set to 1 if the traced instruction is a Storeinstruction, dcbz, or ecowx; otherwise setto 0.

42 Set to 1 if the traced instruction is lswx orstswx; otherwise set to 0.

43 See the Book IV, PowerPC ImplementationFeatures document for the implementation.

44 Set to 1 if the traced instruction is a Branchinstruction and the branch is taken; other-wise set to 0.

45 Set to 1 if the traced instruction is eciwx orecowx; otherwise set to 0.

46 Set to 1 if the traced instruction is lwarx,ldarx, stwcx., or stdcx.; otherwise set to 0.

47 See the Book IV, PowerPC ImplementationFeatures document for the implementation.

SIAR and SDAR

If the optional Performance Monitor facility is imple-mented and includes SIAR and SDAR (see AppendixE. “Example Performance Monitor (Optional)” onpage 107), the following additional registers are setwhen a Trace interrupt occurs:

SIAR Set to the effective address of the tracedinstruction.

SDAR Set to the effective address of the storageoperand (if any) of the traced instruction;otherwise undefined.

If the state of the Performance Monitor is such that thePerformance Monitor may be altering these registers(i.e., if MMCR0PMAE=1), the contents of SIAR andSDAR as used by the Trace facility are undefined andmay change even when no Trace interrupt occurs.

Appendix F. Example Trace Extensions (Optional) 117

Version 2.02


Version 2.02

Appendix G. PowerPC Operating Environment Instruction Set

1Key to Mode Dependency Column

Except as described below and in the section entitled“Effective Address Calculation” in Book I, all instruc-tions in the PowerPC Operating Environment Architec-ture are independent of whether the processor is in 32-bit or 64-bit mode.

32 The instruction must be executed only in 32-bit mode.

64 The instruction must be executed only in 64-bit mode.

2Key to Privilege Column

P denotes a privileged instruction.

O denotes an instruction that is treated as privi-leged or nonprivileged (or hypervisor, formtspr), depending on the SPR number.

H denotes an instruction that can be executedonly in hypervisor state.

FormOpcode

Mode Dep.1

Priv.2 PageMne-

monicInstructionPri-

maryExtend

XL 19 274 H 13 hrfid Hypervisor Return From Interrupt DoublewordX 31 83 P 23 mfmsr Move From Machine State RegisterXFX 31 339 O 21 mfspr Move From Special Purpose RegisterX 31 595 32 P 96 mfsr Move From Segment RegisterX 31 659 32 P 96 mfsrin Move From Segment Register IndirectX 31 146 P 91 mtmsr Move To Machine State RegisterX 31 178 P 22 mtmsrd Move To Machine State Register DoublewordXFX 31 467 O 19 mtspr Move To Special Purpose RegisterX 31 210 32 P 95 mtsr Move To Segment RegisterX 31 242 32 P 95 mtsrin Move To Segment Register IndirectXL 19 18 P 13 rfid Return From Interrupt DoublewordSC 17 12 sc System CallX 31 498 P 50 slbia SLB Invalidate AllX 31 434 P 49 slbie SLB Invalidate EntryX 31 915 P 52 slbmfee SLB Move From Entry ESIDX 31 851 P 52 slbmfev SLB Move From Entry VSIDX 31 402 P 51 slbmte SLB Move To EntryX 31 370 P 55 tlbia TLB Invalidate AllX 31 306 64 H 53 tlbie TLB Invalidate EntryX 31 566 H 56 tlbsync TLB Synchronize

Appendix G. PowerPC Operating Environment Instruction Set 119

Version 2.02


Version 2.02

Index

A

ACCR 39address

effective address 25real 27, 29

address compare 26, 66ACCR 39

Address Compare Control Register 19, 21, 39Address Space Register 19, 21address translation 43

EA to VA 29esid to vsid 29overview 32PTE

page table entry 36, 43Reference bit 43RPN

real page number 35VA to RA 35VPN

virtual page number 3532-bit mode 29

address wrap 27addresses

accessed by processor 31implicit accesses 31interrupt vectors 31with defined uses 31

Alignment interrupt 69, 105assembler language

extended mnemonics 97mnemonics 97symbols 97

B

BESee Machine State Register

Branch Trace 73Bridge 93

Segment Registers 93SR 93

C

Caching Inhibited 26Change bit 43context

definition 2synchronization 4

Control Register 17Control Register 0 19, 21Count Register 19, 21CTRL

See Control RegisterCurrent Instruction Address 12

D

DABR interrupt 40DABR(X)

See Data Breakpoint Register (Extension)DAR

See Data Address Registerdata access 27Data Address Breakpoint Register (Extension) 7, 19,

21, 40, 86data address compare 66

ACCR 39Data Address Register 15, 19, 21, 67, 68, 70Data Segment interrupt 68Data Storage interrupt 66Data Storage Interrupt Status Register 16, 19, 21, 67,

70, 105Alignment interrupt 105

dcbst instruction 66dcbz instruction 39, 47, 66, 70, 105DEC

See DecrementerDecrementer 19, 21, 80Decrementer interrupt 22, 72, 91DR

See Machine State RegisterDSISR

See Data Storage Interrupt Status Register

E

E (Enable bit) 89eciwx instruction 66, 69, 70, 90ecowx instruction 66, 69, 70, 90EE

See Machine State Registereffective address 25, 32

size 25translation 33

eieio instruction 57

Index 121

Version 2.02

emulation assist 2exceptions

address compare 26, 39, 66definition 2page fault 26, 38, 66protection 26segment fault 26storage 26

execution synchronization 4External Access Register 19, 21, 66, 89External interrupt 22, 69, 91

F

FE0See Machine State Register

FE1See Machine State Register

Fixed-Point Exception Register 19, 21Floating-Point Unavailable interrupt 72FP

See Machine State Register

H

hardwaredefinition 2

hashed page table 36size 37

HDECSee Hypervisor Decrementer

HDICESee Logical Partitioning Control Register

hrfid instruction 10, 76HRMOR

See Hypervisor Real Mode Offset RegisterHSPRGn

See software-use SPRsHTAB

See hashed page tableHTABORG 37HTABSIZE 37HV

See Machine State Registerhypervisor 5

page table 36Hypervisor Decrementer 19, 21, 81, 86Hypervisor Decrementer interrupt 72Hypervisor Machine Status Save Restore Register

See HSRR0, HSRR1Hypervisor Machine Status Save Restore Register 0 9Hypervisor Real Mode Offset Register 6

I

icbi instruction 66ILE

See Logical Partitioning Control Registerimplicit branch 27

imprecise interrupt 62in-order operations 27instruction 66instruction fetch 27

effective address 27implicit branch 27

Instruction Segment interrupt 69Instruction Storage interrupt 68instruction-caused interrupt 62instructions

dcbst 66dcbz 39, 47, 70, 105eciwx 66, 69, 70, 90ecowx 66, 69, 70, 90eieio 57hrfid 10, 76icbi 66isync 63ldarx 63, 66, 69, 70lmw 69lookaside buffer 47lwa 70lwarx 63, 66, 69, 70, 105lwaux 70lwz 105mfmsr 10, 23mfspr 21mfsr 96mfsrin 96mtmsr 10, 76, 91mtmsrd 10, 22, 76

address wrap 27mtspr 19mtsr 95mtsrin 95optional

See optional instructionsptesync 4, 57rfid 10, 13, 63, 76sc 12, 73slbia 50slbie 49slbmfee 52slbmfev 52slbmte 51stdcx. 63, 66, 69, 70stmw 69storage control 47stw 105stwcx. 63, 66, 69, 70stwx 105sync 4, 43, 63tlbia 39, 55tlbie 39, 53, 56, 58tlbiel 54tlbsync 56, 57

interruptAlignment 69, 105DABR 40Data Segment 68


Version 2.02

Data Storage 66Decrementer 22, 72, 91definition 2External 22, 69, 91Floating-Point Unavailable 72Hypervisor Decrementer 72imprecise 62Instruction Segment 69Instruction Storage 68instruction-caused 62Machine Check 66new MSR 65overview 61Performance Monitor 73precise 62priorities 76processing 62Program 70recoverable 63synchronization 61System Call 73System Reset 66system-caused 62Trace 73vector 62, 65

IRSee Machine State Register

isync instruction 63

K

K bits 45key, storage 45

L

dcbf 66instructions

dcbf 66large page 33ldarx instruction 63, 66, 69, 70LE

See Machine State RegisterLink Register 19, 21lmw instruction 69Logical Partition Identification Register 7Logical Partitioning 5Logical Partitioning Control Register 5, 19, 21, 48, 86

HDICE Hypervisor Decrementer Interrupt Condition-ally Enable 6, 8, 23, 72, 73, 86, 91

ILE Interrupt Little-Endian 5, 65LPES Logical Partitioning Environment Selector 5,

8, 12, 29, 30, 45, 46, 65, 88RMI Real Mode Caching Inhibited Bit 5, 8, 88, 90RMLS Real Mode Offset Selector 5, 88

lookaside buffer 47lookaside buffers 85LPAR (see Logical Partitioning) 5LPCR

See Logical Partitioning Control RegisterLPES

See Logical Partitioning Control RegisterLPIDR

See Logical Partition Identification Registerlwa instruction 70lwarx instruction 63, 66, 69, 70, 105lwaux instruction 70lwz instruction 105

M

Machine Check interrupt 66Machine State Register 10, 12, 22, 23, 62, 63, 65, 91

BE Branch Trace Enable 10DR Data Relocate 11EE External Interrupt Enable 10, 22, 91FE0 FP Exception Mode 10FE1 FP Exception Mode 10FP FP Available 10HV Hypervisor State 10IR Instruction Relocate 10LE Little-Endian Mode 11ME Machine Check Enable 10PMMPerformance Monitor Mark 11, 108PR Problem State 10RI Recoverable Interrupt 11, 22, 91SE Single-Step Trace Enable 10SF Sixty Four Bit mode 10, 27

Machine Status Save Restore RegisterSee SRR0, SRR1

Machine Status Save Restore Register 0 9, 19, 21, 62,63

Machine Status Save Restore Register 1 19, 21, 62,63, 72

MESee Machine State Register

Memory Coherence Required 26mfmsr instruction 10, 23mfspr instruction 21mfsr instruction 96mfsrin instruction 96mnemonics

extended 97mode change 27MSR

See Machine State Registermtmsr instruction 10, 76, 91mtmsrd instruction 10, 22, 76mtspr instruction 19mtsr instruction 95mtsrin instruction 95

N

Next Instruction Address 12, 13

Index 123

Version 2.02

O

opcode 0 105optional facilities 93optional instructions 47, 89

slbia 50slbie 49tlbia 55tlbie 53tlbiel 54tlbsync 56

out-of-order operations 27

P

pagesize 25

page fault 26, 38, 66page size

large page 33page table

See also hashed page tablesearch 38update 57

page table entry 36, 43Change bit 43PP bits 45Reference bit 43update 57, 58

partition 5Performance Monitor interrupt 73PMM

See Machine State RegisterPP bits 45PR

See Machine State Registerprecise interrupt 62priority of interrupts 76Processor ID Register 21Processor Utilization of Resources Register 7, 19, 21,

82Processor Version Register 17, 21Program interrupt 70protection boundary 45, 70protection domain 45PTE 38

See also page table entryPTEG 38ptesync instruction 4, 57PURR

See Processor Utilization of Resources RegisterPVR

See Processor Version Register

R

RC bits 43real address 29, 32Real Mode Offset Register 6

real pagedefinition 1

real page number 36recoverable interrupt 63reference and change recording 43Reference bit 43registers

ACCRAddress Compare Control Register 19, 21

ASRAddress Space Register 19, 21

CTRCount Register 19, 21

CTRLControl Register 17Control Register 0 19, 21

DABR(X)Data Address Breakpoint Register

(Extension) 7, 19, 21, 40, 86DAR

Data Address Register 15, 19, 21, 67, 68, 70DEC

Decrementer 19, 21, 80DSISR

Data Storage Interrupt Status Register 16, 19,21, 67, 70, 105

EARExternal Access Register 19, 21, 66, 89

HDECHypervisor Decrementer 19, 21, 81, 86

HRMORHypervisor Real Mode Offset Register 6

HSPRGnsoftware-use SPRs 16

HSRR0Hypervisor Machine Status Save Restore Regis-

ter 0 9LPCR

Logical Partitioning Control Register 5, 19, 21,48, 86

LPIDRLogical Partition Identification Register 7

LRLink Register 19, 21

MSRMachine State Register 10, 12, 22, 23, 62, 63,

65, 91optional 89PIR

Processor ID Register 21PURR

Processor Utilization of Resources Register 7,19, 21, 82

PVRProcessor Version Register 17, 21

RMORReal Mode Offset Register 6

SDR1Storage Description Register 1 19, 21, 37

Segment Registers 85


Version 2.02

SPRGnsoftware-use SPRs 16, 19, 21

SPRs 85Special Purpose Registers 19, 21

SRR0Machine Status Save Restore Register 0 9, 19,

21, 62, 63SRR1

Machine Status Save Restore Register 1 19,21, 62, 63, 72

status and control 85TB

Time Base 79TBL

Time Base Lower 19, 79TBU

Time Base Upper 19, 79XER

Fixed-Point Exception Register 19, 21relocation

data 27reserved field 2rfid instruction 10, 13, 63, 76RI

See Machine State RegisterRID (Resource ID) 89RMI

See Logical Partitioning Control RegisterRMLS

See Logical Partitioning Control RegisterRMOR

See Real Mode Offset Register

S

sc instruction 12, 73SDR1

See Storage Description Register 1SE

See Machine State Registersegment

size 25type 25

Segment Lookaside BufferSee SLB

Segment Registers 85, 93Segment Table

bridge 93sequential execution model

definition 2SF

See Machine State RegisterSingle-Step Trace 73SLB 33, 47

entry 33slbia instruction 50slbie instruction 49slbmfee instruction 52slbmfev instruction 52slbmte instruction 51

software-use SPRs 16, 19, 21Special Purpose Registers 19, 21speculative operations 27SPRGn

See software-use SPRsSPRs 85SR 93status and control registers 85stdcx. instruction 63, 66, 69, 70stmw instruction 69storage

accessed by processor 31consistency 26G 45Guarded 45implicit accesses 31interrupt vectors 31K 45key 45N 38, 45No-execute 38, 45ordering 26PP 45PR 45protection 45

translation disabled 46weak ordering 26with defined uses 31

storage controlinstructions 47

storage control bits 41Storage Description Register 1 19, 21, 37storage key 45storage model 26storage operations

in-order 27out-of-order 27speculative 27

storage protection 45stw instruction 105stwcx. instruction 63, 66, 69, 70stwx instruction 105symbols 97sync instruction 4, 43, 63synchronization 4, 57, 85

context 4execution 4interrupts 61

System Call interrupt 73System Reset interrupt 66system-caused interrupt 62

T

table update 57Time Base 79Time Base Lower 19, 79Time Base Upper 19, 79TLB 39, 47tlbia instruction 39, 55

Index 125

Version 2.02

tlbie instruction 39, 53, 56, 58tlbiel instruction 54tlbsync instruction 56, 57Trace interrupt 73translation lookaside buffer 39trap interrupt

definition 2

V

virtual address 32, 35generation 33size 25

virtual page number 36

W

Write Through Required 26

Numerics

32-bit mode 29


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PowerPC Operating Environment Architecture Book III Version 2mueller/cluster/ps3/SDK... · II, PowerPC Virtual Environment Architecture defines the storage model and related instructions

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