Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD) Power Management Reference Guide for Altera ® FPGAs and CPLDs 4Q 2004 R E A L W O R L D S I G N A L P R O C E S S I N G TM Powering Your FPGAs/CPLDs With TI’s Power Management Products FPGA/CPLD DC/DC Converters DC/DC Converters DC/DC Converters Supply Voltage Supervisor SD RAM and DATA CONV. V CCINT V CCIO Input Supply Power Design Library 2 Stratix ™ II Stratix ® GX Stratix ™ Cyclone ™ Max ® II Altera Power Requirements 3 Recommended DC/DC Converters 4 Product Selection Guides 20-21 Active Bus Termination 22-23 Inside ➔ www.ti.com/alterafpga
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Power Management Reference Guide for Altera FPGAs and CPLDs · Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD) Power Management Reference Guide
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Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD)
Power Management Reference Guidefor Altera® FPGAs and CPLDs
4Q 2004
R E A L W O R L D S I G N A L P R O C E S S I N GTM
Powering Your FPGAs/CPLDs With TI’s Power Management Products
FPGA/CPLD
DC/DCConverters
DC/DCConverters
DC/DCConverters
Supply VoltageSupervisor
SD RAMand
DATA CONV.
VCCINT
VCCIO
Input
Supply
Power Design Library 2
Stratix™ IIStratix® GXStratix™
Cyclone™
Max® II
Altera Power Requirements 3
Recommended DC/DC Converters 4
Product Selection Guides 20-21
Active Bus Termination 22-23
Inside➔
www.ti.com/alterafpga
Texas Instruments 4Q 2004 Power Management FPGA/CPLD Reference Guide
2 Power Management FPGA and CPLD Reference Guide
TI’s Power Management Reference Designs for Altera FPGAs and CPLDs
2
Design Library
➔
Complete schematics, bills of materials and additional designs available at:www.ti.com/alterafpga
Important Design Considerations..............................................................................................................................................................................................................5
6-A Core and I/O (Two PTH05050 Modules) Solution; 10-A, 15-A, 22-A, and 30-A Adaptable ....................................................................................................................6
20-A Core (TPS40007 DC/DC Controller) and 6-A I/O (TPS54610 DC/DC Converter) Solution; 8-A, 9-A I/O Adaptable ..............................................................................6
12-V Input Supplies
26-A Core (PTH12030 Module) and 12-A I/O (PTH12010 Module) Solution; 6-A, 10-A, 18-A Adaptable.....................................................................................................7
15-A Core and I/O (Two TPS40055 DC/DC Controllers) Solution ..................................................................................................................................................................7
Stratix GX/Stratix/Cyclone FPGA Core and I/O Power Solutions
3.3-V or 5-V Input Supplies
800-mA Core and I/O, Dual Low Dropout (LDO) Linear Regulator (TPS70402) Solution................................................................................................................................8
1-A Core and I/O, Independent LDOs (Two TPS725xxs) Solution ..................................................................................................................................................................8
3-A Core (TPS64203 DC/DC Controller), 1.5-A I/O (TPS78633 LDO) Solution................................................................................................................................................9
3-A Core and I/O (Two TPS64203 DC/DC Controllers) Solution ...................................................................................................................................................................10
20-A Core and I/O (Two TPS40021 DC/DC Controllers) Solution .................................................................................................................................................................11
12-V Input Supplies
3-A Core and I/O (Two TPS54350 DC/DC Converters) Solution....................................................................................................................................................................12
15-A Core and 10 A I/O, (Two TPS40055 DC/DC Controllers) Solution........................................................................................................................................................13
1.5-A LDO (TPS78633) Powering Both Core and I/O.....................................................................................................................................................................................16
3-A DC/DC Converter (TPS54350) Powering Both Core and I/O...................................................................................................................................................................17
Appendices
Texas Instruments Power Management Products Selection Guide..............................................................................................................................................................20
Active Bus Termination Solutions (DDR/QDR/GTL/SSTL/HSTL) ...................................................................................................................................................................22
Stratix II FPGA Power Requirements1
VCCINT (core voltage) 1.15 V min, 1.2 V typ, 1.25 V max ICCINT (core current) EP2S15: 5 A maxInrush to start-up included EP2S30: 7 A max
EP2S60: 9 A maxEP2S90: 11 A maxEP2S130: 15 A maxEP2S180: 20 A max
VCCPD (internal buffer voltage) 3.3 V typ, 300 mA maxICCIO (input/output voltages) 3.3 V, 2.5 V, 1.8 V and/or 1.5 V ICCID (input/output current) Up to 8 I/O banks @ up to 1.25 A eachTransient Response Requirements VCCINT shall remain within 1.15 V to 1.25 V
under these transient conditions:ICCINT < 8 A, load transient - 25% of ICCINT/µsICCINT ≥ 8 A but <12 A, load transient - 4 A/µsICCINT ≥ 12 A, load transient - 2 A/µs
VCCD_PLL 1.15 V min, 1.2 V typ, 1.25 V maxVCC_PLL_OUT 3.3 V, 2.5 V, 1.8 V, and/or 1.5 V ICC_PLL_OUT 50 mA (max)Digital(2) voltages above Analog voltages belowVCCA_PLL 1.15 V min, 1.2 V typ, 1.25 V max ICC_PLL 200 mA max per PLL,
Up to 12 each with separate VCC and GNDStratix and Stratix GX FPGA Power RequirementsVCCINT (core) 1.5 V ± 5%ICCINT (core) 250 mA to 10 AICCINT inrush to start-up EP1S10, EP1SGX10: 250 mA typ, 700 mA max
EP1S20: 400 mA typ, 1,200 mA maxEP1S25, EP1SGX25: 500 mA typ, 1,500 mA maxEP1S40, EP1SGX40: 650 mA typ, 2,300 mA maxEP1S60: 800 mA typ, 2,600 mA maxEP1S80: 1,000 mA typ, 3,000 mA max
VCCIO (I/O) 3.3 V, 2.5 V, 1.8 V and/or 1.5 VICCIO (I/O) Up to 8 I/O banks @ 50 mA to 1.5 A eachVCC_PLL_OUT 3.3 V, 2.5 V, 1.8 V and/or 1.5 VICC_PLL_OUT 50 mA (max)Digital2 voltages above Analog voltages belowVCCA_PLL 1.5 V ± 5%ICC_PLL 200 mA (max) per PLL
Up to 12 each with separate VCC and GND
33
➔
➔
Texas Instruments 4Q 2004 Power Management FPGA/CPLD Reference Guide
Power Management FPGA and CPLD Reference Guide
Introduction
Texas Instruments (TI) works closely with Altera to recommend robust power solutions. On this page you will find a summary of the FPGA/CPLDpower requirements. On page 3 is a comprehensive library of power designs. A listing of the TI DC/DC converter products that have been testedand endorsed by Altera® to power the listed devices is on page 4; schematics begin on page 5. Complete schematics and bill of materials(BOMs) are available at www.ti.com/alterafpga. Please send questions to [email protected].
This information is intended to provide the designer with a general understanding of the power requirements of Altera FPGA/CPLD families in typical applications. Please refer to the Altera Power Estimators, available at www.altera.com, for closer approximations specific to individualFPGA/CPLD devices and applications.
Power Requirements of Altera FPGAs and CPLDs
Additional Stratix GX Power RequirementsDigital Transceiver Voltage: VCCP, VCCG 1.5 V ± 5%ICC_Transceiver 250 mA (max) per transceiver
4 transceivers per blockUp to 5 blocks per device
Analog Transceiver Voltage: VCCR, VCCT 1.5 V ± 5%ICC_Transceiver 250 mA (max) per transceiver
4 transceivers per blockUp to 5 blocks per device
Analog Transmitter Voltage: VCCAQ 3.3 V ± 5%50 mA (max) per transceiver block
Cyclone FPGA Power RequirementsVCCINT (core) 1.5 V ± 5%ICCINT (core) 300 mA to 5 AICCINT inrush to start-up EC1C3: 300 mA max
EP1C4: 400 mA maxEP1C6: 500 mA maxEP1C12: 900 mA maxEP1C20: 1,200 mA max
VCCIO (I/O) 3.3 V, 2.5 V, 1.8 V and/or 1.5 VICCIO (I/O) Up to 4 I/O banks (50 mA to 1.5 A each)Digital(2) voltages above Analog voltages belowVCCA_PLL (two) 1.5 V ± 5%ICC_PLL 200 mA (max) per PLLMax II CPLD Power RequirementsVCCINT (core voltage) 2.375 V min, 2.5 V typ, 2.625 V max(2.5 V or 3.3 V supported on all Max II 3.00 V min, 3.3 V typ, 3.6 V maxwithout “G” ordering code. 1.8 V 1.71 V min, 1.8 V typ, 1.89 V maxsupported with “G” ordering code.)ICCINT (core current) EPM240: 30 mA typ, 75 mA max
EPM570: 40 mA typ, 125 mA maxEPM1270: 55 mA typ, 250 mA maxEPM2210: 75 mA typ, 400 mA max
ICCINT (inrush to start-up) 65 mA maxICCSTANDBY 12 mA typVCCIO (input/output voltages) 3.3 V, 2.5 V, 1.8 V and/or 1.5 VICCIO (input/output current) 25 to 50 mA each typ, 75 to 225 mA each max(up to 4 I/O banks)
1Stratix II advance information is based on Altera’s initial characterization of silicon, as of August 2004.2Digital voltages can be powered by linear or switching DC/DC converters. Linear regulators are recommended for analog voltages, for minimal noise.
4 Power Management FPGA and CPLD Reference Guide
TI Recommended DC/DC Converters For Powering Altera FPGAs and CPLDs➔
➔
Texas Instruments 4Q 2004 Power Management FPGA/CPLD Reference Guide
Complete schematics available at: www.ti.com/alterafpga
DC/DC Converter Selection Considerations
These recommended DC/DC converter products have been tested and endorsed by Altera to power the listed FPGAs. Max II CPLDrecommendations are preliminary pending testing. Digital voltages can be powered by either linear or switching DC/DC regulators. Linear regulators are recommended for analog voltages, for minimal noise. Please see the selection guides on pages 20 and 21 for electrical specifics of the recommended devices.
Stratix GXFPGA
Stratix IIFPGA
StratixFPGA
CycloneFPGA
Max IICPLD
compensation, resulting in a smaller solution due to the ability to minimize the inductor and use ceramic capacitors
- Exhibit switching noise- Up to 95% efficient, giving a much cooler solution than
a linear regulator, but due to the power dissipation inthe internal FETs, switching DC/DC converters supportonly up to about 9 A
• Switching DC/DC Controllers
- More cost-effective than DC/DC converters, but consume more board space and are more challenging to implement as they require the addition of externalFETs
- Can support high-current applications, limited only by the controller’s drive and the external FET’s powerdissipation capabilities
• Modules
- Easiest switching DC/DC solution available. The modulesolution is complete, needing only the addition of aninput and output capacitor for increased transientresponse
- Double-sided modules save board space- Full environmental qualification and EMI reports
are available
• Low Dropout (LDO) Linear Regulators
- Easiest, smallest, and most cost-effective type of DC/DCconverter to implement
- Typically just require the addition of a small inputcapacitor and output capacitor for stability
- Exhibit low noise and therefore are ideal for poweringanalog voltages
- Recommended for low power applications only due togenerally low efficiency (LDO Eff = VOUT/VIN x 100%) andresulting heat. Ensure the application does not violatethe regulator’s maximum allowable power dissipation.Refer to TI Application Note SLVA118 ‘Digital Designer’s
Guide to Linear Voltage Regulators and Thermal
Management’ for guidance.- Low dropout performance needed to support small
VIN to VOUT voltage differential
• Switching DC/DC Converters
- Easiest, smallest, discrete IC, switching DC/DC solutionto implement due to integration of the FETs
- Require the addition of an inductor and capacitors forthe output filter
- Use fixed output voltage, internally compensateddevices to minimize component count and simplifyimplementation
- Using adjustable output voltage TPS54xxx devicesinstead of fixed output options allows for external
Digital Voltages Analog VoltagesLow Dropout Switching Switching Low Dropout(LDO) DC/DC Converters DC/DC Controllers Switching (LDO) Linear Regulators (Integrated FET) (External FET) DC/DC Modules Linear Regulatorsto 1.5 A to 9 A to 20A to 30 A to 1.5 A
TPS79xxx TPS79xxxTPS786xx TPS54xxx TPS6420x PTH Series TPS786xxTPS725xx TPS400xx TPS732/6xxTPS703/4xx
TPS79xxx TPS79xxxTPS786xx TPS54xxx TPS6420x PTH Series TPS786xxTPS725xx TPS400xx TPS732/6xxTPS703/4xx
TPS79xxx TPS79xxxTPS786xx TPS54xxx TPS6420x PTH Series TPS786xxTPS725xx TPS400xx TPS732/6xxTPS703/4xx
TPS79xxx TPS79xxxTPS786xx TPS54xxx TPS6420x PTH Series TPS786xxTPS725xx TPS400xx TPS732/6xxTPS703/4xx
TPS736xx TPS62042 Max II is low power. Max II does not haveTPS786xx TPS54xxx LDOs and Switching Converters are recommended. Analog Supplies
Texas Instruments 4Q 2004 Power Management FPGA/CPLD Reference Guide
Important Design Considerations 5
➔
Stratix II 6-A Core and I/O3.3-V or 5-V Input DC/DC Converters (Two TPS54610) Solution ➔
• Highly efficient VCCINT railsup to 6 A
• Drop-in replacement of U1/U2 with TPS54810 orTPS54910 (VIN = 3.3 V) gives 8-A or 9-A solution, respectively
• SWIFT™ (Switcher withIntegrated FET) TPS54610adjustable design allows:•• Use of smaller inductor,
ceramic capacitors•• Flexibility to recompensate
depending on thebulk/bypass capacitorsused for the FPGA
• Fixed TPS5461x output voltage options available
• SWIFT design software isavailable for further customization
• UVLO and integrated soft-start of U1/U2 eliminate the need for an external SVS to monitor the input voltage• Sequencing of VCCINT, then VCCIO, then PLL minimizes the demand on the input supply• Additional rails easily added and sequenced using TPS54xxx PWRGD feature and enable• Adapt to 3.3-V supply:
Complete schematics available at: www.ti.com/alterafpga
• The shown power solutions are for applications guidance.Please visit the TI website for the latest updated information.
• Although Altera FPGAs do NOT require it, TI’s referencedesigns employ sequencing when possible, as well as a Supply Voltage Supervisor (SVS) to monitor the inputsupply. This practice is consistent with good power supplydesign and prevents the input power supply from beingpulled down due to in-rush currents for charging largecapacitive loads.
• VCCG_PLL powers the guard ring, which isolates the PLLfrom the rest of the device. VCCG_PLL should be connected to the quietest digital 1.5-V supply on the board, which is typically the device’s VCCINT supply.
• These designs meet Altera’s VCCINT and VCCIO start-up profile requirements, where applicable, including monotonic voltage ramp.
• Only the minimum input and output capacitors for eachIC are given in the schematics. Larger bulk and/or bypasscapacitors will be required between the input supply andDC/DC converters depending on the placement of theinput supply relative to the converters. Each FPGA alsorequires a minimum amount of bypass capacitance oneach power rail as specified by Altera.
Texas Instruments 4Q 2004 Power Management FPGA/CPLD Reference Guide
6-A Core and I/O Stratix II
Modular (Two PTH05050) Solution 3.3-V or 5-V Input
6
➔
➔
• Cost-effective high-currentsolution using U1 synchro-nous buck controller
U1/ U2 with TPS54810 orTPS54910 (VIN = 3.3 V)gives 8-A or 9-A solution,respectively
• SWIFT™ (Switcher withIntegrated FET) TPS54610adjustable design allows:•• Use of smaller inductor,
ceramic capacitors•• Flexibility to recompensate
depending on thebulk/bypass capacitorsused for the FPGA
• Fixed TPS5461x output voltage options available
• SWIFT design software isavailable for further customization
• UVLO and integrated soft-start of U1/U2 eliminate the need for an external SVS to monitor the input voltage• Sequencing of VCCINT, then VCCIO, then PLL minimizes the demand on the input supply• Additional rails easily added and sequenced using TPS54xxx PWRGD feature and enable• Adapt to 3.3-V supply:
•• Omit U2 circuit
Texas Instruments 4Q 2004 Power Management FPGA/CPLD Reference Guide
3-A Core and I/O Stratix GX/Stratix/Cyclone
DC/DC Controllers (Two TPS64203) Solution 3.3-V or 5-V Input
10
➔
• Tiny SOT-23 switchingDC/DC controller (U2, U3)delivers up to 3 A at ultra-low cost
• VCCINT soft-starts from internal soft-start of U2, minimizing inrush due tocharging capacitors
• Current Sense resistor R1and R4 give more precisecurrent limit; omit and connect ISNS to drain of Q1,Q2 to save cost and space
• External SVS provides noiseimmunity to start-up glitcheson 5-V supply
Positive Voltage, Single Output DevicesTPS731xx 150 30 400 1.2, 1.5, 1.8, 2.5, 3.0, 3.3, 5.0 1.2 to 5.5 1.7 5.5 1 ✔ EN, BP No Cap Reverse Leakage Protection 0.45TPS793xx 200 77 170 1.2, 1.8, 2.5, 2.8, 2.85, 3.0, 3.3, 4.75 1.2 to 5.5 2.7 5.5 2 ✔ EN, BP 2.2 µF C RF Low Noise, High PSRR 0.40TPS794xx 250 145 170 1.2, 1.8, 2.5, 2.8, 3.0, 3.3 1.2 to 5.5 2.7 5.5 3 ✔ ✔ EN, BP 2.2 µF C RF Low Noise, High PSRR 0.65TPS732xx 250 40 400 1.2, 1.5, 1.8, 2.5, 3.0, 3.3, 5.0 1.20 to 5.5 1.7 5.5 1 ✔ ✔ EN, BP No Cap Reverse Leakage Protection 0.65TPS736xx 400 75 300 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 1.20 to 5.5 1.7 5.5 1 ✔ ✔ EN, BP No Cap Reverse Leakage Protection 0.85TPS795xx 500 105 265 1.2, 1.6, 1.8, 2.5, 3.0, 3.3 1.2 to 5.5 2.7 5.5 2 ✔ EN, BP 1 µF C RF Low Noise, High PSRR 0.95TPS796xx 1000 200 265 1.2, 1.8, 2.5, 2.8, 3.0, 3.3 1.2 to 5.5 2.7 5.5 2 ✔ ✔ EN, BP 1 µF C RF Low Noise, High PSRR 1.05TPS725xx 1000 170 75 1.2, 1.5, 1.6, 1.8, 2.5 1.2 to 5.5 1.8 6 2 ✔ ✔ EN, SVS No Cap Low Noise 1.10TPS786xx 1500 390 265 1.2, 1.8, 2.5, 2.8, 3.0, 3.3 1.2 to 5.5 2.7 5.5 2 ✔ ✔ EN, BP 1 µF C RF Low Noise, High PSRR 1.30
1xx represents the voltage option. For example, 33 represents the 3.3-V option. 4C = Ceramic output capacitor; No Cap = Capacitor Free LDO. The adjustable output voltage option is represented by 01.
2EN = Active High Enable; BP = Bypass Pin for noise reduction capacitor; SVS = Supply Voltage Supervisor. 5Suggested resale price in U.S. dollars in quantities of 1,000.31.2 V fixed achieved by using the adjustable option and tying VOUT directly to the FB pin.
Min
V IN
Max
VIN
Accu
racy
(%)
Dual Output LDOs Output Options Features
VDO1 VDO2
IO1 IO2 @ IO1 @ IO2 Iq Fixed Voltage Accuracy PWP Min Max Low Min MaxDevice (mA) (mA) (mV) (mV) (µA) (V) Adj. (%) Package VO VO /EN PG SVS Seq Noise VIN VIN CO
1Suggested resale price in U.S. dollars in quantities of 1,000.
Switc
hing
Fre
quen
cy(m
ax) (
kHz)
Quie
scen
t Cur
rent
(typ)
(mA)
Shut
dow
n
Pow
er G
ood
Dual
Inpu
t Bus
(3.3,
2.5 V
)
Curre
nt L
imit
Texas Instruments 4Q 2004 Power Management FPGA/CPLD Reference Guide
Selection Guides
www.ti.com/alterafpga
21
➔Complete schematics available at: www.ti.com/alterafpga
Switching DC/DC Controllers VO VO Vref Driver Output Regulated
VIN (max) (min) Tol Current Current Outputs Device (V) (V) (V) (%) (A) Range (A) (#) Protection1 Comments Price2
Performance Processor Power Supply Controllers (Synchronous Rectification)TPS64203 1.8 to 6.5 6.5 1.2 2 0.150 0 to 3 1 OCP, UVLO Non-sync buck in SOT-23 0.50TPS40007 2.25 to 5.5 4 0.7 1.5 1 3 to10 (3.3 VIN) 1 OCP, UVLO 300-kHz switching frequency gives highest 0.99
3 to 20 (5 VIN) efficiency for lowest heatTPS40009 2.25 to 5.5 4 0.7 1.5 1 3 to10 1 OCP, UVLO 600-kHz switching frequency gives smallest 0.99
solutionTPS40021 2.25 to 5.5 4 0.7 1 1 10 to 20 1 OCP, UVLO Enhanced flexibility with user programmability 1.15TPS40055 8 to 40 35 0.7 1 1 3 to 20 1 OCP, UVLO Wide input range sync buck, source/sink 1.35TPS40061 10 to 55 45 0.7 1 1 1 to 10 1 OCP, UVLO Wide input range sync buck, source/sink 1.35
1OCP = over-current protection; UVLO = under-voltage lockout. 2Suggested resale price in U.S. dollars in quantities of 1,000.
Plug-In Power Solutions Input Bus POUT Isolated VO Range VO
Device1 Voltage or IOUT Outputs (V) Adjustable Price2
Non-Isolated Single Positive Output
PTH03010/20/30/50/60 3.3 V 15 A, 22 A, 30 A, 6 A, 10 A No 0.8 to 2.5 Yes 14.00, 18.15, 24.65, 9.10, 11.20PTH05010/20/30/50/60 5 V 15 A, 22 A, 30 A, 6 A, 10 A No 0.8 to 3.6 Yes 14.00, 18.15, 24.65, 9.10, 11.20PTH12010/20/30/50/60W 12 V 12 A. 18 A, 26 A, 6 A, 10 A No 1.2 to 5.5 Yes 14.00, 18.15, 24.65, 9.10, 11.20PTH12010/20/50/60L 12 V 12 A, 18 A, 6 A, 10 A No 0.8 to 1.8 Yes 14.00, 18.15, 9.10, 11.20
1See power.ti.com for a complete product offering.2Suggested resale price in U.S. dollars in quantities of 1,000.
TPS3808 1 Adj./0.9/1.2/1.5/1.8/2.5/ SOT-23 2.4 µA Prog ✔ — OD New. Adjustable delay from 1.25 ms to 10 s 0.703.0/3.3/5/0
TPS3809 1 2.5/3.0/3.3/5.0 SOT-23 9 µA 200 — — PP Small, low cost 0.29TLC77xx 1 Adj./2.5/3.3/3.0/5.0 SO-8, DIP-8, TSSOP-8 9 µA Prog — ✔ PP Universal SVS with broad voltage range and both 0.60
active-low and active-high resetTL7712A 1 12 SOIC, PDIP 1.8 mA Prog — ✔ OC For 12-V monitoring 0.50
1PP = Push-Pull; OD = Open Drain; OC = Open Collector.
2Suggested resale price in U.S. dollars in quantities of 1,000.
Man
ual R
eset
Inpu
t/MR
Act
ive-
Hig
hRe
set O
utpu
t
Rese
t Out
put
Topo
logy
1
Comments
Texas Instruments 4Q 2004 Power Management FPGA/CPLD Reference Guide
22 Active Bus Termination Solutions (DDR/QDR/GTL/SSTL/HSTL)
Tables➔
Active Bus Termination Plug-In Power Module Solutions Input Bus Isolated VO Range VO
Device Voltage POUT or IOUT Outputs (V) Adjustable Price1
PTH03010/50/60Y 3.3 V 6 A, 10 A, 15 A No 0.55 to 1.8 Yes 13.95, 9.95, 11.50PTH05010/50/60Y 5 V 6 A, 10 A, 15 A No 0.55 to 1.8 Yes 13.95, 9.95, 11.50PTH12010/50/60Y 12 V 6 A, 8 A, 12 A No 0.55 to 1.8 Yes 13.95, 9.95, 11.50
1Suggested resale price in U.S. dollars in quantities of 1,000.
Active Bus Termination Converter (with Integrated FETs) Solutions IOUT VIN Adj. VOUT Switching Frequency Pin Count Evaluation
TPS51100 3 LDO 10 1.2 to 3.6 2.5 to 1.8 ADJ 1/2 VDDQ 1/2 VDDQ Yes 10 MSOP 0.80PowerPAD™
1Suggested resale price in U.S. dollars in quantities of 1,000.
Texas Instruments offers a wide selection of Active Bus Termination solutions from LDOs and switching controllers to Plug-In Power. To aid in product selection, TI provides the solution recommendations in the tables below and offers various schematics as shown on page 15.
Texas Instruments 4Q 2004 Power Management FPGA/CPLD Reference Guide
Active Bus Termination Solutions (DDR/QDR/GTL/SSTL/HSTL)
Schematics
23
➔Complete schematics available at: www.ti.com/alterafpga
VDDQ = 2.5 V (DDR I), RDSCon Sense, Quick Discharge
GND
GND
GND
PTHxx050Y = 6 A, PTHxx060Y = 10 A, PTHxx010Y = 15 A
VINVBIAS
ENAPG
VSENSE
PGND
BOOT
LSG
PH
TPS543504.5 V to 20 V 3.3 V
SWIFT™
SOFTWARE
TOOL
R E A L W O R L D S I G N A L P R O C E S S I N GTM
Key Features• Operating input voltage range: 4.5 V to 20 V• 4.5-A peak MOSFET switch for high efficiency at 3-A
continuous output current• Uses external low-side MOSFET or diode• Output voltage adjustable down to 0.9 V with 1% accuracy• Wide PWM frequency – fixed 250 kHz, 500 kHz or adjustable
250 kHz to 700 kHz• Load protected by peak current limit and thermal shutdown• Internal slow start• Adjustable undervoltage lockout• Synchronizes to external clock• Packaging: Available in 16-pin PowerPAD™ TSSOP • Suggested resale price starts at $2.35 each in quantities of 1,000
Get samples, datasheets, app reports, EVMs and software tool at:www.ti.com/sc/device/TPS54350
TPS543504.5-V to 20-V Input, 3-A Step-Down Converter in TSSOP-16
TI Worldwide Technical SupportInternetTI Semiconductor Product Information Center Home Pagesupport.ti.comTI Semiconductor KnowledgeBase Home Pagesupport.ti.com/sc/knowledgebase
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