Power Management

Power Management Systems, System on Chip (SoC)

Power Management Systems, System on Chip (SoC)

Jyotirmoy GhoshJyotirmoy GhoshAdvanced VLSI Design Laboratory,Advanced VLSI Design Laboratory,Indian Institute of Technology KharagpurIndian Institute of Technology KharagpurEmailEmail-- [email protected]@iitkgp.ac.in

Power Management Group, AVLSI Design Lab, IITPower Management Group, AVLSI Design Lab, IIT--KharagpurKharagpur 2

ContentsWhat is power managementHow to decideDC-DC power converters■ LDO■ Inductor based switched mode converters

● Closed loop control■ Switched capacitor converters

Voltage regulator module■ Dynamic voltage scaling■ Current mode control■ Pulse skip mode

SOC implementation

Power Management Group, AVLSI Design Lab, IITPower Management Group, AVLSI Design Lab, IIT--KharagpurKharagpur

What is Power Management ?

3

A direct connection is not desirable.

Supply LoadVin VoutL, C, Power switches, etc.

Converter - Power Stage

Controller

An Example of a Power Management System: DC-DC Converter

2.5V-5.5V 1.2V


Domains of Power Management

4

DC to DC – Cell phones

DC to AC – Home inverter

AC to DC – Rectifier as in a PC supply

AC to AC - Transformer

Voltage Conversion

OthersBattery Charging – Cell phone chargers

Drivers – CFL and LED Drivers

Power Quality Improvement

And many more…


Typical applications

5


World wide Power Management

The market is expected to grow at a rate higher than most of other areas in IC design.

In many large analog companies, half of the business is in power management.


Example: Power Management Unit for a Notebook

7


How to choose?Input - Output Voltage RangeLoad current Voltage and Current RippleEfficiencyNature of ApplicationTransient RequirementsLoop BWEMIInput – Output IsolationBoard AreaCost…

8


DC-DC conversion techniques

9

Low Drop-Out Regulators

Inductor Based Switched Mode Power Converter

Switched Capacitor Converters


Low Drop-Out Regulator

10


Resistor divider

11

VinR2

R1 Vout

LOA

D

→ V’out

Can’t draw any current without causing extra drop!

inout VRR

RV21

1

+=


LDO – Low Drop Out regulator

12

The idea is to control R1.

VinR2

R1

Vout

Drop R2.

LOA

D

→V’out

Use feedback control to adjust the value of R1.

Controller

→ Vout

Consider Vin = 5.0 V; Vout = 1.0 V. Efficiency = ?


R1 to a MOSFET

13

Power MOSFET

Vin

(Acting as R1)

Vout

LOA

DController

→ Vout

Driver


Inductor Based Switched Mode Converter

14


Step down switching converter: Buck Converter

Buck Converter Circuit

Inductor Voltage

ON-state OFF-state

Ts

L0

DTs Ts

L L0 DTs

1 V dt 0Ts

V dt V dt 0.

(Vg Vo)DTs ( Vo)(1 D)Ts 0 Vo DVg

=

⇒ + =

⇒ − + − − =⇒ =

∫

∫ ∫

Applying volt-sec balance for the inductor:

VoDVg

=Conversion ratio of Buck Converter:Thus, this is a step-down conversion


Analysis of Buck Converter Cont..Inductor current ripple:

L

O

diInductor voltage current relation: V Ldt

During time interval dt D.Ts, change in inductor current di is i ;and voltage across the inductor is (Vg V )

=

=∆

−

OL

OL

OL O

(Vg V )DTsThus iL

(1 D)V Tsor, iL

VSince I IR

−∆ =

−∆ =

= =

L

L

i (1 D)RTsCurrent ripple factor I L∆ −

=


Analysis of Buck Converter Cont..

Output voltage ripple:Total charge transferred to capacitor that causes the voltage to swing from maximum to minimum:

2

Voltage ripple factor Vo (1 D)Ts

Vo 8LC∆ −

=

8LCD)T(1V

8CT∆i

C∆q∆V

8T∆i

2T

2∆i

21∆q

2SOSL

O

SLSL

−===

==


Inductor Voltage

From inductor volt-sec balance:

D)(1VgVor,

0D)Ts)(1V(Vg(Vg)DTs

O

O

−=

=−−+

D11

VgVO

−=

Boost Converter Circuit ON-state OFF-state

Conversion ratio of Boost Converter:

Thus, this is a step-up conversion

Analysis of Boost Converter


Analysis of Boost Converter Cont..Inductor current ripple:

diInductor voltage current relation: V=L

dt

During tiem interval dt= D.Ts

change in inductor current di is iL

and votlage across the inductor is Vg

∆

L

L 2

VgDTsThus, iL

Io Vo VgI(1 D) R(1 D) R(1 D)

∆ =

= = =− − −

L

L

2D.(1 D) RTsiCurrent ripple factor

I L

−∆=


Analysis of Boost Converter Cont..Output voltage ripple:Total charge transferred to capacitor that causes the voltage to swing from maximum to minimum:

O s

O s OO

q I DT

I DT V DTsqThus, VC C RC

∆ =

∆∆ = = =

O

O

V DTsVoltage ripple factor V RC∆

=


Cascading of Buck Converter and Boost Converter

Voltage conversion ratio:D1

DVgVO

−= when, Vg)(VO ≥ )5.0( ≥D

when, Vg)(VO < )5.0( <D

Non inverting Buck-Boost Converter


Switched Mode Converter in Closed Loop

22


Classical PWM Voltage mode control

23


Small signal model

24

T(s) = Gvd(s) . H(s) . Gc(s) . 1/VM


Switched Capacitor Converter

25


Step-up Conversion

Simple voltage doubler circuit

DDout

DDDDout

V2V or,CV)CV(V

:balance charge-capacitor From

==−

Voltage multiplier circuit – Dickson charge pump


Step-down Conversion

2IN

OUTVV =

3IN

OUTVV =

On-chip scalable voltage generationGood choice for very low power battery operated systemVoltage scaling below 1V


Comparison of three classes

Criteria LDO Inductor Based Switcher

Charge Pumps

Voltage Conversion Range

Only Buck1 All (buck, boost, inversion)

All (in discrete steps)2

Efficiency Low High High

Max Output Current Moderate3 High3 Low4

Vout ripple Negligible High High

Design Complexity Moderate High High

This is a basic comparison for typical members from each class and is only meant to give a rough idea. Depending on actual circumstances, exceptions may arise.


An application of Switching Converter:Voltage Regulator Module (VRM) for Processors



Technology Challenges

Stringent transient specifications

Low voltage and current ripple

Tight line and load regulations

High efficiency throughout the operation periods

Typical load transient waveform

Typical efficiency vs. load current waveform


Dynamic voltage scaling

Typical processor voltage and dynamically scaled processor voltage

LEAK2CC P CV losspower CPU += f

Advanced VLSI Design Lab, IITAdvanced VLSI Design Lab, IIT--KharagpurKharagpur 33

LOAD

DriverDeadband

Latch

PWM Comparator

Vref

Vf

Ve

PID

EA

Vout

Ri

IL

Faster dynamic response

Better stability

Better line regulation

PWM Current Mode Converter

Advanced VLSI Design Lab, IITAdvanced VLSI Design Lab, IIT--KharagpurKharagpur 34

Difference between VMC and CMC

EAPWM

d

ramp

Vref

V0

Voltage Mode Control

vcontrol

EAComp.

SVref

V0

vcontrol

Rclk

Qd

iL(t)

Current Mode Control

vcontrol

t

Inductor current


Low load efficiency

Pulse skip mode

Boost converter with pulse skip mode


SOC Implementation


Block diagram of buck converter & its different flavors

LOAD

DriverDeadband

LatchPWM Comp

Ramp Osc.

VREF

Error Amp

Compensator

Controller ICConverter IC Fully

Integrated Converter IC


Commercially where we are now?Controller IC: (Commercially most popular)■ As power circuits and compensator are external, it has lot of flexibility to

change the power circuits for various applications, value of L & C etc.■ But, it takes lot of area.

Converter IC: (Commercially moderately popular) ■ As, fixed power circuit are integrated in-side the chip, it can be used for

specific type of applications.■ As, compensator is also integrated, only specific value of L & C should be

connected as off-chip. ■ It takes much lesser area than the previous solution.

Fully integrated converter IC: (Commercially less popular/ mostly in research phase)■ Can be used for very specific applications. ■ It is most area efficient solution.■ But, it has lesser power efficiency due to the limitation of on-chip L & C.


Selection of switching frequencyAdvantages and Disadvantages of Higher Switching Frequency

Advantages:■ Enable smaller solution size

● Smaller inductor can be used with higher switching frequency to maintain the same current ripple

● Improve dynamic performance because of higher bandwidth of control loop

Disadvantages:■ Increase AC losses

● Gate drive loss● Switching loss● Dead time loss● AC loss of inductor

■ EMI impact


Selection of MOSFETs

40

• For a given die size, N-MOSFET offers low on-resistance and lower gate charge compared to P-MOSFET but requires “bootstrapped” drive circuit

• Tradeoff in selection: power loss, cost and package type (for discrete MOSFETs)• MOSFETs are characterized by its Figure of Merit (FOM) = Qg * RDS(on)

Vertical MOSFETs:High voltage blocking capabilityHigher packing density

Lateral MOSFETs:Lower gate chargeHigher current carrying capacity per unit cross sectional area at low voltageSuitable for low voltage, high current applicationsTerminals are readily available for connection with metal layers: suitable for on-chip implementation of DC-DC converters

Cross-section of vertical MOS

Cross-section of lateral MOS


Different losses in converter circuit

Conduction loss:■ Losses due to drain-source resistance of big power MOS■ Conduction loss ∞ RDS_on of the power MOS∞ 1/ Die size.

∆+=

12

22 IIDRP outonDScond **_

( ) swinGDGSGateDrive FVCCP **+=

Gate drive loss:■ Losses due to charging/discharging the highly capacitive gate

node of the power MOS.■ Gate driver loss ∞ Gate charge (Qg=Cg*Vin) ∞ Die size.


Transition loss:■ Losses across the power switch at the edge of transition.■ tr and tf are the rise and fall time of the switch node

respectively.■ Ipm and Ipp are the minimum and maximum peak value of

inductor current.

( )ppfpmrswintran ItItFVP *****. += 50

2

21

inDBDB VCP *=

Drain-bulk capacitive switching loss:■ Losses due to the parasitic drain-bulk capacitance of the

power MOS in the switch node.




Dead time loss:■ Losses due to the conduction of body diode of power MOS

during dead-time.■ VF is the diode forward voltage.■ tD_rise and tD_fall are the dead time at rising and falling edge

respectively.( )fallDriseDswoutFDiode ttFIVP __*** +=

rrswinrr QFVP **=

Body diode reverse recovery loss:■ Losses due to reverse recovery in the body diode of the low-

side power MOS .■ Qrr is the reverse recover charge.



Inductor loss:■ Loss due to the DC and AC resistance of the inductor.

12

22 IRIRP acoutdcInductor

∆+= **

12

2IRP ESRESR∆

= *

Capacitor loss:■ Loss due to the ESR of the capacitor.

Controller loss:■ Loss due to the quiescent current consumption in the

controller.

qinController IVP *=


Trade-off in optimizing different losses

How to fix the size of power MOS in a particular technology?■ Total power loss is minimum at the point where gate driver

loss and conduction loss is equal.■ This sizing maximizes the power efficiency.

Power dissipation (W)

Die size (mm2)

Optimal die size

Total loss

Gate driver loss

Conduction loss


Packaging issues

Typical value of bond-wire inductance is 1.5 nH – 4.8 nH.

For high speed converter (not necessarily high frequency converter), di/dt=1A/1nS.

So, assuming 2 nH bond-wire inductance, supply bounce is 2 V!

Solution: Use of lead-less package which eliminates the supply bounce.

+ *(di/dt)

-

+

-

Wafer

Package

PVDD

PGND

Vout

RLOAD

L

C

PMOS

NMOS

Gate Driver

LBONDWIRE

*(di/dt)LBONDWIRE

LBONDWIRE


Example of layout

47

Layout of a 20MHz dc-dc buck converter in a 0.5 µm process.

NMOS

PMOS

Controller

NMOS Driver

PMOS Driver


20 MHz DC-DC converter developed by IIT-Kharagpur- An example

AVDD PVDD

VFS1

VFS2

VTS1

VTS2

AGND PGND

SW

VFB

VTEST,ANA

VTEST,DIG

+−

CIN

C CBYPASS

L

VIN

VOUT

Typical application circuit

Die photograph


20 MHz DC-DC converter developed by IIT-Kharagpur- An example

PCB layout Evaluation board


Acknowledgement

50

Prof. Amit Patra, Department of Electrical Engineering, IIT KharagpurPower Management Group, AVDL

Rakesh Babu

Asif Eqbal

Pradipta Patra

Ashis Maity

Srikanth Pam

Rupam Mukherjee


Thank You


Robert W. Erickson and Dragan Maksimovic, “Fundamentals of Power Electronics,” Springer International Edition, 2006.B. Lynch and K. Hesse, “Under the hood of low-voltage dc/dc converters,” in Proc. Power Supply Design Seminar (SEM 1500), 2002.Jens Ejury,“How to Compare the Figure Of Merit (FOM) of MOSFETs,” Infineon Technologies Application Notes.Donald Schelle, Jorge Castorena, “Buck Converter Design Demystified,”Maxim Integrated Products.Everett Rogers, “Understanding Buck-Boost Power Stages in Switch Mode Power Supplies,” Application Report, Texas Instruments.Power Management technique for multimedia mobile phones. , no. 1, April 2006, Available at www.edn.com.J.M. Rivas, D. Jackson, O. Leitermann, A.D. Sagneri, Yehui Han, and D.J. Perreault, .Design Considerations for Very High Frequency dc-dc Converters,. Power Electronics Specialists Conference, 2006. PESC '06. 37th IEEE, pp. 1.11, 18-22 June 2006.

References


ReferencesMIC2285 Datasheet, Micrel Inc., 8MHz PWM Synchronous Buck Regulator

with LDO Standby Mode, Available at ww.micrel.com/\_PDF/mic2285.pdf.EP5362Q Datasheet, Enpirion, Inc., 600mA Synchronous Buck Regulators with Integrated Inductor, Available at www.enpirion.com.MIC2245 Datasheet, Micrel Inc., 4MHz PWM Synchronous Buck Regulator with LDO Standby Mode, Available at www.micrel.com/PDF/mic2245.pdf.MAX8460 Datasheet, Maxim Inc., 4MHz, 500mA Synchronous Step-Down DC-DC Converters in Thin SOT and TDFN, Available at www.maxim-ic.comTPS623XX Datasheet, Texas Instruments, 500-mA, 3MHz Synchronous Step-Down Converters in chip scale package, Available at www.focus.ti.com/lit/ds/symlink/tps62315.pdf.S. Abedinpour, B. Bakkaloglu, and S. Kiaei, .A Multi-Stage Interleaved Synchronous Buck Converter with Integrated Output Filter in a 0.18/spl mu/ SiGe process,. Solid-State Circuits, 2006 IEEE International Conference Digest of Technical Papers, pp. 1398.1407, Feb. 6-9, 2006.

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ReferencesB.J. Patella, A. Prodic, A. Zirger, and D. Maksimovic, .High-frequency digital PWM controller IC for DC-DC converters,. Power Electronics, IEEE Transactions on, vol. 18, no. 1, pp. 438.446, Jan 2003.Haifei Deng, A.Q. Huang, and Yan Ma, .Design of a monolithic high frequency fast transient buck for portable application,. Power Electronics Specialists Conference, 2004. PESC 04. 2004 IEEE 35th Annual, vol. 6, pp. 4448.4452 Vol.6, 20-25 June 2004.Yeong-Tsair Lin, Wen-Yaw Chung, Dong-Shiu Wu, Hung-Chan Wang, Hung-Yih Lin, and Jiann-Jong Chen, .A monolithic CMOS step-down DC-DC converter,. Circuits and Systems, 2005. 48th Midwest Symposium on, pp. 448.451 Vol. 1, 7-10 Aug. 2005.http://www.national.com/AU/design/courses/253/index.htm?start_file=swx07/01swx07.htm

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