Power Efficient Comparators for Long Arguments in Superscalar Processors

ISLPED 2003

Power Efficient Comparators for Long Arguments in Superscalar Processors

*supported in part by DARPA through the PAC-C program and NSF

Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose Department of Computer Science

State University of New YorkBinghamton, NY 13902-6000

http://www.cs.binghamton.edu/~lowpower

International Symposium on Low Power Electronics and Design (ISLPED’03), August 27th 2003

ISLPED 2003

Outline

Motivations8-bit comparator designs

Traditional ComparatorDissipate on Match Comparator (ICCD’02)

32-bit Comparator DesignsResults : Application to the Load-Store QueueConclusions

ISLPED 2003

Motivation

Equality comparators are very pervasive in today’s superscalar datapaths.

Wake-up logic of the Issue QueuesDependency checking logicLoad-Store queuesTranslation Lookaside Buffers (TLB)CachesBranch Target Buffers (BTB)

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Motivation (continued)

Traditional comparators dissipate energy on mismatches in any bit position of the arguments In many cases, mismatches are much more frequent than matches

Issue queue : Only 3% of all comparisons result in a match (Ergin et.al. , ICCD’02)

For energy efficiency, dissipate-on-match designs can be considered

ISLPED 2003

Traditional 8-bit Pull-Down Comparator

precharge

Evaluation

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Dissipate-on-Match Comparator (DMC, ICCD’02)

Propagation Precharge

Discharge

Evaluation

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Use of the Long Comparators

Load-Store queues – to allow loads to bypass earlier storesTLBs – for associative lookupCaches – for associative lookupBTBs – for associative lookup

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Traditional 8-bit Pull-Down Comparator

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Dissipate-on-Match Comparator (DMC)

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Comparison of larger operands : Some Alternatives

~270 ps ~270 ps

~270 ps >400 ps

>400 ps

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Choosing the Right Alternative

Need to consider impact on :DelayEnergy

Have to look at distributions of bit values that are comparedMore than one alternative may be acceptable

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Experimental Setup (AccuPower, DATE’02)

CompiledSPEC

benchmarksDatapath

specs

Performance stats

VLSI layoutdata

SPICEdeck

SPICE

MicroarchitecturalSimulator

Energy/PowerEstimator

Power/energystats

SPICE measures ofEnergy per transition

Transition counts,Context information

ISLPED 2003

0.4%

32.5%

22.4%23.7% 21.0%

8.2%

60.5%

8.7%14.0%

8.6%

68.1%

2.8%1.9%4.7%

22.6%

70.1%

4.1%1.7%0.7%

23.5%

0%

10%

20%

30%

40%

50%

60%

70%

80%

0 1 2 3 4

Number of matching bit pairs in each of the 4 8-bit groups

group of bits 0-7

group of bits 8-15

group of bits 16-23

group of bits 24-31

Matching Statistics of 32-bit Addresses in the LSQ

ISLPED 2003

Dissipate-on-Match Comparator (DMC)

ISLPED 2003

Matching Statistics of 32-bit Addresses in the LSQ

0.4%

32.5%

22.4%23.7% 21.0%

8.2%

60.5%

8.7%14.0%

8.6%

68.1%

2.8%1.9%4.7%

22.6%

70.1%

4.1%1.7%0.7%

23.5%

0%

10%

20%

30%

40%

50%

60%

70%

80%

0 1 2 3 4

Number of matching bit pairs in each of the 4 8-bit groups

group of bits 0-7

group of bits 8-15

group of bits 16-23

group of bits 24-31

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Energy savings in comparison of longer operands

19% Energy Increase 19% Energy Savings

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Main Results

We discussed some energy-efficient 32-bit wide comparator designs

19% comparator-related energy reduction in LSQ is achieved by using a hybrid design (3 TRADs + 1 DMC) compared to the use of 4 TRAD comparators

Results can be extended to TLBs and BTBs

ISLPED 2003

THANK YOU !

*supported in part by DARPA through the PAC-C program and NSF

LOW POWER RESEARCH GROUP Department of Computer Science

State University of New YorkBinghamton, NY 13902-6000

http://www.cs.binghamton.edu/~lowpower

International Symposium on Low Power Electronics and Design (ISLPED’03), August 27th 2003

ISLPED 2003

Timing Diagrams

ISLPED 2003

32-bit Matching Statistics: LSQ

0%

10%

20%

30%

40%

50%

60%

70%

80%

0 1 2 3 4 5 6 7 8

group of least significant 8 bits

group of bits 8-15

group of bits 16-23

group of most significant 8 bits

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Traditional 8-bit Pull-Down Comparator

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Pass Logic, Single-Stage Comparator (PLSSC)