Power Distribution Network Design for VLSI

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POWER DISTRIBUTIONNETWORK DESIGNFOR VLSI

QING K. ZHUIntel Corporation

Matrix Semiconductor Inc., U.S.A.

A JOHN WILEY & SONS, INC., PUBLICATION


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Copyright 2004 by John Wiley & Sons, Inc. All rights reserved.

Published by John Wiley & Sons, Inc., Hoboken, New Jersey.

Published simultaneously in Canada.

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Library of Congress Cataloging-in-Publication is available.

ISBN 0-471-65720-4

Printed in the United States of America.

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CONTENTS

Preface vii

1 Introduction 1

1.1 Power Supply Noise 21.2 Power Network Modeling 41.3 Modelling of Switching Currents 121.4 On-Chip Decoupling Capacitance 161.5 On-Chip Inductance 201.6 Process Scaling Impacts 281.7 Summary 32

2 Design Perspectives 33

2.1 Planning for Communication Chips 342.2 Planning for Microprocessor Chips 442.3 IBM CAD Methodology 552.4 Design forIR Drop 622.5 Package-Level Methodology 672.6 Summary 73

3 Electromigration 75

3.1 Basic Definitions and EM Rules 753.2 EM Analysis Tool 803.3 Full-Chip EM Methodology 833.4 Summary 85

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4 IRVoltage Drop 87

4.1 Causes ofIR Drop 87

4.2 Overview ofIRAnalysis 894.3 Static Analysis Approach 964.4 Dynamic Analysis Approach 994.5 Circuit Analysis withIR Drop Impacts 1034.6 Summary 103

5 Power Grid Analysis 105

5.1 Introduction 1065.2 Executing the Tool 1085.3 Advanced Static Analysis 1195.4 Dynamic Analysis 1255.5 Layout Exploration 1295.6 Summary 133

6 Microprocessor Design Examples 135

6.1 Intel IA-32 Pentium-III 1356.2 Sun UltraSPARC 1396.3 Hitachi SuperH Microprocessor 1416.4 IBM S/390 Microprocessor 1466.5 Sun SPARC 64b Microprocessor 1486.6 Intel IA-64 Microprocessor 1536.7 Summary 156

7 Package and I/O Design for Power Delivery 157

7.1 Flip-Chip Package 157

7.2 Simultaneous Switching Noise (SSN) 1597.3 Case Study of a Microprocessor-Like Chip 1677.4 Power Supply Measurement 1817.5 I/O Pads for Power/Ground Supplies 188

Glossary 191

References 199

Index 205

vi CONTENTS


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PREFACE

This book provides the detailed information on power distribution

network design in integrated circuit chips. Power distributionnetwork design is a critical part of the job in circuit design andphysical integration for high-speed chips.

TheIR drop and di/dt noise associated with the power distrib-ution networks are crucial to circuit timing and performance. Dueto the complexity of the millions of gates and interconnects inmodern VLSI chips, power network analysis is accomplished us-ing CAD tools. These tools take the layout database, usually inGDSII files, extract the RC parasitic for the power distribution

network, and model the current consumption for switching de-vices.

A fast circuit simulation is done for the electrical model of thepower distribution network in order to determine the IR drop orother supply voltage noises, as well as the current density of met-al power lines for checking electromigration failures.

In addition, the decoupling capacitors are inserted into thepower network for stabilizing the supply voltages in local regions

where current surges occur from time to time due to clock and log-ic operations. The decoupling capacitors and power distributionnetworks are required in some optimal form not only on-chip, butalso on the package and at system levels.

This book will explain the design issues, guidelines, examples,

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and CAD tools for the power distribution of the VLSI chip andpackage. The user guide of the VoltageStorm tool from CadenceDesign Systems, Inc. is referred to throughout [51], together withthe authors experience using this tool in designs.

The book is organized into seven chapters. Chapter 1 is an in-troduction to the power supply network, power network modeling,decoupling capacitors, and process scaling trends. Chapter 2 illus-trates the design perspectives for the power distribution network,including power network planning, layout specifications, decou-pling capacitance insertion, modeling and analysis of power net-works, and IR drop analysis and reduction. Chapter 3 explores

electromigration phenomena for the on-chip power distributionnetwork.

Chapter 4 discusses IR drop analysis methodology. It is takenprimarily from the VoltageStorm tool, using both static and dy-namic analysis methods. The static method is performed for somelevel worst-caseIR drop analysis without the knowledge of inputvectors at the chips primary inputs. Chapter 5 describes the com-mands and user interfaces of the VoltageStorm tool from Ca-dence Design Systems, Inc. [51]. Chapter 6 lists the microproces-sor design examples, with a focus on on-chip power distribution.Readers will gain the insights into industry chip design for powerdistribution networks from these examples.

Chapter 7 discusses the flip-chip and package design issues,since the package is a part of the global power distribution. A casestudy has been provided in this chapter for selecting the packageoptions, based on the performance requirements for the powersupply. Power network measurement techniques from silicon are

also discussed at the end of Chapter 7.A glossary of key words and basic terms is provided at the end

of the book to help understand the basic concepts in VLSI designand power distribution.

With the continually decreasing supply voltages and the in-creasing transistor switching currents on-chip, power supply nois-es on-chip remains the challenging issue for high-performancechip design. More and more research will be needed in the futurein CAD tools for switching current modeling and accurate powernetwork analysis. The design methodology for power delivery willneed to consider the performance, layout area, and package tech-nology optimization for future chips.

The author would like to thank Mr. George J. Telecki at John

viii PREFACE


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Wiley & Sons, Inc. for providing the chance to get this book pub-lished. He also thanks his co-workers in Intel Corporation, includ-ing David Ayers, Alex Waizman, and Bendik Kleveland. Finally,he appreciates the strong support from family members, includ-ing wife Huiling Song and two sons Phillip and Michael.

PREFACE ix


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Power Distribution Network Design for VLSI, by Qing K. Zhu 1ISBN 0-471-65720-4 2004 John Wiley & Sons, Inc.

As power supply voltage continues to drop with the VLSI tech-nology scaling associated with significantly increasing devicenumbers in a die, power network design becomes a very chal-lenging task for a chip with millions of transistors. The common

task in VLSI power network design is to provide enough powerlines across the chip to reduce the voltage drops from the powerpads to the center of the chip. The voltage drops are mainlycaused by the resistance or inductance of the power networkmetal lines.

The power network can be modeled as a low-pass filter with RLsegments in series, attached with capacitors at each end. The cur-rent sources of the switching gates and the intentional decouplingcapacitors are also inserted in the model. The IR drop is propor-

tional to the average current consumed by the circuit in the chip.TheL di/dt drop is proportional to the time-domain change ofthe current, due to the switching of logic gates in the chip opera-tions.

This chapter is organized into seven sections. Section 1.1 dis-cusses the general trend of power supply noise with the processtechnology scaling. Section 1.2 shows the modeling methodologyfor on-chip power networks. Section 1.3 discusses the switching

current modeling methodology for the power distribution net-work, which is critical for the accuracy of power grid analysis.Once we obtain the models, the power network can be character-ized as a linear network withR,L,C, and current sources, in or-der to solve the voltage distributions across the power network.

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Section 1.4 discusses a special topic in power network design:the decoupling capacitor optimization to allocate enough decou-pling capacitors between Vdd andVss nets, but not over-allocatingso as to result in enlargment of the die area. Section 1.5 discussesthe on-chip inductance effects on power network modeling. Weshow the metal configurations used in the power line design in or-der to minimize the inductance delay. In general, many thin-widthVdd andVss lines interleaved with each other in the powerdistribution network are preferred in order to minimize the areaof the return current loop or on-chip inductance.

Section 1.6 discusses process technology scaling impacts for the

future power network design. We discuss the technology scalingimpacts in two scenarios. Section 1.7 provides the summary tothis chapter.

1.1 POWER SUPPLY NOISE

Noise problems in microprocessor power distribution networkshave been discussed in the literature [1, 2, 3, 4, 5, 6]. The supplyvoltage is continually dropping in microprocessor design to reducethe power consumption and matche the reduced gate oxide thick-ness in the scaled IC process technology generations. Figure 1-1(a) shows the supply voltage drop trend in new technologies; andFigure 1-1(b) shows the gate oxide thickness reduction during theprocess scaling.

The on-chip decoupling capacitor is constructed by using thedummy transistors connected to Vcc with the gate, and Vss with

the drain and source. A conventional method for on-chip decou-pling capacitance allocation is based on a percentage (i.e., 10%)area in each layout window (e.g., 100 100 m) allocated for thedecoupling capacitance.

The decoupling capacitors are inserted near the large-sizebuffers, such as clock buffers or phase-locked loops. The conven-tional method, based on the layout area percentage, is not opti-mal, either being overestimated for a large layout area or under-estimated for meeting the power noise requirements.

The power distribution design techniques used for DEC Alphachips, such as the C4 package and on-chip power planes, can befound in [1]. The decoupling capacitance optimization technique,based on the layout floor plan graph and path-finding algorithm,

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can be found in [2]. The power network modeling and analysistechniques for PowerPC microprocessors can be found in [3]. Apower network modeling and simulation CAD tool is described in[4].

The reliability problems (i.e., electromigration) and CAD toolfor the power network are discussed in [5]. The basics of VLSIpower distribution can be found in [6]. The description of a high-performance power network scaling model and decoupling ca-pacitance optimization method is proposed in [7]. A criterion toinclude the inductance in on-chip interconnect modeling was dis-

1.1 POWER SUPPLY NOISE 3

(a)

0

0.5

1

1.5

2

2.5

0.25 0.18 0.13 0.1

Minimum feature size (m)

Supplyvoltag

e(V)

(b)

0

10

20

30

40

50

60

0.25 0.18 0.13 0.1

Minimum feature size (m)

Gateoxid

ethickness(A)

Figure 1-1. Power supply (a) and gate oxide scaling (b) trends.


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cussed in [8]. The VLSI design basic to the power network de-sign, such as metal sizing equations, can be found in [9]. Inter-connect scaling issues in the deep-submicron process can befound in [10].

1.2 POWER NETWORK MODELING

The layout and C4 package of a high-performance microprocessorpower network is illustrated in Figure 1-2. It is a five metalprocess, and M5 and M4 (the top two metal layers in this process)

are used for the full-chip power distribution, although signal linescan still be routed between the spaces between the power lines inthese top metal layers. Note that the local power networks are notshown in Figure 1-2; they will be routed on lower metal layers todeliver the power to the circuits.

The on-chip power lines are modeled inRLC segments, as illus-trated in Figure 1-3. Rvcc andLvcc are the unit-length resistanceand unit-length inductance (self and mutual) of the power line,multiplied by the line length between two nodes in the power grid.

Rd andCd are the resistance and capacitance in the series, usedto model the decoupling capacitor that is implemented by thedummy transistors.Is is the switching current of devices and it istime varying.Rs andCs represent the turn-on resistance and thecapacitance load of the devices connected at the power grid nodes(AC, BD, etc.).

The model in Figure 1-3 contains only the linear elements suchasR,L,C, and current sources. It suggests to us that a linear cir-

cuit simulator can be used to speed up the large-size microproces-sor power network analysis based on the proposed model. The keyparameters of decoupling capacitors (dummy transistors) areCdecap andRdecap, as shown in Figure 1-4.

The charges in Cdecap are used to help the supply voltage stabil-ity in Csw (switching gates) before the charges eventually comefrom the supply voltage source via the long current loop from thepackage.

To improve the efficiency of the decoupling capacitors, theRdecap needs to be sufficiently small. When Vcc is applied to thegate, as shown in Figure 1-5, the inversion channel is created be-tween the D and S with theRds-on resistance. TheRds-on resistanceis the 1/slope of the I/Vcurves of the resistor at Vds = 0V. The

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1.2 POWER NETWORK MODELING 5

Figure 1-2. Power distribution for high-performance microprocessors.


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Rds-on andCgate form a distributed RC network.Cgate is in serieswith two Rds-on/2 resistors connected in parallel, resulting inRds-on/4 added in series with Cgate, as shown in Figure 1-5.

The simulation of the power network depends on the accuracyand turnaround time of the power grid modeling. In most cases,only the resistance and capacitance of the power lines are needed,

6 INTRODUCTION

Vcc

Rdecap

Cdecap

Lvcc

Lvss

Rsw

Csw

SW

Vc(t=0)=Vcc

Vc(t=0)=

Vccdie

Vssdie

Cdecap>>Csw

RCdecap


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excluding the metal inductances for the on-chip power network.Many CAD tools are available for the purpose of extracting the in-terconnectRC for power grids, as summarized in Table 1-1.

The on-chip inductance for the power grid can be ignored by us-ing special design rules, shortening the return loop of Vdd andVssby using several interleaved Vss andVdd lines, as shown in Figure1-2, for example, to implement the power grid.

During the RC modeling process, each metal segment can be

represented in two forms as follows: (1) the lumped capacitiveparasitic, or (2) the distributedRC parasitic, as shown in Figure1-6(a). The lumped capacitive parasitic represents the total wirecapacitance from each driver circuit in the signal net. The distrib-utedRC parasitic includes the resistance (R) of the metal line inthe modeling.

Power grid modeling usually uses theRC model, since the met-al line resistance of the power grid is significant at the full-chip

level. A long metal line can be broken into multipleRC segments,as shown in Figure 1-6(b).


G=Vcc

DS

Rds_on

G=Vcc

Cgate

Rds_on/4

Rds_on/2 Rds_on/2

Cgate

Figure 1-5. Decoupling capacitor modeling.

Table 1-1. Well-knownRC extraction CAD tools

Tool Manufacturer

Fire & Ice Cadence Design Systems

Star-RCXT Synopsys

xCalibre Mentor Graphics

HyperExtract Cadence Design SystemsArcadia Synopsys

Columbus Sequence Design

Nautilus Cadence Design Systems

QuickCap Random Logic


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EachRC segment is modeled with a series resistor, togetherwith two capacitors at two ends of the resistor. The metal seg-ment capacitance is evenly divided by two capacitors. This is usu-ally called the PaiRC model since it looks like a pi () symbol, asshown in Figure 1-6(b).

The extractedRC data from the layout are saved in a standardparasitic format (SPF) file. It includes a list of nets and detailedRC values. TheR andC elements with the node names are speci-fied either as schematic-based labels or layout-based labels, de-pending on the options used in theRC netlisting stage.

The schematic node names are preferred in the SPF, since thisSPF can be back-annotated to the prelayout schematic netlist [33,

8 INTRODUCTION

(a)

(b)

RC

segment

Break

line 1

Break

line 2Break

line 3

Break

line 4

Net

RC:

pattern

matching

library

Figure 1-6. Lumped and distributedRC models.


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34]. In addition, the SPF can include the device section that mod-els the extracted devices from the physical layout.

In general, the capacitance can be formed between any poly-gons in the layout, although the closer ones have more significantcapacitances, and thus have more impact on the total capacitanceof the net. Figure 1-7 shows the possible capacitances between thegates and metal lines in the physical layouts.

The capacitance to the substrate is dominant over other cou-pling capacitances in the old one or two metals technology. Butthe situation changes in the latest submicron technology with sev-en to eight metal layers, since the top-level metals are far away

from the substrate, and the total capacitance of these top-levelmetals is more impacted by the coupling capacitances between ad-jacent lines in the same layer or adjacent layers of the layout.

In addition, the spacing between metal lines is continuallyscaled, so the coupling capacitance between neighboring metallines becomes more and more important. The calculation of the re-sistance or capacitance can be done through the direct solution ofthe well-known Maxwells EM equations or Greens functions[17].

A complex geometrical layout can require an extremely longcomputational time using the direct EM field solution. Therefore,


Figure 1-7. Coupling capacitances between conductors in a VLSI layout [33].


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equations or capacitance models are usually adopted in the capac-itance calculation for a large-scale layout.

Once the capacitance equations have been established, they areused in the RC extraction, which is fast enough to handle a large-scale layout. The RC extraction works on the physical databasetogether with the specified RC equations.

Let us review the basic resistance equation:

R = sl/w (ohm) (1-1)

In Equation (1-1), s is the sheet resistance in the unit of

ohm/square,l is the length of the line in m, and w is the width ofthe line in m.

Table 1-2 shows the sheet resistance data in a 0.18 m technol-ogy. Metal four and metal five have significantly lower resis-tances, making them suitable for long metal routes. The polysili-con and metal one layers have high resistance, making themsuitable for short metal connects.

The contacts or vias between metal layers, as shown in Figure1-8, are usually modeled as resistors. Each contact or via has a

fixed resistance based on design rules. The contact represents themetal hole between metal one to the diffusion or poly layer,whereas the via represents the metal hole between metal one andmetal two. Contacts or vias will introduce manyRC segments andsignificantly increase the RC parasitic file size and simulationtime.

The unit-length capacitance models are based on the results in[41] as follows.

a. Overlap capacitance: the bottom/top surface of one line tothe bottom and top surfaces of another line in two layers.Two lines are overlapped in the vertical direction. The over-lap capacitance is modeled as Ca =0r A/dl1l2, whereA isthe overlap area of line l1 andl2, 0 is the permittivity of free

10 INTRODUCTION

Table 1-2. Metal sheet resistances in 0.18

m technology

Layer Polysilicon Metal 1 Metal 2 Metal 3 Metal 4 Metal 5

Sheet 5.5 0.1 0.05 0.05 0.01 0.01

Resistance

( square)


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space (8.854 1014 F/cm2), r is the relative permittivity be-tweenl

1andl

2, and d

l1l2is the vertical spacing between two

lines.

b. Fringe capacitance: the side surface of one line to the bottomor top surface of another line in two layers. Two lines may ormay not be overlapped in the vertical direction. The fringecapacitance is modeled as Cfr =Cfr0 l (e

x1/x0 ex2/x0).x1 isthe distance from l1 (side edge) to l2 (near-end edge), andx2is the distance to l2 (far-end edge). l is the length of l1 (sideedge).Cfr0 andx0 are model coefficients that are character-

ized based on different vertical profiles. In a special case,two side edges may coincide in l1 andl2 (x1 = 0 and x2 =width of l2) and the model becomes Cfr =Cfr0 l (1 e

x2/x0).

c. Lateral capacitance: the side surface of one line to the sidesurface of the adjacent line in the same layer. The lateral ca-


Figure 1-8. Contacts and vias [9].


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pacitance is modeled as Clt =Fl1l2 (d) l, andFl1l2 (d) = C0 +C1/d +C2/d

2 +C3/d3 +C4/d

4.l is the parallel length of twoneighboring lines or conductors,Fl1l2 (d) is the lateral capac-itance per unit length, and d is the spacing between twolines.C0,C1,C2,C3, and C4 are coefficients that are charac-terized for the given process technology.

1.3 MODELING OF SWITCHING CURRENTS

The high current consumption in some regions of the die produces

hot spots. In these hot spots, significant current transition oc-curs and the power network voltage fluctuation will be high. Ac-curate transition current modeling and power network simulationare necessary to calculate the noise and temperature distribu-tions across the entire chip power network.

Figure 1-9(a) shows the current waveforms of multiple nearbydrivers with three combinations of the transition patterns forthese drivers. The simulation results are obtained when all dri-

vers are charging (case: ALL UP), all on discharging (case: ALLDN), and half are charging and half discharging (case: UP_DN).In Figure 1-9(a), the X-coordinate is the time (ns) and the Y-coor-dinate is the voltage (V).

The waveforms illustrate the need to include the driver transi-tion patterns (UP/DOWN) to model the transition currents. In oursimulation, a 295.2 m long bus with 130 signals is simulated inthe minimum M5 width and pitch. Figure 1-9(b) shows the circuitschematic to be simulated. Figure 1-9(c) shows the entire power

grid modeling for the simulation. Figure 1-9(d) shows the struc-ture of bus lines and Vcc/Vss lines on the M5 layer included in thesimulation.

In general, the total current consumptionI(t) of the CMOS cir-cuit shown in Figure 1-10 consists of three components:Id,Isc, andIl.Id is the charge or discharge current to the output load:

Id =CloadVccf (1-2)

In Equation (1-2), Cload is the total output load of the driver, in-cluding the gate load and interconnect load; Vcc is the supply volt-age; and fis the switching activity of Cload. Although the chargeand discharge dynamic currentId is a predominant component of

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the total current consumption, other two current components (Isc,Il) are still significant in the submicron CMOS process.

The short-circuit current Isc is due to the fact that pMOS andnMOS transistors are both in the transition region of the inverter.The leakage currentIl is due to the reverse-biased diodes leakagebetween the diffusion region and the substrate or well. Althoughthe sum of the short-circuit and leakage currents accounts for lessthan 15% of the total current consumption of the microprocessorchip, the percentage will go up in future CMOS processes.

Figure 1-10(b) shows the current waveforms based on the esti-mated current components; the waveform is assumed to be a tri-

1.3 MODELING OF SWITCHING CURRENTS 13

112pS

179pS

20.7pS

(a)

Figure 1-9. Switching noise simulation based on power grid modelling. (a) Sim-

ulation result. (Figure continues on next page)


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14 INTRODUCTION

(c)

M5

M6

(b)

VCCDRV

VSSDRV

VCC21

VSS21

Figure 1-9 (continued). (b) Simulated circuit. (c) M5 and M6 power grid model-

ling.(Figure continues on next page)


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1.3 MODELING OF SWITCHING CURRENTS 15

(d)

Figure 1-9 (continued). (d) Bus lines layout structure.

(a)

AVcc

Vss

B D

C

Cload

I(t)

(b)

tr

Tp/2

I(t)

ttf

i(n) i(p)

Tp/2

Figure 1-10. Modeling of switching currents.


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angle. The current waveforms are back-annotated into the powernetwork model, as shown in Figure 1-3. To improve the accuracyof the current waveforms, a current simulation tool such as Syn-opsys, Inc.s PowerMill can be used, although the result largelydepends on the (0, 1) patterns at the input ports.

1.4 ON-CHIP DECOUPLING CAPACITANCE

To prevent the supply level from collapsing when many gatesswitch simultaneously at the same clock transition, it is necessary

to add decoupling capacitors at hot spots to reduce the peakvoltage drops. These decoupling capacitors should be designedsuch that they do not occupy an excessively large area, whichwould decrease the yield.

It is important to realize that the on-chip decoupling capacitorsreduce the di/dt noise generated by the on-chip circuitry, but donot reduce the noise due to the simultaneous switching of off-chipdrivers. Placing many low-inductance decoupling capacitors onthe package and board to provide multiple low-inductance pow-er/ground pins for output buffers should minimize the transientnoise due to off-chip drivers.

If decoupling capacitors are placed, an upper limit or bound ofthe transient voltage fluctuation can be determined by modelingthe power lines behind the capacitor as an infinitely large induc-tor. Immediately after switching, based on the decoupling capaci-tor model, as shown in Figure 1-4, no current flows through thislarge inductor and a capacitance divider is established based on

the charge conservation law:

CdecapVCC = (VCC +V)(Cdecap +Csw)(1-3)

V= VCC

Based on Equation (1-3), to ensure a small voltage fluctuation V,theCdecap (decoupling capacitance) should be much larger than

theCsw (switching capacitance). Accordingly, for a microprocessorchip with a 14 nF load, we need 10 14 nF = 140 nF to achieve a10%Vdd power noise threshold in the worst case. Equation (1-3)provides the calculation of an upper bound of the total on-chip de-coupling capacitance to satisfy the voltage fluctuation Vbound.

Csw

Cdecap +Csw

16 INTRODUCTION


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The objective of the decoupling capacitance optimization problemis to minimize the total amount of decoupling capacitance as need-ed. Meanwhile, all the nodes in the power network model are satis-fied with the specified supply voltage noise thresholds. Formally,we can describe the objective and constraints as follows [83]:

Minni

(Cd)i Subject to V1V(ni)V2 (1-4)

In Equation (1-4), (Cd)i is the decoupling capacitance and V(ni) thevoltage at node ni of the power network model, as shown in Figure

1-3;V1 andV2 are the lower and upper thresholds required forfeasible supply voltages. We define a noisy node in the power net-work model as one in which, at some time, the voltage exceeds therequired [V1,V2] thresholds, as shown in Figure 1-11.

The thresholds are at the upper bound and lower bound awayfrom the nominal supply voltages to guarantee the correct circuittiming. For example, with a nominal voltage of 1.3 V and 10%away allowed, the upper and lower thresholds are [V1,V2] = [1.17V, 1.43 V].

The power network, with each nodes transient voltages in theelectrical model satisfying the given thresholds, is called afeasiblepower network. Adding the decoupling capacitors at noisy nodeswill turn a power network into a feasible one. Figure 1-12(a) shows

1.4 ON-CHIP DECOUPLING CAPACITANCE 17

1.43V

1.17V

Voltage waveform at the node

Thresholds

time

voltage

violation

1.3V: normal voltage

Figure 1-11. Supply voltage thresholds and noisy nodes definition [83].


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18 INTRODUCTION

(a)

Nominal voltage:

Vcc = 1.3V

Voltage thresholds:

Vcc:[1.17V - 1.43V]

Noisy nodes: Node 25 (min V = 0.47V)

Node 10 (min V = 1.15V)

(b)

Nominal voltage:

Vcc = 1.3V

Voltage thresholds:

Vcc:[1.17V - 1.43V]

Noisy nodes: None

Decoupling capacitors:

Node 25

Node 10

Figure 1-12. Adding decoupling capacitors at noisy nodes [83]. (a) Nodes 10 and

25 are noisy. (b) Adding more capacitors on Nodes 10 and 25.


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one example with the simulated voltages of two nodes (Node 25 andNode 10) in the power network.

The minimum voltages (0.47 V and 1.15 V) of these nodes areless than the required lower threshold (1.17 V), and thus they arenoisy nodes. The decoupling capacitor is added at each of thesetwo noisy nodes and the voltages eventually satisfy the requiredthresholds, as shown in Figure 1-12(b).

Figure 1-13 shows the high-level decoupling capacitance opti-mization flow [83]. Procedure I adds the decoupling capacitors atthe noisy nodes. Procedure II removes the unnecessary decou-pling capacitance overallocated initially.

We have done experiments on a power network model withabout 100RLC grids and decoupling capacitors. Current sourceshave been added at each node in the model for transistor transi-tions with the current waveforms, as shown in Figure 1-10(b). The

1.4 ON-CHIP DECOUPLING CAPACITANCE 19

Procedure I: Decoupling Capacitance Increment

Simulate the power network model withRLC

elements and current sources.Identify the noisy nodes by comparing the voltage results with the specified thresholds.

While (there is noisy node){

For (each noisy node){

Add a step size of the decoupling capacitance.

}

Simulate the power network model with the updated decoupling capacitance.

Identify noisy nodes by comparing simulation voltages with the required thresholds.

}

Procedure II: Decoupling Capacitance Decrement

For (each node){

Mark the node as deductible;

}

While (there is still deductible node){

Deduct a step size of decoupling capacitance from each deductible node;

Simulate the power network model with the updated decoupling capacitance;

Identify the noisy nodes by comparing simulation voltages with the required thresholds;

For (each noisy node){

Add a step size of the decoupling capacitance;Make the node as nondeductible;

}

}

Figure 1-13. Decoupling capacitance optimization flow [83].


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cycle time is 3 ns or 330 MHz frequency in the experiments. Twovoltage sources are added to model the C4 package power pads.TheRL parasitic (200 and 0.5 nH) of the package layer are in-cluded in the model. The nominal supply voltage is 1.3 V.

The power grid simulation is done using a fast linear circuitsimulator [20]. The flow shown in Figure 1-13 is used to deter-mine the locations and amounts of on-chip decoupling capacitors.Figure 1-14 shows the experimental results for a sensitivity studyto decoupling capacitances. The decoupling capacitance is mostsensitive to the changes in the noise margin and device transitioncurrents.

This suggests to us that the model of the current consumptionis the key to getting the accurate voltage drop and decoupling ca-pacitance amounts. In addition, we want to reduce the on-chipdecoupling capacitance size by improving the noise margin. Thiscan be achieved by improving the power distribution on thepackage and the board. The changes of power line RLC values,as well as the absolute supply voltages with the same noisethresholds, do not show significant impact on the decoupling ca-pacitance.

In the experiment, we assigned the initialRLC values at eachnode of the power network as follows:R = 40 ,L = 0.005 nH, C =0.3 pF (without the decoupling capacitance at this initial assign-ment). The change of on-chip power line inductance does not leadto a lot of variation in decoupling capacitance, as shown in Figure1-14(b); this is due to the very smallL/R delay (0.12 ps) comparedto theRC delay (12 ps) in this example.

The decoupling capacitor can be improved by using either the

PN junction or a MOS varactor device [43]. As shown in Figure 1-15(a), the PN junction is formed by diffusing p+ doping in an n-well. As shown in Figure 1-15(b), the MOS varactor is formed byplacing an nMOS in an n-well. The n-well is added to form a chan-nel between the source and drain. In addition, Vtune andVgate volt-ages are controlled to vary the gate capacitance used for the de-coupling capacitances between Vdd andVss.

1.5 ON-CHIP INDUCTANCE

The inductive drop or noise (L di/dt) on the power lines becomessignificant for high-speed microprocessor chips [14, 15], especially

20 INTRODUCTION


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1.5 ON-CHIP INDUCTANCE 21

(a)

0

50

100

150

200

250

300

350

400

450

0% 10% 20% 30% 40% 50%

Line Resistance Increasing Rate

DecouplingCapacita

nce(pf

Vcc = 0.15V

Vcc = 0.075V

Vcc = 0.00375V

(b)

0

50

100

150

200

250

300

350

400

450

0% 10% 20% 30% 40% 50%

Line Inductance Increasing Rate

Decoup

ling

Capacitance

(pf)

Vcc = 0.15V

Vcc = 0.075V

Vcc = 0.0375V

Figure 1-14. Sensitivity study of on-chip decoupling capacitances [83]. (Figure

continues on next page)

(c)

0

50

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150

200

250

300

350

400

450

0% 10% 20% 30% 40% 50%

Load Capacitance Increasing Rate

Decoupling

Capacitanc

e

(pf)

Vcc = 0.15V

Vcc = 0.075V

Vcc = 0.0375V


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22 INTRODUCTION

(d)

0

100

200

300

400

500

600

700

0% 10% 20% 30% 40% 50%

Is (Current Source) Increasing Rate

DecouplingCapacita

nce(pf)

Vcc = 0.15V

Vcc = 0.075V

Vcc = 0.0375V

(e)

0

50

100150

200

250

300

350

400

450

0% 10% 20% 30% 40% 50%

Vcc Increasing Rate

Decouplin

gCapacitance(pf)

Vcc = 0.15V

Vcc = 0.075V

Vcc = 0.0375V

Figure 1-14 (continued).

(f)

0

50

100

150

200

250

300

350

400

450

0% 10% 20% 30% 40% 50%

Vcc Increasing Rate

Decoupling

Capacitance

(pf

Vcc = 0.15V

Vcc = 0.075V

Vcc = 0.0375V

0

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200

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300

350

400

450

0% 10% 20% 30% 40% 50%

Vcc Increasing Rat

D

ecoupling

Capacitance

(pf)

Vcc = 0.15V

Vcc = 0.075V

Vcc = 0.0375V


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when the chip becomes faster and larger in size. The characteris-tic impedance isZ0 =L/C. Adding decoupling capacitors will in-crease the capacitance but does not affect the inductance of thepower planes. As a result,Z0 is reduced, and current spikes gener-ate smaller voltage drops because V=Z0I

Low impedance of the power network helps the pulse responseand curbs the instantaneous fluctuations. The impedance Z0 canbe further reduced by lowering the inductanceL of the power net-work. This section presents a metal wire design method to reducethe inductance by carefully selecting the sizes and spaces of pow-er lines.

Figure 1-16(a) shows five different combinations of the widthsand spaces for two adjacent Vcc andVss lines [21]. The inductanceand resistance of these five combinations are shown in Figure1-16(b) and Figure 1-16(c) for 10,000 m long power lines. The in-

ductance is calculated by using a two-dimensional model with thecurrent loops between adjacent Vss andVcc lines. The first-orderestimation of the unit-length loop inductance for two adjacent VccandVss lines is as follows:

L = (1-5)

In Equation (1-5), is the permeability of the dielectric material

between adjacent Vcc andVss lines,s the space between the VccandVss lines, and w the width of Vcc orVss lines. The Vcc andVddnets are interchangeable in this book. Usually, Vcc is used for theanalog signal and Vdd for digital design.

The inductance becomes large when the line space is big, which

sw


Figure 1-15. Decoupling capacitor [43]. (a) PN Junction. (b) MOS varactor.


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24 INTRODUCTION

(a)

Case 1 Medium width pair of

minimum spaced M5

4.24

M5

0.8

Vcc

Case 2 Try half width pair of

minimum spaced M5

2.12

M5

0.8

Vcc

Case 3 Narrow width pair of

minimum spaced M6

1.64

M6

0.84

Vcc

Case 4 Wide minimum spaced M6

lines pair

37

M6

0.84

Vcc

Case 5 Spread out medium width

M5

4.24

M5

22

Vcc

(b)

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

1.2

1 10 100 1,000 10,000

Freq [MHz]

L

[nH/10

00u]

4.24

M5

0.8

2.12

M5

0.8

1.64

M6

0.84

37

M6

0.84

4.24

M5

22

Figure 1-16. Characterization results of Vdd/Vss metal structures [21]. (a) VccandVss cases. (b) On-chip inductance characterizations.


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(c)

16.5

14.2

27.626.626.3

30.830.8

5.92

3.971.3

13.2

0

5

10

15

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25

30

35

1 10 100 1,000 10,000

Freq [MHz]

R[/

1000u]

4.24

M5

0.8

2.12

M50.8

1.64

M6

0.84

37

M6

0.84

4.24

M5

22

(d)

16.5

14.2

27.626.626.3

30.830.8

5.92

3.971.3

13.2

0

5

10

15

20

25

30

35

1 10 100 1,000 10,000

Freq [MHz]

R[/1000u]

4.24

M5

0.8

2.12

M50.8

1.64

M6

0.84

37

M6

0.84

4.24

M5

22

Figure 1-16 (continued). (c) Resistance characterizations. (d) Impedance calcu-

lation.(Continued on next page)


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is opposite to the case of line-to-line capacitance coupling. Case 5has far more inductance than any other cases, since it has a largeline-to-line space. More magnetic coupling is caused by two con-ductors in the far distance and that is one of difficulties in accu-rate inductance modeling.

The inductance is reduced at high frequencies because timevarying currents tend to concentrate near the surface of the con-ductors at high frequencies; this is known as theskin effect [6].

As a consequence of this electromagnetic induction phenome-non, the magnitude of the current density drops exponentiallywith the distance away from the surface. The distance at whichthe current density becomes a fraction 1/e of its value at the sur-face is calledskin depth, which is calculated by

s = (1-6)In Equation (1-6),fis the frequency, and and are the perme-ability and resistivity of the material. Making the thickness of the

f

26 INTRODUCTION

(e)

391.97 391.97 391.97 391.97 391.97 384.17341.45

264.67

178.14

39.09

95.72

57.94

391.97

90.15

10

100

1,000

1 10 100 1000 10000

Freq [MHz]

[pS]

15.55

18.78

4.24

M5

0.8

2.12

M50.8

1.64

M6

0.84

37

M6

0.84

4.24

M5

22

Figure 1-16 (continued). (e)L/R delay.


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conductor larger than approximately 2s will not reduce the effec-tive resistance of the line.

Figure 1-16(c) shows the resistance plots over the frequency forthe five line configurations shown in Figure 1-16(a). The skin ef-fects are observed at the higher frequencies with the increased re-sistances for all configurations. Case 4, shown in Figure 1-16(c),which has the largest width, shows the skin effect at the lowestfrequency due to its large width.

The impedance of a power line is calculated as follows:

|Z(f)| = R2+ (2fL)2 (1-7)

In Equation (1-7), fis the clock frequency and R andL are unit-length line resistance and unit-length line inductance. Figure 1-16(d) shows the impedance as the frequency functions of the VccandVss line configurations shown in Figure 1-16(a).

At the high frequency, the impedance is rising, especially forCase 5, due to the inductance effect, as shown in Figure 1-16(d).Case 4, shown in Figure 1-16(a) with the largest wire width and

small line space, has the smallest impedance.Theinductance delay due to the line inductance and line resis-tance is calculated as follows:

= L/R (1-8)

TheL/R delay characterizes the importance of the inductance inpower network modeling. Figure 1-16(e) shows theL/R delay re-sults; Case 2 and Case 3, with small line widths and small line

spaces, have the smallest L/R delay, as small as 1519 ps for a10000m long power line.

If the L/R delay is much smaller than the RC delay per unitlength, the line inductance Lvcc orLvss can be ignored in the on-chip power network model. In this condition, the RC network isaccurate enough to model the on-chip power network.

Based on the experimental results shown in Figure 1-16(e), wecan conclude that narrow and dense lines are preferred in the

power network design for metal inductance reduction. Howeverother effects, like theIR drop, need to be considered as well.Just considering how to reduce the inductance effect through

wire sizing is not very useful since the inductance is still dominat-ed by the package in modern chips. But we can use dense and nar-row lines for reducing both on-chip inductance and resistance. An



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example is shown in Figure 1-17. The inductance is obviously re-duced based on our experiments.

The resistance of these narrow lines combined is equal to, or lessthan, a wide line. The example in Figure 1-17 shows a practicalguideline used in the Intel microprocessor power network design.

1.6 PROCESS SCALING IMPACTS

We have considered two scenarios for the technology scaling inmicroprocessor chips. Scenario A scales the existing chip to a new

process with a scaling factor S with little logic change. In ScenarioA, die size is reduced by S2. Scenario B scales the existing chip toa new process with lots of new logics implemented.

In Scenario B, the die size is assumed to be unchanged whenusing the new process due to more transistors employed in thenew design. Table 1-3 shows the impact on the microprocessorpower distribution of using the above two scaling scenarios for themicroprocessor chips. The detailed derivations are given below.

Scenario A

The line width and space are both reduced by S, assuming theline thickness change is negligible in process shrinking. The unit-length resistance is increased by 1/S. The unit-length capacitanceis reduced in S by assuming that the plate capacitance is reducedby 1/S2 but the coupling capacitance increases by 1/S due to thesmaller line space.

28 INTRODUCTION

Vcc Vss

Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss

Preferred

Vcc Vss

Vcc VssVcc Vss Vcc VssVcc Vss Vcc VssVcc Vss Vcc VssVcc Vss Vcc VssVcc Vss

Preferred

Figure 1-17. Design guidelines for on-chip power lines.


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The die size is reduced by S2, and the length of power lines is

scaled in S. The line resistance for the power network is notchanged, and the line capacitance for the power network or longsignal lines is reduced by S2.

Based on Equation (1-5), the unit-length inductance betweentwo adjacent Vcc and Vss lines is not changed, because the line space(s) and line width (w) are both reduced by S. The total line induc-tance is reduced in S, due to the power line length scaled in S.

Chip clock frequency is assumed to increase by 1/S2, which is asimplification of the fact that the microprocessor frequency will

roughly double every two years for the next process generation. InScenario A, the logic of the chip is changed very little and thenumber of toggling transistors per clock cycle is kept unchanged.

The channel length and width of each device are both scaleddown in S. The average gate capacitance is down by S2. So the total

1.6 PROCESS SCALING IMPACTS 29

Table 1-3. Technology scaling model for microprocessor power distribution

Design Parameters Scenario A Scenario B

Dimensions Die size S2 (down) UnchangedTransistor count Unchanged 1/ S (up)

Metal width S (down) S (down)

Metal space S (down) S (down)

Metal thickness Unchanged Unchanged

Global metal length S (down) Unchanged

Decoupling capacitance bound S2 (down) Unchanged

Area % of decoupling capacitor Unchanged Unchanged

RLC Metal resistance Unchanged 1/S (up)

Parameters Metal capacitance S2 (down) S (down)

Loop inductance S (down) Unchanged

Clock frequency 1/S2 (up) 1/ S2 (up)

Toggling transistors per cycle Unchanged 1/S (up)

Average gate capacitance S2 (down) S2 (down)

Total gate capacitance S2 (down) S (down)

Total signal connections Unchanged 1/ S2 (up)

Total wire capacitance S2 (down) 1/ S (up)

Total toggling capacitance S2 (down) Unchanged

Power Power consumption (total) S2 (down) Unchanged

Consumption Supply current (total) S (down) 1/ S (up)Current density on power line Unchanged 1/ S2 (up)

Voltage Supply voltage S (down) S (down)

Drop IR drop S (down) 1/ S2 (up)

L Di/Dt drop S2 (down) 1/ S (up)


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gate capacitance is down by S2. Since the total wire capacitance ofsignals is also down in S2, with unchanged transistor numbers andsignal connections, the total toggling capacitance (C

toggle

=Cgate

+Cwire) of the chip is reduced by S

2. The supply voltage is scaled in S

at each process generation, as shown in Figure 1-1(a).The power consumption can be estimated as: 0.5 fV2dd

Ctoggle, wheref= clock frequency, Vdd = supply voltage, and Ctoggle= total toggling capacitance of the chip. The power consumption isreduced by S2 based on the above assumptions for the frequency,supply voltage, and the total toggling capacitance per clock cycle.

The current of the power distribution network is calculated by

the power consumption divided by the supply voltage. Since thepower is down by S2 andVdd is down by S, the current is thusdown by S. Since the line width is down by S and current down byS, the current density of the power line is not changed.

The IR drop is down by S, since the line resistance is notchanged but the current is reduced in S. The L di/dt voltagedrop is reduced by S2 because the line inductanceL is scaled downbyS;di (current) is reduced by S for the same dt period.

Based on Equation (1-3), we got the bound of the total on-chipdecoupling capacitance with 10 times the total toggling capaci-tance to achieve 10% Vdd noise bound. Because the total togglingcapacitance is reduced by S2, the upper bound of the total decou-pling capacitance needed in the chip is also reduced by S2.

Since the die size is reduced by S2 in Scenario A, the percentageof die size used for the on-chip decoupling capacitance is notchanged in this scenario.

Scenario B

The die size is assumed to be not changed in this scenario, so theglobal line length is not changed. The line resistance of the powernetwork is increased by 1/S. The line capacitance of the powernetwork, or long signals, is reduced in S, since the unit-length ca-pacitance is down in S, as derived in Scenario A.

Based on Equation (1-5), the unit-length inductance between

two adjacent Vcc andVss lines is not changed due to the line space(s) and the line width (w), both reduced by S. The total line induc-tance is not changed because the global line length is not changed.

The chip clock frequency is supposed to increase by 1/S2 aboutevery two years for each process generation. In Scenario B, new

30 INTRODUCTION


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logic features are implemented, assuming employment of 1/S

more transistors in the design. Therefore, the total toggling tran-sistors per cycle increases by 1/S.

The gate channel length and channel width are both scaleddown by S, so each gate capacitance is down by S2 and the totalgate capacitance is down by S. The total signal number is in-creased by 1/S2, for 1/S more transistors used in the design. Thisimplies that the total wire capacitance of signals in this chip is in-creased by 1/S, based on the unit line capacitance in this scenariobeing reduced by S.

If we assume that the total wire capacitance is almost equal to

the total gate capacitance across a chip (and that is the case wefound in a microprocessor chip), we get the unchanged total tog-gling capacitance, Ctoggle (Ctoggle =Cgate +Cwire). The supply volt-age is reduced in S at each process generation.

The average power consumption is calculated by 0.5 fV2dd Ctoggle, wheref= clock frequency, Vdd = supply voltage, and Ctoggle= toggling capacitance. The power consumption is unchanged inthis scenario. The current through the power distribution net-work is calculated by the power consumption divided by the sup-ply voltage. Since the power is unchanged and Vdd is down by S,the total current increases by 1/S.

Because the wire width is down by S and current increases byS, the current density of the power network increases by 1/S2. TheIR drop increases by 1/S2, due to the line resistance increasing by1/S and the supply current also increases by 1/S. The L di/dt

noise increases by 1/S sinceL not changed; di (current) increasesby 1/S for the same dt period.

Because the total toggling capacitance per cycle is unchanged,the upper bound of the total on-chip decoupling capacitance isalso unchanged, based on Equation (1-3). Since the die size is notchanged in Scenario B, the area percentage used for the on-chipdecoupling capacitance is also unchanged.

Although the scaling models show unchanged power consump-tion in Scenario B, for most new microprocessors we see more ag-gressive transistor number increase or more parallelism used forhigher performance. This observation results in more power con-sumption in new microprocessors. For example, Alpha 21264(0.35m) has 1.63 times more transistors than Alpha 21164 (0.50m) (> 1/0.7 = 1.42 scaling factor assumed in Scenario B), and thepower consumption is increased from 50 W to 72 W [1].

1.6 PROCESS SCALING IMPACTS 31


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Process scaling factor S in Table 1-3 is the ratio of the mini-mum feature sizes between two process generations. S is about0.7 [10]. For example, an 0.18 m process is scaled to 0.13 m fora scaling factor S of about 0.72 (0.13/0.18 = 0.72).

1.7 SUMMARY

This chapter discusses the modeling issues of on-chip power grids.It provides the primary models and characterization results forthe resistance, capacitance, and inductance associated with metal

lines and vias to route the power distribution network on the chip.The power distribution network, in general, can be characterizedas a low-passRLC filter for the frequency domain analysis.

In addition, the resonant frequency should be removed from theworking frequency of the circuit; otherwise, thisRLC network willgenerate a lot of noise. We describe the inductance effects for theon-chip power grid. Usually, very dense and narrow width Vss andVcc lines are interleaved with each other to reduce the inductance.

In general, as a designer of a power grid, you want to increasethe capacitance while reducing the resistance and inductance.The latter two parameters are associated with theIR drop andL di/dt noise.

The capacitance increase for a power grid is implemented byadding intentional decoupling capacitors. In addition, decouplingcapacitors are inserted at the noisy nodes of the power distribu-tion network. A CAD algorithm has been proposed to automatethis decoupling capacitor insertion process [83].

Finally, we predict future design directions by providing tech-nology scaling models related to power distribution performanceand voltage drop based on two different chip improvement scenar-ios.

32 INTRODUCTION


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Power Distribution Network Design for VLSI, by Qing K. Zhu 33ISBN 0-471-65720-4 2004 John Wiley & Sons, Inc.

In this chapter, we describe guidelines for chip layout and floorplanning in power grid design. Enough metal power lines shouldbe allocated for both the global power network and local power

network in all metal layers in order to deliver current efficientlythrough the power network. However, power grids or metal linesused for Vdd andVss networks will use up a lot of signal routingresources.

Therefore, there is an intention from the circuit design perspec-tive to ignore the power network metal density at the planningstage in order to reduce the metal layers or reduce the chip sizefor manufacturing cost reduction, but it carries the risk of in-creasingIR drop and L di/dt noise associated with the power

distribution network.Therefore, we believe that planning or design guidelines for the

power networks metal lines are essential at the early designplanning stage in order to deliver a successful chip.

This chapter is organized into six sections as follows. Section2.1 covers power grid planning for a communication chip [45].Section 2.2 examines power grid planning for two microprocessorchips [46, 47, 48]. Section 2.3 describes the power grid analysis

and decoupling capacitance optimization method for another mi-croprocessor chip [49]. Section 2.4 discusses the general method-ology forIR drop analysis and reduction. Section 2.5 discusses thepackage-level power network planning [61]. Section 2.6 is a sum-mary of the chapter.

2DESIGN PERSPECTIVES


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2.1 PLANNING FOR COMMUNICATION CHIPS

Deciding on the metal line layout in a chip to minimize the IR

drop and reduce L di/dt noise is part of power network plan-ning. Based on Equation (1-1), the metal line resistance is in-versely proportional to the metal line width. Based on Equation(1-5), the inductance is also inversely proportional to the metalline width. In addition, based on the guidelines shown in Figure1-17, the interleaving of Vdd andVss lines in small widths is pre-ferred to reduce the area of the current loop paths and reduce theinductance. In addition, the resistance and inductance are both

reduced if we use short metal lines from the power supply pads tothe devices.

The methods to improve the layout or package for the powerdistribution network are summarized as follows:

1. Adding multiple power lines (Vdd/Vss) over the chip, usuallyat some constant space over the chip surface.

2. Adding enough power lines in each layer (for example, M1,M2, M3, M4, M5, and M6, etc.).

3. Adding enough vias between power lines in adjacent metallayers.

4. Using advanced package technology, such as the C4 pack-age, to place multiple C4 power bumps over the chip and toreduce the distance from the bumps to the on-chip powernetwork.

The following design example is from a communication chip, as

shown in Figure 2-1 [45].

The first step is to decide on the floorplanning and chip area.The floorplanning also includes the package options and I/Olocations.

A simplifiedRLC model is constructed that reflects the pow-er line electrical models. In order to reduce the computation-al time, theR andC in the area are lumped in theRC model.

To improve accuracy, the package model is also included forVdd/Vss pads.

The inductance may not be included in the above model if itis not significant in the power distribution and the R/L delayis much less than theRC delay, as discussed in Section 1.5.

34 DESIGN PERSPECTIVES


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A sensitivity study is executed by varying the metal density ormetal widths in the chip floorplanning for the power distribu-tion network. TheR andC values in the simplifiedRC modelwill be varied based on the density of the power grid metals.

The sensitivity study can be done by changing the numberand locations of the Vdd/Vss pads supplied to the chip. We then

decide the bestIR drop andL di/dt drop across the chip. Once we select the power grid structure, we need to deter-

mine the number of Vdd/Vss pads and locations and the metalline widths for each layer of power grid.

Again, the design is optimized for the power grid with regardto the IR drop and L di/dt drop targets, with as little aspossible taken from the layout area.

TheIR drop analysis is performed on the DC analysis for this

simplified RC model of the power grid. The package resis-tance or inductance for each Vdd pad is included in the modelto analyze the voltage drop across the package.

The above power grid modeling and analysis should be donefor both Vdd andVss networks.

2.1 PLANNING FOR COMMUNICATION CHIPS 35

Fabric ESRAM

Standard_Cell

14.6mm

10.9mm 2.2mm

2.5mm13.4mm

IO pads (0.28mm)

Boundary scan bank (0.10mm)

PIO SRAM block (0.20mm)

PIO control bank (0.12mm)

Routing channel (0.40mm)

15.40mm

19.33mm


PLL


Routingchannel(0.3

0mm)

Routing

channel(0.5

0mm)

ARC

Memory

Routi

ngchannel(0.5

0mm)

IO pads (0.28mm) Boundary scan bank (0.10mm)

Fabric ESRAM

Standard_Cell

14.6mm

10.9mm 2.2mm

2.5mm13.4mm

IO pads (0.28mm)

Boundary scan bank (0.10mm)

PIO SRAM block (0.20mm)

PIO control bank (0.12mm)


15.40mm

19.33mm


PLL


Routingchannel(0.3

0mm)

Routing

channel(0.5

0mm)

ARC

Memory

Routi

ngchannel(0.5

0mm)

IO pads (0.28mm) Boundary scan bank (0.10mm)

Figure 2-1. Floor plan of a communication chip [45].


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TheIR drop or voltage drop is estimated for either Vdd orVss net-works. Let us assume the Vdd worst-case drop is Vdd, and the Vssworst-case drop is Vss. So the total worst-caseIR drop across theVdd andVss networks is (Vdd + Vss). Let us assume the voltage(Vdd) at the inputs of the Vdd pads is Vmax, and the Vss voltage atthe inputs of the Vss pads is 0 V. Therefore, the lowest voltageVmin in the chip is estimated based on the following equation:

Vmin =Vmax (Vdd +Vss) (2-1)

Figure 2-1 shows the floor plan of the communication chip. The

area is about 15.40 19.33 mm. This chip is in a wire bondingpackage with Vdd and Vss pads on the chips four boundaries.The power lines cross the main regions as follows: Fabric,ESRAM, standard cells, and routing channels.


Figure 2-2. RC modeling of full-chip power grid.

(a)


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Figure 2-2(a) shows the simplified RC model for the full-chip

power grid, and Figure 2-2(b) shows the unit-cellRC model for thepower grid in each unit region. The entire chip is partitioned intomany finer unit regions to cover the power grid. Each node in theunit-cellRC model is tied to a current source, which is a DC cur-rent to model the average current consumption by the devices lo-cated in that region.

The most difficult job in the modeling is to estimate the currentconsumption, since the current consumption depends on the ap-

plications of the chip and it is very hard to determine with accura-cy in the model before the chip is manufactured.

There are CAD tools on the market to estimate the current con-sumption based on test vectors or worst-case assumptions. For asmall unit region, we could apply the circuit simulation on the de-


Figure 2-2 (continued).

(b)


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vices to extract the average current. Figure 2-3 shows the currentmodels used for each unit region in this example. In addition, thecurrents will be different in different regions of the chip due todifferent circuit density and switching activity.

The modeling of the current sources can be improved continual-ly during the chip design stages as more circuits are designed andmore accurate current estimations are obtained. In addition, thepower grid current modeling can be further optimized based onsome test chip or earlier version chips power measurement. Theinitial specifications of the power grid will come up based on thesimulation model, as shown in Figure 2-2. Figure 2-4 shows the

power routing specifications in the fabric tile region of this com-munication chip [45].

The simulation result for the power grid model in this chip isshown in Figure 2-5. The simulation is done for theIR drop analy-sis. The worst-caseIR drop, based on Figure 2-5, is about 99 mV(1.71 1.6112 V). The lowest (Vdd Vss) voltage across the chip isabout 1.512 V (1.6112 0.0998 V).

For the communication chip power grid design shown in Figure2-1, due to the wire bonding package technology in which all theVdd andVss pads are located on the chip boundaries, many powerstraps are required across different regions and routing channels.In our case, theIR drop target is about 100 mV for each Vdd orVssnetwork across the chip.

The following specifications are given for the power routing onthe chip for the Vdd network; the Vss network has the same specifi-cations and equal metal lines in the routing [45].


.SUBCKT std_pwrI_T1 T1 0 6.9mAI_T2 T2 0 13.8mAI_T3 T3 0 6.9mAI_T4 T4 0 13.8mAI_T5 T5 0 13.8mAI_T6 T6 0 6.9mAI_T7 T7 0 13.8mA

I_T8 T8 0 6.9mAI_N_5 N_5 0 27.6mA.ENDS $ std_pwr $

.SUBCKT tile_pwrI_T1 T1 0 20.3mAI_T2 T2 0 40.6mAI_T3 T3 0 20.3mAI_T4 T4 0 40.6mAI_T5 T5 0 40.6mAI_T6 T6 0 20.3mAI_T7 T7 0 40.6mA

I_T8 T8 0 20.3mAI_N_5 N_5 0 81.2mA.ENDS $ tile_pwr $

.SUBCKT esram_pwrI_T1 T1 0 0.4mAI_T2 T2 0 0.8mAI_T3 T3 0 0.4mAI_T4 T4 0 0.8mAI_T5 T5 0 0.8mAI_T6 T6 0 0.4mAI_T7 T7 0 0.8mA

I_T8 T8 0 0.4mAI_N_5 N_5 0 1.6mA.ENDS $ esram_pwr $

Figure 2-3. Current consumption in unit regions.


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Figure 2-4. Fabric tile power routing specifications [45].


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Vertical and horizontal channels between standard cell, fab-ric, and ESRAM regions (metal width):

M6: 125 m (vertical channel)

M5: 125 m (horizontal channel)



I/O vertical and horizontal channels between core and pads(metal width):

M6: 125 m (vertical channel)M5: 125 m (horizontal channel)




+Vdd = 1.7100

+Vss = 0.

+ xi_2865.n_5 = 1.6910

+ xi_2866.n_5 = 1.6932+ xi_2868.n_5 = 1.6980

+ xi_218.n_5 = 1.6926

+ xi_219.n_5 = 1.6951

+ xi_2867.n_5 = 1.6890

+ xi_636.n_5 = 1.6945

+ xi_427.n_5 = 1.6386

+ xi_638.n_5 = 1.6846

+ xi_637.n_5 = 1.6817

+ xi_4.n_5 = 1.6659

+ xi_432.n_5 = 1.6281+ xi_431.n_5 = 1.6504

+ xi_2870.n_5 = 1.7029

+ xi_840.n_5 = 1.6959

+ xi_424.n_5 = 1.6503

+ xi_423.n_5 = 1.7007

+ xi_428.n_5 = 1.6112

+ xi_425.n_5 = 1.6508

+ xi_434.n_5 = 1.6529

+ xi_430.n_5 = 1.6439

+ xi_429.n_5 = 1.6120+ xi_433.n_5 = 1.6261

+ xi_426.n_5 = 1.6692

+ xi_6339.n_5 = 1.6979

+ xi_220.n_5 = 1.7008

Figure 2-5. Simulation results of node voltages [45].


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Vdd pad connection to core power ring (metal width andlength):

Length: 200 mM6: 90 m

M2: 90 m

Package resistance for each Vdd pad: 40 m (from ball topackage substrate to pad)

InputVdd (lowest) to package Vdd ball: 1.71 V

Fabric tile Vdd lines (metal width):

M6: 200 m total (vertical) inside the tile, 150 m total

(vertical) added between tilesM5: 550 m total (horizontal) inside the tile, 150 m total

(horizontal) added at sides of tiles

M4: 230.5 m total (vertical) inside the tile, 150 m total(vertical) added between tiles

M3: 150 m total (vertical) between tiles, 150 m total(horizontal) added on two sides of the tile

M2: 150 m total (vertical) between tiles.

M1: 150 m total (vertical) between tiles, 150 m total(horizontal) added on two sides of the tile

Standard cell region Vdd lines (metal width):

M6 completely used for Vdd andVss vertical straps (totalM6: ~6.7 mm Vdd, ~6.7 mm Vss)

M3: 20 m width straps (horizontal) per 500 m space

M2: 20 m width straps (vertical) per 500 m space

M1: inside standard cells (horizontal) about total 330 min the region

ESRAM region Vdd lines (Vdd metal width to fill in whitespaces):

M5 completely over the 9 SRAM blocks (ESRAM/ARC) (to-tal M5: ~7.1 mm Vdd, ~7.1 mm Vss). 0 m in channels be-tween ESRAM blocks

M4: 30 m ring (vertical) inside each SRAM block

M3: 30 m ring (horizontal) inside each SRAM block

Figure 2-6 shows the complete power grid (Vdd) simulation model.The node voltages in the simulation by DC analysis are shown inthis figure and the lowest voltage is about 1.32 V at the center of



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the chip. The simplified power distribution model allows us to dothe sensitivity study while changing the metal widths and densi-ties in the power routing to see the impacts on the node voltages.The resistance and capacitance of the metal lines are varied,based on the given power routing widths of the Vdd network. Forexample, Figure 2-7(a) shows the lowest voltage at the center ofthe chip by selecting various metal widths for each Vdd orVss busin the routing (horizontal coordinates in the figure) and variousmetal widths extended directly from each Vdd orVss pad (verticaly coordinates in the figure).

It is done by using parallel metal buses overlapped in the M6and M4 (vertical) or M5 and M3 (horizontal) layers. Figure 2-7(b)

further shows the lowest voltage improvement obtained by addingmore parallel buses in M6, M4, and M2 (vertical) and M5, M3, andM1 (horizontal) routing layers. By adding more power buses in M2,compared with Figure 2-7(a) and Figure 2-7(b), the lowest nodevoltages are slightly improved across the chip by our simulation.


Vdd Vdd Vdd V dd Vdd

Vdd

Vdd

Vdd

Vdd

Vdd

Vdd

Vdd

Vdd

Vdd

Vdd

Vdd

Vdd

urrent and Voltag e D istribut ions

I avg 50mA100mA100mA100m A100m A50mA

120mA240m A240mA240mA178mA58m A

17mA

17mA

8m A

157m A

157mA

78mA

280mA

280m A

140m A 140m A 140mA 70mA

280mA 280m A 140mA

280mA 280mA 140m A

Vdd Vdd Vdd Vdd

1.8V

1.8V

1.8V

1.8V

1.8V

1.8V

1.8V 1.8V 1.8V 1.8V 1.8V

1.8V 1.8V 1 .8V 1 .8V 1 .8 V

1.8V

1.8V

1.8V

1.8V

1.8V

1.76V 1.72 V 1.69V 1.66 V 1 .5 7V 1 .7 2V

1.72 V 1.59V1.49 V 1.46V 1.46 V 1 .5 8V

1.73 V 1.52V 1.36V 1.32V 1.40V1.66V

1.70V 1.55 V1.42 V 1.4 0V 1.47V 1.69V

1.71V 1.72 V 1.70V 1.69V1.71V 1.75V

53.3mA 34.2mA 28. 7 mA 9 8. 1mA 158.2mA

1 49.3mA 102.8mA 4 0. 6mA3.8mA 131 .0mA

251.4mA 1 69.3mA 38.7mA83.2mA 266.6mA

1 77.3mA 134.9mA 2 5. 2mA79.3mA 227.4mA

17.0mA 25.2mA 4.6mA 16.4mA 42.9mA

54.2mA

126.7mA

102 .7mA

102 .7mA

102.7mA

157.7mA

127.1mA

219.6mA

219.6mA

1 71.5mA

1 71.5mA

6 8. 5mA 185 .9mA 281.2mA 297 .7mA 156 .3 mA 194 .2mA

12.1mA 54.3 mA 103 .4mA 1 02.1mA 43.4mA56.8mA

2 7. 6mA 20.6 mA 4 6.0mA 60.0mA 53.1mA 24.2mA

9 .0 mA 1 35.2mA 216.3mA 2 31.5mA 185.0mA48.7mA

1 17.5mA 266.8mA 3 75 .7mA 467.1mA 2 75 .3mA

255 .4mA 335.7mA 350 .5mA 298 .4mA1 61.6mA

Figure 2-6. Power grid simulation model [45].


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The sensitivity study based on the simplifiedRC model for theentire chip power grid provides a useful tool during the powergrid planning. Further sensitivity studies can be iterated duringthe power grid planning stage to answer the following questions:(1) How many Vdd and Vss pads should there be? (2) Whereshould these Vdd andVss pads be located? (3) Do we distributethem evenly or nonevenly? (4) Do we use wire bonding technolo-gy or some other more advanced technology to reduce the IR

drop?In the example we have shown, a huge amount of layout area

has obviously been used by the power grid and the chip area willbe impacted significantly. So C4 or flip-chip technology is definite-ly a good alternative for this design.


Figure 2-7. Sensitivity study of power metal widths [45].

(b)

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

1 (34um) 2 (68um) 3 (102um) 4 (136um) 5 (170um)

# 34um Lines per VDD Bus

LowestvoltageV(fabriccenter)

30um pad

60um pad

90um pad

120um pad

(a)

LowestvoltageV(fabriccenter)


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2.2 PLANNING FOR MICROPROCESSOR CHIPS

The following design example is from a high-performance micro-processor [46]. Power distribution has been always one of the crit-ical issues in high-performance microprocessor designs. The volt-age supplies and also the voltage drop budgets are scaled alongwith the deep-submicron processes. In addition, the power densityof the die is significantly increased in new processors. The C4package is used to increase the power drop reduction across thesystem to inputs of the chip.

The decoupling capacitors are used for two purposes in high-

performance microprocessor design. They provide the chargesharing for nearby switching gates. The local decoupling needs avery fast response time and this response time is scaled in everygeneration of the microprocessors. The decoupling capacitors alsoprovide the charges for suppressing large full-chip current fluctu-ations over the power delivery system.

Figure 2-8 shows the voltage drop across the power networksystem versus the capacitances in the die. It is claimed that thearea of the on-chip decoupling capacitance is about 12% of the to-tal die size [46]. The power distribution network is a low-pass fil-


Figure 2-8. Power voltage drop versus decoupling capacitance in a high-perfor-

mance microprocessor [46].


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ter in order to suppress the high-order noise, preferably only forthe DC voltage across this system.

Based on the series RLC model, as shown in Figure 1-3, thequality factor Q will be reduced with large C, smallR, and smallL. Low Q will result in the wide bandwidth needed to allow theAC resonance to pass over the power delivery system. The qualityfactor of a seriesRLC network can be determined as follows:

Q = (2-2)

There are two methods to plan the power grid in high-perfor-mance microprocessors [46]. The first method uses spreadsheetcalculations. It computes the voltage drop for a section of the pow-er grid, which includes the estimation of voltage drops from thepackage to the transistors.

The second method is to build the complete RLC model of thefull-chip and package-level power distribution networks. The full-system models (die, package, and power supply) are needed in theaccurate model to perform the voltage simulations across the pow-er network.

It is usually simulated overnight and the model complexity islimited by the simulation time. The results can be used to set thespecifications for the power distribution design on the chip and onthe package. Here are the detailed steps for the C4-package-basedpower grid design in the high-performance microprocessor design[46]:

Start with basic calculations of the current needed for thechip. The current can be scaled from the prior products. Itcan also be decided on based on the spreadsheet and handcalculations based on the simulation data in individual mod-ules possibly used in the chip.

Keep in mind that when we design the power grid, the circuitand layout design of each module may not be clear or final-ized. So in this stage, a ballpark figure or estimation is used

for the power design. Usually, overallocation of the powergrid lines are common practice due to the overestimation ofthe switching current.

Build the first full system model based on the understandingof what are the causes of the large voltage drop.

L/C

R

2.2 PLANNING FOR MICROPROCESSOR CHIPS 45


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Propose the first-order solution for the die, package, andpower supply.

Develop the initial voltage drop budget and simulation volt-age for timing modeling.

Move toward the detailed design. Determine the exact C4bump array. Fine-tune the metal grids over the chip basedon the detailedRLC models simulation.

The power grid model is improved during the project whenmore modules are finalized with circuits and layouts.

Determine the distance limits of the decoupling capacitors,based on the response time simulation to neighboringswitching gates, and eventually come up with the decou-pling capacitance placements and sizes needed in the de-sign.

The current estimation usually uses the spreadsheet method,based on power estimates, which have substantial uncertainty[46]. It takes the module power and area into the spreadsheet andproduces the map of the power per grid area. The grid area is fit

to the C4 bump service area. It converts the power of the currentand produces the distribution of the current per bump.

Figure 2-9 shows a detailed M6 grid alignment specification inthis high-performance microprocessor. This gives a regular rela-tionship between the two layers. Only two M5 tracks are neededin this assignment to connect M6 to M4 layers. The M6 grid is de-signed to align with the global M4 grid to enable the efficientrouting of the top-level nets and allow for DRC cleaning in the

full-chip assembly.To accomplish this, the following M6 specifications are given

for the Vcc/Vss lines:

The M6 grid pitch is a multiple of the M4 grid pitch and willbe aligned to the M4 grid on the floor plan.

The M6 major grid pitch = 538.56 m, which is 11 times theM4 grid pitch of 48.96 m. The M6 minor grid pitch = 48.96

m, which is equal to the M4 grid pitch. Each M6 minor grid will exactly overlay the M4 grid under

it. The M6 grid is placed on the floor plan such that the Y off-set of both major and minor M6 grid is a multiple of 48.96m.



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Figure 2-9. Specifications of the power grid on M6 [46].


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16Vcc/Vss stripes between the C4 power rows enable the re-laxation of the decoupling capacitor placement rule, which isfrom 200 m to 500 m.

Each Vcc/Vss strip width is 2.64 m and the space is 1.68m.

Unlike M4 and M5, there are no reserved tracks in M6 forthe global clock distribution.

The global clock will be routed in signal tracks and will beshielded from any adjacent nonclock-related routing by VccandVss.

The global clock routing width is 18.96

m and space is 1.44m. They should be designed to fit into the M6 grid.

The M5 power grid, as shown in Figure 2-10, has the followingspecifications:

The M5 grid pitch is 81.36 m. The M5 Vcc/Vss width is 6.80m and the space is 1.52 m.

The M5 signal pitch is 4.24 m and there are 12 signaltracks between two Vss/Vcc pairs.

The M4 power grid, as shown in Figure 2-11, has the followingspecifications:

The M4 grid pitch is 48.96 m. The M4 Vcc/Vss width is 2.68m and the space is 1.04 m.

The M4 signal pitch is 2.32 m and there are 16 signal

tracks between two Vss/Vcc pairs.

In order to plan the metal grid design for the full-chip power net-work, the package model and decoupling capacitor model have tobe included in the entire AC analysis. A reasonably good AC pow-er network model must be built. We discussed power networkmodeling and characterization in Chapter 1.

In this section, we will examine the power network AC analysis

model from two high-performance microprocessors [4748]. At theminimum, the analysis must account for the Vcc source, the moth-erboardVcc/Vss traces, the board decoupling capacitors, the CPUsocket, the package pin, the power planes, the on-package decou-pling capacitances, the CPU I/O, core circuits, and the global clockdistribution network.



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With this AC model, the CPU I/O and core can be toggled tomimic the execution of the CPU, and the power network perfor-mance can be measured and analyzed. The AC model from a high-performance microprocessor is made of three submodels: thepackage model, the I/O model, and the CPU core model. These

models are shown in Figure 2-12.The I/O and core cell models are represented by an array of the

circuit models to model the global power grid on the M4 and M3layers across the chip, with the switching current tied to each corecell to model the switching activity of the circuit, as shown in Fig-ure 2-13. The current model can be a triangular or other current




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Figure 2-12. Package-level power network modeling [47].


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waveform from the circuit simulation of this design. The I/O mod-el will include the detailed I/O circuits.

Since the global clock tree will consume a lot of power, in thismodel the detailed model of the clock tree is included for thewhole power network simulation. In addition, the decoupling ca-pacitors are included in this model, as shown in Figure 2-13.

As shown in Figure 2-13, the total chip is partitioned into 180core cells in this AC model. Each cell represents about 1150 1000m2 of area in the chip. Each cell includes the modeling ofM4Vcc/Vss, M3 Vcc/Vss and the back power plane network. The on-chip decoupling capacitors are added in the model to simulate theeffectiveness of such capacitors.


Figure 2-13. I/O and CPU core power network modeling [47].


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The core cell current source is turned on to consume a total of8 A average current. The I/O models can be turned on simulta-neously. The AC wave of the core cell current is shown in thecell model. A high current peak is introduced after the rise ofthe clock and a smaller peak is introduced after the fall of theclock.

In order to understand the impact of on-chip decoupling ca-pacitors on the power network, it is necessary to break the on-chip decoupling into two categories: global on-chip decouplingand local on-chip decoupling. For performing global on-chip de-coupling, the on-chip decoupling capacitor value in the core cell

is varied from 0 pF, 100 pF, 300 pF, and 500 pF to represent atotal decoupling of 0 nF, 18 nF, 54 nF, and 90 nF in the activecore.

Simulations were done in a typical corner with the Vcc set to2.5 V. The results are shown in Table 2-1. It is obvious thatthere is a net improvement on the power network and clock dis-tribution with the global decoupling capacitors. Assuming that agreater percentage of the channels can be used to implement thedecoupling capacitors, the decoupling capacitor layout densitycan be calculated, assuming 34% of the active core area in thechannels.

An investigation of the effect of local on-chip decoupling on thepower network was conducted [47]. A 5 nF decoupling capacitorwas placed in one of the core model cells. It had roughly the samedecoupling density as the 90 nF case in the global study with nodecoupling capacitors in other core model cells. Simulation resultsindicate that the effect of the local decoupling is not limited to the

cell where the decoupling capacitors are placed. The surroundingcore cells, both in the M4 and M3 directions, all benefit from thislarge decoupling capacitor. The simulation result of this local de-coupling is shown in Table 2-2.


Table 2-1. Global decoupling capacitor results [47]

Total decoupling Worst-cycle Worst cycle Worst-case

capacitance average minimum Circuit speed global clock(nF) Vcc/Vss (V) Vcc/Vss (V) up (gates) jitter (ps)

0 2.071 2.002 Baseline 96

18 2.089 2.046 1.00% 83

54 2.122 2.087 2.40% 74

90 2.136 2.110 2.75% 59


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The local decoupling capacitors are extremely useful for high-switching-current circuits. They prevent the dip of the power sup-

ply voltage around these areas due to the immediate large currentflows. For example, if the decoupling capacitors are placed in theleft and right I/O areas, ~8 nF total decoupling capacitance in theI/O regions has been reported [47].

The center clock spine will also have decoupling capacitors(~45 nF) [47]. It is strongly recommended to have enough decou-pling capacitors close to each clock buffer in the chip. The globaldecoupling is implemented to prevent the overall dip in the power

supply. Therefore, the die, the package, and the board design re-quire additional decouplin

Power Distribution Network Design for VLSI

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