Power Conditioning Unit for a Harvester Circuit · Index Terms—Energy Harvesting, Voltage Sensor, Voltage Limiter, Low Power, Temperature Compensation. I. INTRODUCTION Wireless

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Power Conditioning Unit fora Harvester Circuit

Diogo Santos

Abstract—This work presents a Power Conditioning Unit(PCU) for autonomously powered devices. Autonomously pow-ered devices are passive systems and require an harvester circuitfollowed by a PCU to manage the power delivered to a loadcircuit. These systems assume a relevant role in the design ofbiomedical implants and wireless sensor networks. As differentenergy sources are accountable (sunlight, vibrations, RF) andits power is dependent on external conditions, it is importantthat the passive systems are tolerant to the harvested powervariability. For this reason, the proposed PCU applies an inter-mittent load activation control and a power limiting functionality.Furthermore, it has to have a negligible idle power dissipation,when compared to the low power output provided by state-of-the-art harvesters (< 1µW). The PCU uses a voltage sensor withhysteresis and a voltage limiter to control the load activation anddefine the maximum voltage. The load activation and deactivationvoltages, and maximum voltage are known as transition voltages.Both blocks are based on a low voltage circuit composed by apico-watt reference and a CMOS inverter, providing a voltagesensing, while imposing a maximum steady state current equalto 2 nA. The PCU is designed in a 130 nm process at simulationlevel and is able to control the transition voltages with a ±10%precision on a −25 oC to 90 oC range.

Index Terms—Energy Harvesting, Voltage Sensor, VoltageLimiter, Low Power, Temperature Compensation.

I. INTRODUCTION

Wireless power transmission is a relevant research field forits role on the development of autonomously powered devices.These correspond to electrical devices that only require the en-ergy provided by harvesting to operate. The circuit responsiblefor providing the energy to the system is known as energyharvester. Nowadays, the temperature gradients, vibrations,sunlight, and Radio Frequency (RF) waves are some of theaccountable external sources that can be harvested.

The combination of an harvester and a load circuit is knownas passive system. In order to store the harvested energy,usually a capacitor is used at the harvester output. Consideringprevious studies [1], it is verified that the RF harvesters provideless power than other external sources. As verified by thestate-of-the-art [2], [3] the RF harvesters power output isapproximately 1 µW for a 10 µW input. Based on thesefacts, a major focus is given to the RF harvesters in this work.

Commonly RF harvesters are used to supply low power cir-cuits, such as front-end interfaces, memory cells and sensors.The Radio Frequency Identification (RFID) systems [4]–[6]are one of the examples, which are used for shopping tagsand Smart Card transportation tickets. Another applicationsare the Wireless Sensor Networks (WSNs) [7], which can beapplied for forest surveillance, and the biomedical implants[8], [9].

As stated by the Friis formula, the power that arrives to theRF based passive system, depends on its distance from theRF source. Therefore, the power provided by the harvesterpresents an undesired variability to the load. To counter thisproblem, Power Conditioning Units (PCUs) are applied in thepassive system between the energy harvester and the loadcircuit. In order for the circuit to operate correctly and notbe damaged, a PCU stabilizes and limits the power deliveredto the load. Moreover, it controls the activation of the loadcircuit. This last characteristic is a key function for low powerharvesters, once that it allows the passive system to operateintermittently. When an intermittent operation is applied, thepassive system is based on charge and discharge cycles [7].Hence, on the charge phase, the system harvests the energyand stores it in the capacitor. When the capacitor charge issufficiently high to deliver the power required by the load, thesystem is discharged.

The state-of-the-art PCUs [7], [10] are based on threefunctions: stored energy evaluation, load activation and powerdelivery. The energy evaluation function, corresponds to thesensing of the voltage at the capacitor terminals. Dependingon that voltage, the load is activated or deactivated. Finally,when the load is activated, the power delivered to the loadhas to be regulated and limited. Therefore, the circuit blocksused to implement such functions are voltage sensors, voltageregulators and voltage limiters.

Due to its advantages, the developed PCU applies a voltagesensor circuit to implement an intermittent load operation. Itassumes that the load can be activated for a supply equalto 1.2 V, and must be deactivated for a supply lower than0.4 V. To ensure that an overvoltage does not occur, the PCUalso contains a voltage limiter, which imposes a maximumvoltage of 1.5 V. Although a voltage regulator is critical fora correct load operation, the implementation of this featureis not included in this work. Based on the state-of-the-artRF harvesters, it is imposed that a 1 µA current output canbe provided to a 1.2 V load. For the passive system to beconsidered power efficient, the power required by the PCUhas to be lower than the harvested. Thus, a 10 nW powerspecification is imposed to the PCU design. Although a majorfocus is given to RF, the assumed circuit design considerationscan be applied to other types of energy harvesters. The PCU isimplemented at simulation level in the UMC 130 technologywith high speed transistors only, to reduce the IntegratedCircuit (IC) cost. Furthermore, a ±10 % precision toleranceis imposed for the transition voltages (0.4 V, 1.2 V and 1.5 V)considering a temperature range from −40 oC to 100 oC andfabrication process corners.

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Once the motivation and research goals are defined, thestructure of this work is defined as follows: Section II in-troduces the passive system internal structure and reviews thestate-of-the-art PCUs; Section III proposes a transistor levelreview on the circuits commonly used in the PCU literature;Section IV presents the complete design procedure from thehigh level circuit structure to the layout implementation ofthe voltage sensor and limiter; Section V provides the finalconsiderations on the developed PCU, comparing the resultsobtained to those proposed.

II. POWER CONDITIONING

The main purpose of this chapter is to verify the powerconditioning role on passive systems. In order to do it, firstlythe passive systems structure and operation are defined. Then,the internal blocks that constitute state-of-the-art PCUs aregenerically characterized.

A. Overview

To understand the passive system operation, each of theblocks influence on the power delivering process to the loadcircuit has to be verified. Figure 1 presents an equivalenthigh level model of the passive system. The energy harvesterand load circuits are replaced by ideal electrical components,whereas the PCU is defined as a circuit block that outputsVLoad based on the supply generated by the harvester, definedas VDC . In order to explain the model, each block is analysed.

In the model of Figure 1, the energy harvesting block iscomposed by a current source IS and a capacitor COut. Thecurrent source value correlates to the power that the harvesteris able to provide to a circuit. COut is the element responsiblefor storing the harvested energy.

Fig. 1. Proposed high level model of the passive system.

The conditioning unit can be interpreted as a gate thatestablishes the power link between the harvester and theload. Recalling section I, to fully accomplish that role, theconditioning unit is responsible for three different functions:stored energy evaluation, load activation and power delivery.Regarding the first conditioning function, the energy stored ina capacitor is directly related to the voltage at its terminals.Therefore it is required that the PCU performs a voltage sens-ing of VDC . By doing this function, the load can be activated ordeactivated based on the VDC value. The activation occurs forVDC = VON , which turns ON the PCU output, equivalentlyVLoad > 0 V. The deactivation is set by VDC = VOFF

and results in turning OFF the output signal, VLoad = 0

V. The power delivery occurs when the load is active. Thislast PCU function is divided in two parts: voltage regulationand limiting. Voltage regulation is used to generate a VLoad

stable and independent of VDC . The voltage limiting consistsin imposing a maximum VDC value, defined as VLim, whenan overvoltage occurs.

For the PCU design point of view, the load circuit canbe interpreted as resistor RL (Figure 1) with voltage andoperating time requirements.

B. System Operation

The passive system, described by Figure 1, operation de-pends on the power harvested and the power required by thesystem, which corresponds to the power delivered to the PCUand load circuit. When the harvested power is below the powerrequired, the load can only operate intermittently, once it relieson the energy stored in COut. The VDC and VLoad voltagesbehave as presented in Figure 2 for an intermittent operation.The time t0 corresponds to the start-up time, which is thetime required for the discharged passive system to reach VON .At t1 the load operation is interrupted, because the capacitordischarge leads to VDC=VOFF . The period between the t0and t1 is defined as the load active period ∆tON .

VON

VOFF

t0

tON

t1 Time

VDC

Fig. 2. Passive system supply voltage (VDC ) for the intermittent operation.

When the harvested power is higher than the required bythe load, the passive system operates continuously. When VDC

continues to rise despite the load activation, a voltage limitingmode at VDC=VLim is imposed, depicted in Figure 3. Thetime between the load activation t0 and the limiter activationtL is defined as ∆tL.

t0 t0L

VOFF

VON

VLim

Time

t L

VDC

Fig. 3. Passive system supply voltage (VDC ) for the voltage limitingoperation.

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C. PCUs Review

After describing the passive system blocks and their in-fluence in the overall operation, the PCU internal structureand the circuit blocks required for this work (voltage sensorand limiter) are presented. As illustrated in Figure 4, thePCU follows a two stage structure. The first is composedby the voltage sensor, which evaluates the harvested energyand activates the load by turning ON the voltage regulatorcircuit. The second stage is composed by a voltage limiter anda voltage regulator to fully ensure the power delivery function.

Fig. 4. State-of-the-art PCU structure composed by a voltage sensor, a limiterand a regulator that outputs the load voltage supply VLoad.

A voltage sensor, also referred as Power-ON Reset (POR)in the PCU literature [5], [6], [11], [12], is usually imple-mented by a comparator based circuit, following the structurepresented in Figure 5. It compares the sensed voltage VS ,to a supply independent voltage (VREF ). When VS becomeshigher than VREF , the comparator output VO switches fromzero to VDC . The VDC where VO toggles between voltagelevels is known as transition voltage, defined by VTR. OnceVTR is configured by a voltage divider and by the fixed VREF

value, by using three resistors RU , RD and RH , as presentedin Figure 5(a), an hysteresis behaviour can be imposed. Thus,for VO = 0 V a voltage division ratio

α0 =VSVDC

=RD//RH

RU +RD//RH(1)

is defined, whereas for VO = VDC the ratio is changed to

α1 =RD

RU//RH +RD. (2)

As VS becomes dependent of the comparator output, VO isactivated at VDC = VON and deactivated at VDC = VOFF , asillustrated in Figure 5(b).

Although a voltage limiter can be implemented simply byseveral diodes in series connecting VDC to ground [6], [10],[13], the circuit presented in Figure 6(a) is more efficient [5],[7], [9], [13], [14]. It uses a voltage sensor without hysteresisto activate a low impedance path, based on a N-type MetalOxide Semiconductor (NMOS) transistor. As illustrated inFigure 6(b), by setting the division ratio α to activate VO atVDC=VLim, a current Idisc is imposed. Once VO = VDC afterthe VLim transition, the VDC increase, causes also an Idiscincrease. In turn, this leads to a VDC reduction. Therefore,a feedback structure is formed by the Idisc relation to VDC .This allows the passive system supply to stabilize in VLim

Fig. 5. (a) Schematic of a voltage sensor with hysteresis behaviour. (b) Plotof the sensed voltages VS resultant of the division ratios α0 and α1, and thecorresponding sensor output VO characteristic.

by dissipating the excess harvested power, as shown in Figure6(b).

Fig. 6. (a) Voltage limiter based on a voltage sensor and MOS transistor. (b)Plot of the voltage sensed VS , and corresponding output of the sensor circuitVO in the voltage limiter.

III. PCU CIRCUITS

Based on the analysis of section II, the voltage sensors andlimiters rely on comparators and voltage reference circuits.Considering the power and precision specifications imposed,those circuits are analysed for both typical conditions, tem-perature and process corners. To do it, the operating regionsand Process, Voltage and Temperature (PVT) influence on theMOS transistors is initially reviewed.

A. MOS transistors review

The current on a MOS transistor is primarily dependent onits gate-to-source voltage VGS , drain-to-source voltage VDS

and threshold voltage Vth. The expression that describes its

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current on the strong inversion saturation region (VDS ≥VGS − Vth) is

ID =1

2µCox

W

L(VGS − Vth))2, (3)

where µ is the charge-carrier effective mobility, Cox is theoxide capacitance and W over L is the relation of the widthand length of the transistor. In order to reduce the current in asaturated transistor, its length can be increased, or its VGS−Vthterm, known as overdrive voltage, can be decreased. If theoverdrive voltage becomes lower than 0 V, the MOS operatesin the subthreshold, which contains the weak inversion region[15]. Compared to strong inversion, a weak inversion biasingallows a greater current reduction, nonetheless it also imposesa slower circuit operation [16]. The current on weak inversionsaturation region (VDS > 4UT ) is modelled by [17]

IDS = IS0 exp

(VGS

nUT

), (4)

where specific current IS0, is defined as

IS0 = µW

LU2TCox exp

(−VthnUT

). (5)

Such current presents an exponential dependence on VGS , Vth,subthreshold swing parameter n and thermal voltage UT .

Once the MOS transistor operation regions are defined,the influence of the temperature and process corners on thetransistor parameters is analysed. Besides the thermal voltage(UT ) variation, the temperature influence is mainly noticed onthe mobility (µ) and threshold voltage (Vth). UT and Vth areknown to increase with temperature, whilst µ to decrease withit. However, the Vth effect for low currents is more significantthan µ. Consequently, in weak inversion the current increaseswith temperature.

A process corner represents a fabrication condition imposedby the technology foundry that causes the worst shift on thesemiconductor device properties. Considering MOS devices,the corners state how fast or slow is the produced N or Ptype transistor relatively to a typical case. In a fast corner,the mobilities µ are increased and threshold voltages Vthdecreased, whereas in a slow corner the opposite is verified.

B. Comparator Circuits

The PCU literature usually apply simple, well-known cir-cuits as the differential pair [5]–[7], [9], [13] and the Comple-mentary MOS CMOS inverter [12] to implement the requiredvoltage comparison. That is verified because they present agood power to performance trade-off when power dissipationis a design specification.

The differential pair is an amplifier circuit that affectsthe amplitude of the differential signal applied at its inputs.Applying large amplitudes makes the circuit leave the linearregion and its output saturates, providing two voltage levels,zero and the supply voltage. Commonly the topology usedis the presented in Figure 7(a), also known as the pseudodifferential pair. To make the output VO1 or VO2 saturate, thecurrent on one of the branches has to be higher than the other,thus the transition occurs when the currents are equal. If the

transistor pairs M3, M4 and M1, M2 have the same sizes,then the comparison offset VOS is zero, as the input voltagesVI1 and VI2 impose the same current on both branches whenthey have equal values.

Fig. 7. Comparators schematic. (a) A (Pseudo) Differential Pair. (b) A CMOSInverter.

The CMOS inverter, presented in Figure 7(b) is normallyused as logic gate that operates with digital signals, presentinga fast transition between the voltage levels, as desired for acomparator. The output toggles when VI reaches a transitionvoltage that is usually half of the supply voltage. This circuitpresents an high resistance path from VDD to ground, becausethere is always one transistor in the cut-off region, exceptduring the transition, where both MN and MP are saturated.Such characteristic makes the circuit steady state current to bevery low.

By comparing both circuits under the same conditions, theinverter has a lower power dissipation. Nonetheless the inverterpresents a high sensitivity to PVT variations, once that itstransition voltage depends on the transistors parameters. Onthe differential pair, the PVT effect is mitigated by makingM3, M4 and M1, M2 have the equal sizes.

C. Voltage References

The design of a voltage reference circuit has to accountfor the voltage value generated, the supply and temperatureinfluences on it, and the power dissipated. The reference outputVREF dependence on the supply voltage is known as the linesensitivity. The temperature influence on VREF is defined bythe figure of merit known as the Temperature Coefficient (TC).The temperature independence can be achieved, as occurs inbandgap circuits. Nonetheless these require a power in themicro-watts range [7], [18], which is not feasible to apply inthe described system.

Commonly, the circuit of Figure 8(a) is applied to provide areference voltage VREF for PCUs [5], [6], assuring the supplyindependence with reduced design time. The VREF providedis imposed by the saturation current of the Bipolar JunctionTransistor (BJT).

On Figure 8(b) another reference is presented, which is pro-posed by [18]. This simple design known as the 2T topologyhas a pico-watt power dissipation. It applies a negative VGS

on the upper transistor MC to impose a subthreshold operationand significantly reduce the voltage reference circuit current.The generated VREF is mainly defined by the MD and MC

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Fig. 8. (a) BJT based reference circuit. (b) 2T reference circuit.

thresholds difference (VthD− VthC

). Thus it is required thatsuch difference is great enough to produce a positive VREF .

Comparing both circuits, the proposed by Figure 8(b)presents a lower power dissipation and does not use BJTdevices, which is advantageous for IC design.

IV. PROPOSED PCU

A. Structure and Design Considerations

As previously referred, the circuit blocks required to im-plement an intermittent operation and a voltage limiting, arethe voltage sensor and voltage limiter, respectively. In orderto match the specifications proposed in the research goals,the transition voltages are: VON = 1.2 V, VOFF = 0.4 Vand VLim = 1.5 V. The applied PCU structure is presented inFigure 9. The PCU output is the power enable signal (P EN )provided by the voltage sensing circuit. This allows the controlof the load activation by using a switch. Once VON < VLim,the voltage sensor output is also used to activate the voltagelimiter sensing part.

Fig. 9. Proposed PCU circuit blocks structure.

In order to verify the expected VDC charge and dischargebehaviours (section II) that characterize the intermittent andvoltage limiting operations, an ideal voltage source cannot beused. Thus, the testbench presented in Figure 10 is used. Infact, this results from the passive system high level modeldefined in the power conditioning review (Figure 1). Thecurrent source IS , capacitor COut, switch and load resistanceRL used in the testbench are ideal. The IS and RL valuesare changed in order to simulate different operating modes.COut is fixed to 50 nF, which is considered sufficient for anintermittent passive system with a IS = 1 µA.

Fig. 10. Passive system testbench used for the PCU simulation.

B. Voltage Sensor

The applied voltage sensor follows the structure presentedin Figure 11, where VDC is the input, and P EN andP EN the outputs. The comparator and reference circuitscompose the voltage sensing core, due to its main role ondetecting the transition voltage through the voltage sensed,defined by VS . In the case of the proposed voltage sensor, thetransition voltage, generically defined by VTR, corresponds tothe VDC where P EN and P EN toggle between voltagelevels. To reduce the power dissipation, the comparator supplyvoltage is the sensed voltage and the down resistance of thevoltage divider is eliminated. As later explained, the downresistance is provided by the load imposed by the circuitsupplied by VS . The voltage level shifter is used to to shiftthe voltage sensor output to VDC . The shifted VO is P EN ,whilst P EN corresponds to its logical opposite. In orderto implement the hysteresis behaviour, the resistors RU0 andRU1 are accompanied with switching interfaces controlled bythe level shifter outputs. The division ratio achieved with RU0

defines the VON transition, whilst the ratio established by RU1

tunes VOFF . The implemented voltage sensor is illustrated inFigure 12 at transistor level. Each circuit section is explainedin the following paragraphs.

Fig. 11. Proposed voltage sensor circuit structure.

The voltage sensing core is composed by two circuit blocks,the comparator and the voltage reference circuit, as picturedin Figure 12. The reference is made by the transistors MC

and MD as a result of adapting the 2T topology reviewed insection III. The transistors M1 and M2 form the comparatorcircuit based on a CMOS inverter.

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Recalling subsection (III-C), the mean value of the referencegenerated by the 2T circuit, defined by VREF , is mainlydependent on the transistors thresholds difference, namelyVthD

− VthC. Once that only high speed transistors are used,

that term can only be sufficiently high when transistors ofdifferent channel types are applied. Thus, a PMOS is usedas MD and an NMOS as MC , because the PMOS thresholdis higher than the NMOS. This reference provides a stableVREF ≈ 0.1 V for a supply VS> 0.2 V.

By connecting the reference voltage to the inverter input, thetransistor M1 operates in the weak inversion region. Hence, thecomparator output transition depends mainly on M2 switchingbetween the cut-off and strong inversion saturation region. Thetransition of the complete sensor output P EN , depends onthe transition of the sensing core. Therefore, VTS is used todefine the supply VS required to make the sensing core outputVO to switch voltage levels. According to the proposed design,VTS = 0.3 V and the sensing core current is below 1 nA.

In order to perform the VS to VDC conversion, a volt-age level shifter based on cross coupled PMOS transistorsM7 − M8 is used [19]. Besides that main block, also onelow voltage inverter (M3 −M4) is required to generate VO,the logical opposite of VO, and an output inverter (M9−M10)to buffer the signal P EN . The transistors used in the levelshifter present low aspect ratios in order to reduce the currentspikes that occur at the VTR transitions. The sensing coreoutput transition, defined by VTS , occurs at VS= 0.3 V, andthe voltage sensor has to activate P EN at VDC=VON .Attending at Figure 12, the cross coupled PMOS transistorsoperate in the strong inversion and the NMOS M5 and M6

operate near the subthreshold region. Therefore, the aspectratio of the NMOS is increased comparatively to the PMOS,so that the NMOS current drive capability can be sufficientlyhigh to pull-down the P EN voltage node. However it isverified that when VO transits from zero to VS at VTS , the lowvoltage VS is not high enough for the P EN pull-down tooccur. In fact, the pull-down is only verified for VS= 0.32 V.From VS=VTS to VS= 0.32 V, the cross coupled level shiftersection establishes a direct current path, which compromisesthe power dissipation specification. Note that this effect is onlyverified for the VON transition, because at VOFF the supplyVDC = 0.4 V.

In order to minimize the effect of the NMOS low currentdrive capability, the time period between the VTS transitionand VS= 0.32 V, has to be reduced. Once the current on thevoltage sensing core stabilizes at approximately 0.9 nA whenVS=VTS . Furthermore, the current on the low voltage inverterof the level shifter (M3−M4) decreases from 0.25 nA to 0.5pA, at the referred transition. Thus, it can be verified that thecurrent on the low voltage circuit, which is defined by ILV

and identified in Figure 12, becomes lower and stable afterVS=VTS . As a consequence, the load imposed by the lowvoltage circuit, which is defined as RLV = VS/ILV , increasesafter VS=VTS . Once the RD resistor is not used on the voltagedivider, the voltage VS presents a faster rise after the transitionat VTS . This causes the reduction of the time period betweenthe VTS transition and VS= 0.32 V.

Besides depending on the RU0, RU1 resistances, the config-

uration of the load activation (VON ) and deactivation (VOFF )is based on the RLV resistance at the sensing core transition.When VS=VTS the RLV value is defined as RTS≈ 300 MΩ.Bearing that VON= 1.2 V, VOFF = 0.4 V and VTS= 0.3 V,the division ratio for the load activation must be

α0 =VTS

VON=

RTS

RTS +RU0= 1/4 (6)

and for the deactivation

α1 =VTS

VOFF=

RTS

RTS +RU1= 3/4. (7)

Thus the up resistance values have to be RU0 ≈ 1 GΩ andRU0 ≈ 100 MΩ. When the circuit is simulated with ideal RU0

and RU1 resistances, the voltage sensor current IV S , harvesteroutput VDC and VS behave as depicted in Figure 13. The loadis activated at VDC= 1.28 V and deactivated at VDC= 0.38 V.To impose the intermittent operation IS = 1 µA and RL =0.3 MΩ.

0 0.05 0.1 0.15 0.2 0.250

0.3

0.6

0.9

1.2

Voltage[V

]

Time [s]0 0.05 0.1 0.15 0.2 0.25

0

50

100

150

200

Current[nA]

IV S

VDC

VS

Fig. 13. Passive system supply VDC , sensed voltage VS and voltage sensorcurrent IV S for an intermittent system operation with IS = 1 µA andRL = 0.3 MΩ.

When using ideal resistors RU0 and RU1 in the voltagedivider, their resistance does not change with temperature.Nonetheless the current increase with temperature, reported insubsection III-A, affects the division ratios α0 and α1 throughRTS . The load imposed by the voltage sensing core at thetransition moment (RTS), decreases with temperature, due tothe current increase. Furthermore, the sensing core transitionvoltage, defined as VTS , increases with temperature. In orderto verify those influences on the VON and VOFF transitions,the generic voltage sensor transition voltage, defined by VTR

is analysed. Once VTR is given by

VTR =

(RU

RTS+ 1

)VTS , (8)

the transition voltages rise significantly with temperature,considering the VTS positive temperature dependence and thedenominator RTS negative temperature dependence. There-fore, a negative temperature dependence has to be introducedin RU so that both VTS and RTS influences can be overcome.

In order to compensate the temperature effect on VTR (VON

and VOFF ), resistors based on diode connected MOS stringsare proposed, Figure 12. This approach is based on the voltagedividers of [20]. According to [21], the gate to source voltage

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Fig. 12. Final voltage sensor circuit schematic.

of a diode connected MOS varies in temperature according toits drain current. For this implementation, the current will beimposed by the sensing core, and its effect on the MOS stringis influenced by three parameters: the transistors type, thenumber of transistors (NU ) and also their aspect ratio (W/L).Considering the nominal temperature case, RU0= 1 GΩ andRU1= 100 MΩ, a subthreshold biasing is required at thetransition time so that the MOS strings can generate suchhigh resistance values. Once the PMOS overdrive voltage hasto be lower than zero to impose a subthreshold biasing, theminimum number of transistors, defined by NU , is 5 for RU0

and 1 for RU1. It is verified that the transistors aspect ratioand the number of transistors used, have different influenceson the VTR temperature dependence. By optimizing the circuitthrough simulation, it is verified that the best temperaturecompensation is achieved for RU0 with NU = 6 and RU1

with NU = 1. Attending at Figures 14 and 15, it canbe perceived that the voltage sensor transitions occur insidethe defined ±10 % tolerance. In fact, the VON variation is±2.75% for and the VOFF variation is ±2.86%. Both theaverage power dissipated and the peak current defined by arebelow the specifications imposed, 10 nW and 1µA, respec-tively. Furthermore, the voltage sensor steady state current at1.2 V is 1 nA.

−40 −20 0 20 40 60 80 1001.08

1,14

1.2

1,26

1.32

Temperature [C]

VON

[V]

Fig. 14. VON for the temperature range.

−40 −20 0 20 40 60 80 1000.36

0.37

0.38

0.39

0.4

0.41

0.42

0.43

0.44

Temperature [C]

VOFF[V

]

Fig. 15. VOFF for the temperature range.

C. Voltage Limiter

In this section, the second part of the developed PCU isreviewed, following a similar analysis to the previous section.The block proposed to perform the voltage limiting is basedon the high level circuit presented in Figure 16. This uses thesame voltage sensing method as the voltage sensor, but withouthysteresis. To create the discharge current Idisc mentioned inthe voltage limiters review (section II-C), a low impedancepath is established by Mdisc. To successfully control Idisc, aCMOS inverter is used to amplify VO. Power down switchescontrolled by P EN are included in the design to block thelimiter operation and the current flow while the load is notactive.

The complete voltage limiter schematic is shown in Fig-ure 17, where the up resistor RUL is implemented by aMOS string to compensate the temperature effect. The voltagesensing core uses the same circuit as the voltage sensor.The discharge control part uses the M3 − M4 inverter asan amplifier to control the discharge current Idisc throughVdisc. Transistors MS1 −MS2 are the power down switches.The P EN transition from VDC to zero activates the limitervoltage sensing function. When VDC=VLim, VO transits fromzero to VS , which decreases Vdisc. The consequent Idiscrise forces VDC to reduce. Thus a feedback loop based onthe voltage supply is verified. Once the voltage limiter issensing VDC when the load active, it is important that the

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Fig. 17. Proposed voltage limiter circuit schematic.

Fig. 16. Voltage limiter structure when turned ON.

leakage current on the limiter does not compromise the powerdissipation specification. Figure 18 displays the VDC , VSVdisc and Idisc plots when a voltage limiting operation isimposed (RL = 0.3 MΩ, IS = 10 µA) and RUL is ideal.Attending at those results, VLim is close to 1.5 V and VDC

stabilizes in the acceptable range by making Idisc= 4 µA.However, it can be verified by Vdisc, that the limiter responseis started at VDC= 1.4 V and the system presents a transientresponse caused by the feedback loop. This factor is mainlylimited by the sensing core long response time, which causesa VDC propagation delay through VO. Furthermore, VLim isdifferent from VDC= 1.4 V, because the sensing core outputat VS=VTS is not sufficiently high to reduce VDC . Thus, Idiscmust be activated for the lowest VDC value that makes VLim

to be contained inside the acceptable range. When RUL isreplaced by the MOS string to compensate the temperatureeffect, the maximum VDC achieved, which is VLim, andthe voltage where VDC stabilizes, defined as final VDC , arepresented in Figure IV-C. RUL is made by 8 PMOS transistorsand the voltage limiting is imposed for the same conditionsused on Figure 18. Attending at the plots of Figure IV-C, itis confirmed that both the maximum VDC (VLim) and finalVDC satisfy the ±10 % tolerance imposed. In fact, the VLim

tolerance to the temperature is ±4.5 %.

0 0.005 0.01 0.0150.15

0.3

0.45

0.6

0.75

0.9

1.05

1.2

1.35

1.5

1.651.65

Voltage[V

]

Time [s]0 0.005 0.01 0.015

0

1

2

3

4

5

6

7

8

9

10

11

Curren

t[µA]

Idisc

VDC

Vdisc

VS

Fig. 18. Voltage limiter transient response for the limiting operation RL =0.3 MΩ and IS = 10 µA.

−40 −20 0 20 40 60 80 1001.48

1.5

1.52

1.54

1.56

1.58

1.6

1.62

1.64

Temperature [C]

Voltage[V

]

VDC finalVLim

Fig. 19. Voltage limiter transient response for RL = 0.3 MΩ and IS =10 µA.

D. Layout and Final Results

When the voltage sensor and limiter blocks are connectedas displayed in Figure 9, the specifications achieved are notsignificantly affected when compared to those obtained forthe separate blocks simulations. The most affected is thepower dissipated during the intermittent operation, due tocontribution of the voltage limiter current. The PCU steadystate current becomes 2 nA. The layout of the proposed PCU

9

with pads is presented in Figure 20, which occupies an areaof 32310 µm2. If pads are not included, the area is only1215 µm2. Besides VDC , ground and P EN , also a P ENpad is included for testing purposes.

Fig. 20. Layout implementation of the proposed PCU with pads.

By performing Monte Carlo simulations to test the inter-mittent operation (IS = 1 µA, RL= 0.3MΩ), it is verifiedthat the circuit does not meet the precision and peak currentspecifications imposed. However, if the temperature range isdecreased to −25 oC to 90 oC and the peak current is allowedto reach 30 % more than the current provided by the harvester(IS), the circuit yield increases. Based on these changes,when the PCU is simulated for the intermittent operationthe final yield is 88 %. Furthermore, the maximum powerdissipation is below 6.2 nW. Considering the voltage limitingoperation, which is imposed by setting IS = 10 µA andRL= 0.3 MΩ, the yield obtained is 90 %. However, the circuityield decreases if the current provided by the harvester (IS)increases to 20 µA. This is caused by the voltage sensing coreslow response. Consequently, the circuit can only be assuredto verify the specifications imposed when it is applied ona system that presents a t0 = 57 ms, ∆tON= 33 ms and∆tL= 3.3 ms. t0 corresponds to the system start-up time,∆tON to the load active period and ∆tL to the time periodbetween the load activation and VDC=VLim.

TABLE IRESULTS OBTAINED FOR POST-LAYOUT SIMULATIONS ON MOS PROCESS

CORNERS AND −25 TO 90 OC RANGE.

ProcessCorner

VON

(µ± ∆) [V]VOFF

(µ± ∆) [V]Pav

[nW]IP

[µA]VLim

(µ± ∆) [V]Typical 1.167 ± 0.032 0.396 ± 0.012 5.8 0.92 1.5 ± 0.05

SS 1.188 ± 0.104 0.405 ± 0.012 10.1 0.88 1.498 ± 0.19SNFP 0.655 ± 0.061 − 0.92 0.2 0.863 ± 0.109

FF 1.174 ± 0.08 0.396 ± 0.032 13.76 1.2 1.546 ± 0.094FNSP 1.755 ± 0.071 0.613 ± 0.028 14.1 2.4 2.18 ± 0.068

Target [1.08; 1.32] [0.36; 0.44] < 10 < 1.3 [1.35; 1.65]

The results obtained by simulating the extracted circuitfor MOS process corners and temperature range (−25 oC to90 oC) are presented in Table I. Once it is a temperaturesweep, the mean (µ) and (∆) variation are indicated for eachtransition voltage. For Pav and Ip only the maximum valuesare presented. As it can be verified, the specifications are notmet for all the corners, therefore the research goals are notmet. In fact, a variation as high as ±55 % is verified for thetransition voltages VON , VOFF and VLim, considering all theprocess corners. That is due to a shift in the mean value ofthe sensing core transition voltage VTS for mixed corners.

Table II, compares the specifications achieved to the state-of-the-art PCUs literature. Analysing the presented results,the maximum current achieved by the circuit in nominalconditions is below the other results. However, the proposedPCU does not include a regulator, which would impose ahigher current on the discharge phase, as happens on [7].Compared to state-of-the-art voltage sensors [11], [12], whichpresent a ±4.8 % precision to process corners on a temperaturerange from −40 oC to 105 oC, the tolerance achieved by thiswork (±55 %) is inferior. However, the current required in thiswork is 2 nA and in the state-of-the-art is 6.8 nA.

TABLE IICOMPARISON OF THE PCU SPECIFICATIONS.

Reference This Work [7] [10]Load Activation V. 1.2 V 1.75 V 2.75 V

Load Deactivation V. 0.4 V 1.2 V 1.9 V

PCU BlocksSensor,Limiter,

Reference

Sensor,Limiter,

Reference,Regulator

Sensor,Limiter,

Reference,Regulator

PCU Current 2 nA80 nA@ charge100 µA@ disc. 1.5 µA

Table III compares the specifications achieved for the mostprobable process variation event (yielded by Monte Carlo)with those proposed in the research goals. The average poweris below the target and the worst transition precision can reach±17 %, which does not meet the target. However it is verifiedthat 88 % of the circuits present a tolerance below or equal to±10 %. The remaining specifications do not satisfy the initialtargets.

TABLE IIICOMPARISON OF THE ACHIEVED SPECIFICATIONS AND TARGET

SPECIFICATIONS.

Specification Target AchievedTransitionTolerance ±10% ±17%

AveragePower 10 nW 6.2 nW

PeakCurrent 1 µA 1.2 µA

Temp.Range [−40 100] oC [−25 90] oC

10

V. CONCLUSIONS

This work proposes the design of a PCU implementable onpassive systems based on low power external energy sources.In order to verify the role of a PCU in a system composed byan energy harvester and a load circuit, known as a passivesystem, a study of its high level model is proposed. Thisallows the characterization of three different system opera-tions: intermittent, continuous and voltage limiting, which isa special case of the continuous. The intermittent case provesto be more advantageous for low power applications, onceit requires the lowest input power. The voltage limiting is theextreme operation mode, where the PCU must limit the powerdelivered to the load, so that it is not damaged.

In this work, a voltage sensor is needed to apply theintermittent operation and a voltage limiter for the limitingoperation. The circuits are designed in the UMC 130 nmtechnology with high speed transistors only. The load isactivated at 1.2 V (VON ), deactivated at 0.4 V (VOFF ) andits supply cannot surpass the 1.5 V(VLim). The voltage sensorrelies on a voltage sensing core circuit based on subthresholdbiasing to achieve a low power dissipation, required for thepassive system to be power efficient. The core combinesa CMOS inverter connected to a modified 2T referencecircuit. To provide the sensing core supply voltage and thehysteresis sensor behaviour, two voltage dividers are used.Those are based on the resistance implemented by a stringof diode connected MOS and the sensing core equivalentresistance. By applying the correct number of MOS and aspectratio, the VON , VOFF and VLim transitions are temperaturecompensated, yielding a maximum tolerance of ±10 %. Dueto the sensing core slow response, Monte Carlo analysis provethat the circuit performance is severely dependent on thevoltage supply charge and discharge rates. The final circuitis implemented at layout level and it is verified that thespecifications achieved do not meet those initially imposed.That is mainly due to the sensing core circuit high sensitivityto mixed process corners, which leads to a ±55 % toleranceon the transition voltages. However the PCU power dissipation(6.2 nW) is still below the power provided by state-of-the-artharvesters (1 µW). Considering the transition voltages ±10 %tolerance, an 88 % yield is verified for Monte Carlo processand temperature variations. Thus, the circuit only does notachieve the target specifications for process corners.

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