PollEx Updates Period: 2019.01.01~2019.09.30 30 September 2019 Interface - ODB++ Added Option: “User Setting Layer” menu is added to get the certain layer from ODB++. Interface - Allegro Expansion Added Option: Hatched display is supported for polygon shape.
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PollEx Updates Period: 2019.01.01~2019.09.30 30 September … · 2019-09-30 · Tools - PCB Data Extractor Added Option: It is added to export property of each net. Interface - Altium
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PollEx Updates
Period: 2019.01.01~2019.09.30
30 September 2019
Interface - ODB++
Added Option: “User Setting Layer” menu is added to get the certain layer from ODB++.
Interface - Allegro Expansion
Added Option: Hatched display is supported for polygon shape.
Component Arrangement Plan - Setting
Added Option: It is able to export with having file name(*.caps) and date of ECAD file on
PDF.
Option - Attribute Finder/Search Parts Using Pin Pitches
Added Option: ‘Long Pin Pitch’ information is added.
Tools - PCB Data Extractor
Added Option: It is added to export property of each net.
Interface - Altium Designer
Added Option: Reference is distinguished if partition is different even though they are using
same reference name.
File - Export To
Added Option: The property can be added when netlist exports for Mentor Graphics’ PADS
format.
Setting
Added Option: ‘Close All’ button is added.
Environment - DFM
Added Option: Added option to Limit the number of CPU Core to use
New Items/DFM Input Manager
- Added new item to register and manage multiple DFM Input files
- Added synchronize feature from DFM Item settings to the other DFM infput file
DFM Input
Added Option: Added option to set Point Tool per each DFM Input file
Board – Guide Hole
Added Option: Enhanced the setting type of Guide Hole location check
Added Option: Added Center Guide Hole and Guide Hole clearance checking option
- Guide Hole location setting by the standard position of board (Left-Top, Left-Bottom,
Right-Top, Right-Bottom)
- Added option to check if Center Guide Hole exists in the design.
- Added option to check the clearance between Guide Hole and Route Pattern or Copper-Pour.
The clearance can be checked by Top, Bottom and Inner layer.
Board – PCB Outline Spacing
Added Option: Added option to check the clearance of PCB Outline according to the
component direction
Added Option: Added option to check the clearance between PCB Outline and component’s
Solder Mask.
Board – Routing Slit
Added Option: Added option to recognize as the measure base area where Routing Slit Layer
and user defined layer line overlap
Board – Sub Board Placement
Added Option: Added option to check Misalignment Mark and added check box per each
checking item
- Added option to check the Misalignment Mark existence where the mark is specified and
to check the mark width
- As the Misalignment Mark check item is added, the check box is added on the existing
menu.
Board – Min Silk Width
Added Option: Added option to exclude special characters when checking text size. When the
option is selected, special characters are excluded from the checking (only numbers and
alphabetical characters are checked)
Component - OSP
Added Option: Added option to exclude Through-Hole Type Pad from checking
Added Option: Added option to exclude Pads having OSP from checking
Component – First Pin Mark
Added Option: Added option to define the First Pin Mark shape
Component – Reverse Placement Spacing
Added Option: Added option to recognize as Pad area where conductive shape and solder
mask overlap
Etc. – TCP Pad
Added Option: Added option to check the minimum size of TCP Pad
Etc. – TCP Dummy Pad
Added Option: Added option to check the clearance between TCP Dummy Pad and Copper-
Pour
Added Option: Added option to exclude components on clearance checking between keep-out
area of TCP Dummy Pad and component
Etc. – Text Existence
Added Option: Added option to check the existence of prohibited string in the design
Etc. – Text Existence
Added Option: Added option to check the existence of string from left side of the PCB
Design Name to user specified position.
FPCB – Figure Layer
Added Option: Added measure base for components to be checked (Solder Mask, Pad/Solder
Mask Overlap)
Added Option: Added option to check only the Layer Object related to the specified
component
Pad – Silk on Pad
Added Option: Added Measure Base setting option for the target pad
Pad – Solder Resist Pad
Added Option: Added option to check whether a specific part area is covered with Solder
Mask.
Pattern – Unrouted Net
Added Option: Added option to exclude specified components from checking.
- The option is exclude checking the specified components when not connected to Net
although GND Net Name of the component is assigned.
Placement – Mark Placement
Added Option: Added option to check the Mark position from the reference point of the PCB
Board Left Top, Left Bottom, Right Top, Right Bottom)
Placement – Placement
Added Option: Added option to select the Soldering Direction as the long side of the board
Added Option: Added option to check symmetric placement
Placement – Placement Keepout
Added Option: Added option to set Keepout area considering component direction
Tooling – Screw2
Added Option: Added option to exclude the Net connected to the Screw from checking
Excel Export/Export Result Table “Main Item List” and “Sub Item List” sheets are added to the Excel Report File.
HighSpeed/Routing Area Ratio - Modify Layer selection method: user can set “Inner Layer” and “Outer Layer”.
DFE Input/Define Differential Pair Add feature: User can preview the selected differential net paring result.
Net/Via Quantity Added Option: Added option to verify VIA quantity around defined components.