PLDs

Slide 1

EET 1131 Unit 4Programmable Logic Devices Read Kleitz, Chapter 4.Homework #4 and Lab #4 due next week.Quiz next week.1FIRE UP QUARTUS-Do Quiz #3.Handouts: page 5 of GAL22V10 datasheet; SPLD Practice sheet and Converting practice sheet; Altera board; Altera board assignment sheetProgrammable LogicSPLD (Simple PLD): the earliest type of programmable logic, used for smaller circuits with a limited number of gates. CPLD (Complex PLD): contain multiple SPLD arrays and inter-connection arrays on a single chip.FPGA (Field Programmable Gate Array): a more flexible arrangement than CPLDs, with much larger capacity. Programmable Logic Devices (PLDs) are chips with a large number of gates that can be configured with software to perform a specific logic function. Major types of PLDs are: 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved2Approximate Equivalent DensitiesThe Lattice GAL22V10 (a popular SPLD) is equivalent to about 500 logic gates.

A typical Altera MAX7000 CPLD is equivalent to about 2500 logic gates.

A typical Altera Cyclone FPGA is equivalent to about 50,000 gates.

4Major PLD ManufacturersThree big names in this field are Xilinx, with 51% of market shareAltera, with 34%Lattice, with less than 10%

Market share numbers retrieved from Wikipedia on 9/10/2014.

5Some Product Lines from Altera and XilinxAlteraCPLDs: MAXFPGAs: Cyclone, Arria, StratixProgramming software: Quartus IIXilinx:CPLDs: CoolRunner, XC9500FPGAs: Vertix, Spartan, Kintex, ArtixProgramming software: ISE

6PALs and GALsPALs have a one-time programmable (OTP) array, in which fuses are permanently blown, creating the product terms in an AND array. SPLDs contain arrays of gates. Two important kinds of SPLD are PALs (Programmable Array Logic) and GALs (Generic Array Logic). A typical array consists of a matrix of conductors connected in rows and columns to AND gates.Simplified AND-OR arrayXA A B B

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved7XA A B B

What expression is represented by the array?ExampleX = AB + ABPALs are programmed with a specialized programmer that blows selected internal fuse links. After blowing the fuses, the array represents the Boolean logic expression for the desired circuit.PALs 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved8The GAL (Generic Array Logic) is similar to a PAL but can be reprogrammed. For this reason, they are useful for new product development (prototyping) and for training purposes.A A B BX

GALs were developed by Lattice Semiconductor. GALs 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved9PALs and GALs are often represented by simplified diagrams in which a single line represents multiple gate inputs. The logic shown is for the same circuit shown earlier.

Input bufferA A B BSingle line with slash indicating multiple AND gate inputsFuse blownFuse intactABABAB + ABPALs and GALs 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved10The GAL22V10 is a typical SPLD. It has 12 dedicated inputs pins and 10 pins that can be used as inputs or outputs.Link to datasheetGAL22V10

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved11-This chip contains 5892 reprogrammable fuses. -Each AND gate has 44 inputs.-Do SPLD practice sheet.CPLDsA complex programmable logic device (CPLD) has multiple logic array blocks (LABs), each roughly equivalent to an SPLD. LABs are connected via a programmable interconnect array (PIA). Various CPLDs have different structures for these elements.

The PIA is the interconnection between the LABs. 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved12FPGAs compared to CPLDsCPLDsFPGAsBased on programmable AND array and fixed OR array.Based on look-up table (LUT), which is basically a truth table. (Results in higher density.)Both are programmed using the same software, using either schematic entry or text entry.13-Two different but equivalent ways of specifying a logic function: by drawing schematic diagram with ANDs and ORs, or by giving truth table. CPLD implementation is like the former, while FPGA is like the latter.-A look-up table is like a memory in which you provide the address and the chip reads out what is stored at that address.Programmable Logic SoftwareAll manufacturers of programmable logic provide software to support their products. The process is illustrated in the flowchart.

The first step is to enter the logic design into a computer. It is done in one of two ways:1) Schematic entry2) Text entry using a hardware description language (HDL). 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved14Programmable Logic SoftwareIn schematic entry, the design is drawn on a computer screen by placing components and connecting then with simulated wires. After drawing the schematic, it can be reduced to a single block symbol:

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved15Programmable Logic SoftwareIn text entry, the design is entered via a hardware description language (HDL).Learning an HDL takes longer than learning to do schematic entry. But for complex designs it can provide a more powerful and simpler way to enter designs.

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved16Some Popular Hardware Description LanguagesOpen-standard HDLsVHDL (IEEE 1076)Verilog (IEEE 1364)Proprietary HDLsCUPLABEL (Advanced Boolean Expression Language, now owned by Xilinx)AHDL (Altera HDL)

17A VHDL SampleOne way of writing VHDL programs is to use Boolean-type statements. There are two parts to such a program: the entity and the architecture. The entity portion describes the I/O. The architecture portion describes the logic. Following is a short VHDL program showing the two parts. entity Example isport (B,C,D: in bit; X: out bit);end entity Example;architecture Behavior of Example isbegin X