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PLD State Machine DesignELCTEC-131

State Machine Definitions State Machine:

◦ A synchronous sequential circuit consisting of a sequential logic section and a combinational logic section.

The outputs and internal flip flops (FF) progress through a predictable sequence of states in response to a clock and other control inputs.

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State Machine Types Moore Machine:

◦ A Finite State Machine (FSM) whose outputs are determined only by the Sequential Logic (FF) of the FSM.

Mealy Machine:

◦ An FSM whose outputs are determined by both the sequential logic and combinational logic of the FSM.

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State Machine Basics State Variable:

◦ The variable held in the SM (FF) that determines its present state.

A basic FSM has a memory section that holds the present state of the machine (stored in FF) and a control section that controls the next state of the machine (by clocks, inputs, and present state).

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Basic Block Diagram

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FSM Design Techniques Classical Design:

◦ Makes use of state tables, FF excitation tables, and Karnaugh Mapping to find FF input control logic.

VHDL Design:

◦ Uses case statements or IF THEN ELSE statements to set the design and the logic synthesis tools to define equations.

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Classical Design Approach Define the actual problem.

Draw a state diagram (bubble) to implement the problem.

Make a state table.

◦ Define all present states and inputs in a binary sequence.

◦ Then define the next states and outputs from the state diagram.

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Classical Design Approach Use FF excitation tables to determine in

what states the FF inputs must be to cause a present state to next state transition.

Find the output values for each present state/input combination.

Simplify Boolean logic for each FF input and output equations and design logic.

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FSM Design Example 1

Gray Code Counter that sequences

◦ {000, 001, 011, 010, 110, 111, 101, 100, 000}.

From this the state and excitation table is developed for D flip flops (see Table 10.2 in the textbook).

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State Diagram

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State Table

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K-Maps

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FSM Design Example 2

From the K-Maps for the inputs D0, D1, and D2, the following equations are developed:

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12120

02011

02012

QQ QQ D

QQ QQ D

QQ QQ D

+=

+=

+=

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Simulation

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VHDL FSM Design Uses an enumerated type to declare state

variables.

Enumerated Type: A user-defined type in which all possible values of a named identifier are listed in a type definition.

An FSM uses a CASE statement on the enumerated type state variable.

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FSM VHDL Example

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-- gray_ct1.vhd

-- 3-bit Gray code counter

-- (state machine with decoded outputs)

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

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FSM VHDL Entity

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ENTITY gray_ct1 IS

PORT(

clk : IN STD_LOGIC;

q : OUT STD_LOGIC_VECTOR(2 downto 0));

END gray_ct1;

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FSM VHDL Architecture

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ARCHITECTURE a OF gray_ct1 IS

TYPE STATE_TYPE IS (s0,s1,s2,s3,s4,s5,s6,s7);

SIGNAL state :STATE_TYPE;

BEGIN

PROCESS(clk)

BEGIN

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FSM VHDL Architecture

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IF (clk’EVENT AND clk = ‘1’) THEN

CASE state IS

WHEN s0 => state <= s1;

WHEN s1 => state <= s2;

WHEN s2 => state <= s3;

WHEN s3 => state <= s4;

WHEN s4 => state <= s5;

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FSM VHDL Architecture

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WHEN s5 => state <= s6;

WHEN s6 => state <= s7;

WHEN s7 => state <= s0;

END CASE;

END IF;

END PROCESS;

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FSM VHDL Architecture

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WITH state SELECT

q <= “000” WHEN s0,

“001” WHEN s1,

“011” WHEN s2

“010” WHEN s3,

“110” WHEN s4,

“111” WHEN s5,

“101” WHEN s6,

“100” WHEN s7;

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VHDL Output Assignment

The output assignment for the following example could have also been in the CASE test statements (in the process).

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WHEN s0 => state <= s1;

q <= “001”;

WHEN s1 => state <= s2;

q <= “011”;

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FSM with Control Inputs

Same design approach used for FSM such as counters.

Uses the control inputs and clock to control the sequencing from state to state.

Inputs can also cause output changes not just FF outputs.

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FSM with Control Inputs

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SM Diagram Notation Bubbles contain the state name and

value (StateName/Value), such as Start/000.

Transitions between states are designated with arrows from one bubble to another.

Each transition has an ordered Input/Output, such as in1/out1.

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SM Diagram Notation For example, if SM is at State = Start and

if in1 = 0, it then transitions to State = Continue and out1 = 1, out2 = 0.

The arrow is drawn from start bubble to continue bubble.

On the arrow the value 0/10 is given to represent the in1/out1,out2.

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SM Design

State Table for the State Diagram

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Present Status Input Next State Sync. InputsQ in1 Q JK out1 out20 0 1 1X 1 00 1 0 0X 0 01 0 0 X1 0 11 1 0 X1 0 1

Outputs

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SM Design

The State Excitation Tables for the JKInputs

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Transition JK

0 to 0 0X

0 to 1 1X

1 to 0 X1

1 to 1 X0

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SM Design

The following equation represents the next state and output logic of the state machine.

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Qin1Qin1Q out2

in1Q out1

1 Kin1 in1Q in1Q J

=•+•=

•=

==•+•=

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SM Design

The pulser SM has two outputs that are not always synchronized to clock.

The pulse out2 is always synched to a change in clock, but out1 could change if in1 changes.

The following slides show a BDF implementation of the Pulser SM.

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SM Design

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Simluation Results

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SM Pulser Architecture

Uses an enumerated type state listing of start and continue.

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ARCHITECTURE a OF state_x1 IS

TYPE PULSER IS (start, continue);

SIGNAL sequence : PULSER;

BEGIN

PROCESS(clk)

BEGIN

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SM Pulser Architecture

A portion of the case statement:

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IF(clk’EVENT AND clk = ‘1’) THEN

CASE sequence IS

WHEN start =>

IF in1 = ‘1’ THEN

sequence <= start;

out1 <= ‘0’;

out2 <= ‘0’;

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SM Pulser Architecture In the VHDL case statement, an IF

conditional test statement was used to check the Input Signal (in1) for State = Start.

IF in1 = 1, stay at State = Start; IF in1 = 0, then move to State = Continue (next clk).

If the present state was continue, the next state is always start, so an IF statement is not required.

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