Place and Route With SoC Encounter12313

9/8/2015 PlaceandRoutewithSoCEncounter

http://vlsicad.ucsd.edu/courses/ece260bw05/Lab2/Lab2.php 1/20

PlaceandRoutewithSoCEncounterHome|Labs

Version03Datemodified:01/25/2004

Instructions(READCAREFULLY)

ImportantnoteforLab2experiments

1.PleasereadthroughthetutorialandworkwithSoCEncounterinparalleltoknowvariousknobsavailableinthetool.

2.AnSoCEncounterDesignFlowGuideandTutorialcanbefoundat/home/ostl/cs241w/software/SOC32/doc/soceflow/soceflow.pdf.Thiswillprovideyouwithalittleunderstandingofwhatthistoolisusedforandwhatitsfeaturesare.

3.Thetutorialmakesyouworkthroughastraight(floorplanplacerouteextractiontiminganalysis)flow(Flow1).SOCEallowsyoutoperformincrementaloptimizationsateachofthesestepsandhenceinthelab,youwillbeworkingonanupdatedflowgivenatthebeginningoflab.Thisflow,whileprincipallyidenticaltoFlow1,enhanceseachstepandperformsmoredetailedoptimizationsforimprovingtimingofthedesign.

4.Inthelabpart,youwillbeworkingontheenhancedflow(Flow2).YoucanchoosetoworkwiththeSOCEGUIortheSOCEcommandlineorbothinparallel(asyoudidwithBuildGatesPKS).

Youcanperformexactlythesamesetofsteps(giveninFlow2)withboththeGUIandthecommandline.

5.Twoveryimportantreferencesare:(a)TheSOCEuserguide,foundat/home/ostl/cs241w/software/SOC32/doc/encounter/encounter.pdf(b)TheSOCEtextcommandreferencemanual,foundat/home/ostl/cs241w/software/SOC32/doc/fetxtcmdref/fetxtcmdref.pdf.Refertothesedocumentsforhelp.

6.Duetocontinuousenhancementstoscripts,configfilesetc.,filenames/paths/defaultvaluesofitemsinthetutorialscreenshotsmaydifferfromwhatyouwilluse.Donotpanic:).ThedirectorystructureusedforthislabisexactlythesameasyouusedinLab1.Youshouldbeworkingfromthetopleveldirectory(thatcontainssrc/run/output/andcmd/directories)inorderfortheflowtoexecutesmoothly.Youmightafacelittledifficultyinrunningthetutorialforthefirsttime,andthatisnotuncommon.

7.DownloadthetarpackageforLab2fromhere.Thispackageincludessynthesizednetlistinsrc/netlistdirectoryandtimingconstraintfileinsrc/sdcdirectory.Youdonotneedtoperformsynthesisagaintoobtainthesefiles.

8.LinktoflashtutorialsonplaceandrouteusingSoCEnconter

ABSTRACT

ThislabwillstartwithanintroductiontutorialtotheplaceandrouteflowinSOCEncounter.CadenceSOCEncounterisaversatiletoolwhichtakesadesignfromtheRTLsignoffstagetotheGDSIIformat.Inthislab,wewillfirstfollowthetutorialtogetacquaintedwiththetoolsothatyougainanunderstandingofthebasicplaceandrouteflow.Thelabsection(questions)arebasedonanenhancedflowthatperformsdetailedoptimizationsateachstage.Wewillrunthetoolwiththisflowtomeetspecifictiming/areaobjectives.

ForthistutorialweuseasynthesizedVerilogfile(.sv)oftheAEScorefromtheSynthesislab(providedinthetarpackageabove)alongwithArtisanTSMC0.13umtimingandphysicallibraries.

1.Tutorial

Inthistutorial,weuseSOCEncounter(SOCE)3.2(v03.20p005_1)onx86serversrunningRedHatEnterpriseLinux.SOCEcanberuneitherfromacommandlineorfromaGUI.Togetacquaintedwiththetool,wewillusetheGUIinitially.However,werecommendyourunthetoolfromthecommandlineonceyouarefamiliarwithit.Thiswillhelpyouwritetclscriptsthatcanbeusedtoautomatetheflowandrunitinbatchmode,aswedidinLab1.

Inthistutorial,wefollowthesectionoftheflowindicatedinorange.Startingwithinitializationandfileimport,weperformfloorplaning,placement(withAmoebaPlace),andclocktreesynthesisandrouting(withNanoRoute).WethenperformRCextractionwiththeSOCEinbuiltextractorandperformtiminganalysiswiththeCommonTimingEngine.



Initialization

Togetstarted,youneedtosetupyourenvironmentvariablesandorganizeyourdirectories.Forthistutorial,youareprovidedwitha.tar.gzpackagecontainingallthefilesyouneed.FollowthesestepstoinitializeandrunSOCE.

Createdirectorystructure[cs241wzz@ostl10~]$pwd/home/ostl/cs241w/cs241wzz[cs241wzz@ostl10~]$tarzxfLab2.tar.gz[cs241wzz@ostl10~]$cdLab2[cs241wzz@ostl10~/Lab2]$lscmd/output/run/src/SetupSOCEenvironment//SetpathstoSOCE3.2andothertools[cs241wzz@ostl10~/Lab2]$source~/../public/cshrc

TostartSOCE[cs241wzz@ostl10~/Lab2]$encounter(1)[cs241wzz@ostl10~/Lab2]$encounternowin(2)

Use(2)ifyouexplicitlywanttoinitializeEncounterwithouttheGUI.Ifyouuse(1),youwillgettheSOCEGUIaswellastheencounter>shellontheterminalfromwhichyouinitializedSOCE.(shownbelow)



Hereisthedirectorystructureforyourreference.Theaesdirectorymaydifferonyoursystem,dependingonwhatnameyoudecidedtouseforyourtoplevelLab2directory.

Afterinitialization,theSOCEGUIshowsup.Thefirststepistoimportdesign,tech,library,LEFandconstraintfiles.Toimportfiles,clickonthethe"Design"menu.

Theloaddesignmenupopsupandyoucanentertherelevantfilesintheboxprovided.Wedescribeeachtypeoffilesbelow.



Inthe"Design"tab,loadallinputfilespertainingtothedesign.Thesefilescanbefoundinsimilarlocationstowhereyoufoundtheminthepreviouslab.Thecommandlineequivalentstothisstepcanbefoundincmd/encounter/aes_cipher_top.conf

EnterthesynthesizedVerilognetlistfileaes_cipher_top.svin"VerilogFiles".

TheILM(InterfaceLogicModeling)filesspecifytheinterfacenetlist(thisisoptional).Inourcase,youmayleavethisblank.

"Topcell"isthenameofthetoplevelVerilogmoduleinthesynthesizednetlist.

SpecifytheLEFfile(s)inthephysicallibrarysection.[LEFfile=tsmc13fsg_6lm.lef]

IntheFETechnologyfilessection,specifythetechnologyfile(.tech)thatcontainsgeometricandcapacitanceinformationofvariouslayersofthechosentechnology.[Techfile=tsmc13fsg_6lm.lef.tech]

IntheStd.CellLibrariessection,specifythelistoflibrarycelldumpfiles.[Celldumpfile=tsmc13fsg_6lm.lef.cdump]

FEtechfilesandStd.celllibraryfilesarecreatedfromLEFfilesusingtheutilityreadlef.YoucanfindmoreinformationabouttheutilityfromtheSOCEmanual.

Loadtiminglibraries(.tlforSynopsys.lib)filesinthe"TimingLibraries"section.Thisspecifiesthetiminginformationofvariouscellsinthelibrary.

The"Footprints"sectionspecifiesthenamesofbuffer,delayelement,andinverternamesinthelibrary.Thissectionisoptional.YoucanloadIOpinassignmentinformationinthe"IOinformation"section.Ifyoudonotspecifythis,IOassignmentwillbeperformedrandomly.WestronglysuggestyoutosavetheIOassignmentaftertheinitialrunanduseitforeveryrunafterwards.Thishelpsinstudyingtheimprovementinvariousstepsoftheflowstartingfromthesameinitialpoint.

The"CoreSpecDefaults"tabshowsthedefaultaspectratioandrowutilizationratioofthedesign.Thesearesetto1.0and0.6respectively.Youcanchangetheseparametersduringthefloorplanningstage.

Inthe"Timing"tab,youcanentertimingconstraintfiles,capacitancetablesforRCextraction,andotherrelatedparmeters.



Forthistutorial,wewillonlyloadthetimingconstraintfile(whichweusedforsynthesis)andretainallthedefaultvalues.Formoreinformationonchangingthedefaultvalues,refertotheSOCEmanual.

Inthepowertab,youcanspecifynamesofthepowerandgroundnets(VDDandVSS)alongwiththetoggleratescalefactorforpoweranalysis.ThisfactorsetsthescalingvaluethatisusedtomultiplythetogglerateinthePowerAnalysisformtoanewscaledvalue.Thedefaultvalueis1.0,whichmeansthatnotogglescalingisdone.Youmayleavethisfieldblank.



Underthe"misc"tab,thereareoptionsforenteringtheSignalStormdatabase,Fire'n'Ice(RCextractor)techfiles,CeltICdatabasefiles.



However,wedonotusethesetoolsforcurrenttutorial,soyoucanleavetheseboxesempty.Clickon"OK"afteryouhaveenteredpathstoallrelevantfiles.IttakessometimeforSOCEtoloaddesignfiles,librariesandconstraints.Thesefilescanalsobeloadedfromthecommandline.Youcanspecifyallinputfilesina.conffile(forexample,aes_cipher_top.conf)andusethefollowingcommandtoloadit.

encounter>loadConfigaes_cipher_top.conf

Thefileaes_cipher_top.confispresentincmd/encounter/directorywithallappropriatepathsset.Tosavetimeinfuturerunsyoucanwritethedesignimportprocesstoa.conffileusingthe"Save..."buttoninthebottomofdesignimportdialogbox.

Floor&Powerplanning

Inthisstep,weperformfloorplanningofthedesign.Toinitializethefloorplan,goto"Floorplan"andchoosethe"SpecifyFloorplan"option.



Thefollowingmenupopsupandyoucanchoosevariousoptionstospecifyafeasiblefloorplan.Inthisstep,youwillspecifytheaspectratioofthedie(usuallysetto1.0),therowutilizationratio,andthecoretoIOdistance,amongotheroptions.



Theaspectratioisspecifiedusing"Ratio(H/W)".Thisratiois1.0bydefault.Thecoreutilizationcorrespondstotherowutilizationratioofthestandardcells.Dependingonthetypeofdesign,thisnumberhastobespecifiedappropriately.Highutilizationratios(typically>0.75)resultinhighcongestionduringroutingresultinginunroutabledesigns.

TheAEScoreisheavilyinterconnectdominated.Topreventcongestion,wechoosearowutilizationof0.6.Insubsequentruns,youcantryincreasingtherowutilizationandobserveitsaffectoncongestionandtiming.

Inthe"CoreMarginsby"section,youcanspecifythecoretoIOdistanceonallfoursidesofthecore.ThisnumberhastobechosenbasedonthenumberofIOsinthedesign.IfthenumberofIOsistoolarge,thenthecoretoIOdistanceshouldbelargeenoughtoreduceIOdensityattheboundary.Inourtutorial,weuse15umspacings.

RowtoRowspacingcanbespecifiedin"StandardCellRows"box.Thedefaultvalueissetto0.0um.Afterloadinginallvalues,clickApply.Allthevalueswillbeadjustedslightlytocreateafeasiblefloorplan(observethattheaspectratioischangedto0.99990525andthecoremarginwidthsarechanged).ClickOKtoclosethedialogbox.

Thenextstepintheflowispowerplanning.Inthisstep,youwillcreateapowerringandpowerstripestocreateapowerdistributionnetworkforcellsinthedesign.Clickon"FloorplanPowerPlanningAddRings".



Thefollowingwindowpopsupandyoucanspecifytheringtypeandconfiguration.Youcanplanthepowerdistributionnetworkinvariousmodestofacilitatecreationofvariousdesignstyles.Inthistutorial,werestrictourselvestocorerings.

The"ringconfiguration"optionsspecifywhichmetallayerstouseforeachsideoftheringaswellasthedesiredwidthsandspacings.WechooseMETAL4fortopandbottomsidesandMETAL3forleftandrightsides.ThewidthsandthicknessesoftheseshouldcorrespondtowirewidthsandthicknessesinLEFfile.



Afteryoucreatearing,createpowerstripes.Choose"FloorplanPowerPlanningAddStripes"fromthemenu.Thefollowingwindowpopsup.



Settosetdistancespecifiesthedistancebetweentwosetsofstripesconnectingpowerrings.Powerstripesshouldbespacedcorrectly.Toomanypowerstripescreateroutingblockagewhichmakesroutingdifficult.Toofewpowerstripesresultsinpoorpowerdistributiontothecellsandwasteswiringresourcesonthelowermetallayers.

Forthistutorial,enterasettosetdistanceof50um.Topreventpowerstripesfrombeingplacedalongtheedgesofthedie,youcanspecifyastripeoffsetboundaryvalue.ClickOKafteryouenterallrelevantvalues.

AlthoughfloorplaningcanalsobeperformedusingcommandlineequivalentsofGUIoperations,itisrecommendedthatyourinitialfloorplanbeperformedusingtheGUIsothattheusergainsabetterunderstandingoftheprocess.Therearevarioustools(pointer,resizing,reshaping,cloningetc)thatyoucanalsousetodofloorplanning.MoreinformationontheuseofthesetoolscanbefoundintheSOCEmanual.

Yetanotherfloorplanningmethodisusingtheblockplacer.ThisanalyzestheconnectivitybetweenblocksandIOsandperformsfloorplanning.Toinitializeit,choose"FloorplanPlaceBlocks/ModulesPlace"fromthemenu.ChoosetheoptionspresentinthewindowandclickonOK.Thetoolperformsblockplacementanddisplaysoneofthepossiblefloorplansolutions.Youcanviewothersolutionsbychoosing"FloorplanPlaceBlocks/ModulesViewPlacementSolutions"fromthemenu.ClickOKtoacceptasolution.Showninthefigurebelowisonesuchfloorplansolution.

REMEBER:Thefloorplansolutionshownhere(obtainedbyblockplacement)cannotbereplicatedexactly.Itdependsonyourchoiceofparameters.Thisisshownasanexampleofwhatyoumightget.Forlargehierarchicaldesigns,partitioningandfloorplanningareverycrucialsteps.Thequalityoftheplacement,routingandthereforetimingdepends,toalargeextent,onthefloorplan.



Placement

Inthisstep,youwillperformtimingdrivenplacementusingAmoebaPlace.Choose"Place"fromthePlacemenuandthefollowingwindowpopsup.

Choosetheplacementeffortlevel:prototyping,low,mediumorhigh.Ifyouaretryingtoevaluatethequalityofthepartitioningorfloorplanningstep,chooseprototyping.Forourtutorial,choosemediumeffort.Timingdrivenplacementisenabledbyclickingonthecheckboxlabeled"TimingDriven".Check"SaveNewNetlist"tosavethemodifiednetlistwhichmayhavewithbuffersinsertedbytheplacer.

Tominimizecongestion,theplacercanalsoberunwithcongestionoptimizationturnedon.Thisoptionisnotavailableinthewindowyouseeabove.Todothis,runthefollowingcommandfromtheencountershell.

encounter>amoebaPlaceslowtimingdrivendoCongOpt

Ittakessometimeforthetooltoperformtimingdrivenplacementwithcongestionoptimization.Themodifiednetlistwillbesavedtothefileaes_cipher_top.post_tdp.v.*YoucanviewtheplacementusingtheGUIafterthisstep.Youcandoubleclickonaparticularcelltoviewitsproperties(location,size,name,#ofconnectionsetc.).



Afterperformingplacement,addfillercellstomakethechipuniformlydense.Choose"PlaceFillerAddFiller"fromthemenu.Specifythenamesoftypesfillercellsinthefollowingwindow.

AfteraddingFILL64cells,addFILL32,FILL16,FILL8,FILL4,FILL2andFILL1,inthatorder.

ClockTreeSynthesis

Toperformclocktreesynthesis(CTS),afilecontainingclockspecificationsneedstobeimportedtoSOCE.Thisfileisalreadyincludedtheinsrc/cts/directory.Foryourreference,itisshownbelow

#ClockSynthesisFile

AutoCTSRootPinclkNoGatingNOMaxDelay2.5nsMinDelay2nsMaxSkew100psMaxDepth20BufferCLKBUFX20CLKBUFX16CLKBUFX12CLKBUFX8CLKBUFX2End

Thisfilespecifiestheclocksignalnames,maximumrequireddelay,minimumrequireddelay,maximumclockskewbetweenleafnodes,andtreedepth,amongotherparameters.FormoreinformationonallavailableoptionsrefertotheSOCEmanual.Importtheclocktreespecificationfilebyselecting"ClockSpecifyClockTree"fromthemenu.Synthesizetheclocktreebychoosingthe"SynthesizeClockTree"optionfromtheClock



menu.Thefollowingwindowshows.

ClickOKtostartckSynthesis(theutilityequivalenttoCTGen).Ittakessometimetocompleteclocktreesynthesis.Thelogfileofthesynthesisrunisproducedinhtmlformat.Youcanviewthereportfilesusinganywebbrowser.Ifthereportmentionsanyviolations,thentheclocktreespecificationshavetobemodifiedandckSynthesisshouldbererun.

Nanoroute

AfterCTS,starttheglobalanddetailroutingusingNanoroute.Choose"Nanoroute"fromtheRoutemenu.Thefollowingwindowpopsup.

Choosethetimingdrivenoption.ThisperformsseveraliterationsoftheroutingwithfastRCextractionandtiminganalysistoimprovetimingslack.ClickonOKtostartNanoroute.Ittakessometimefortheroutingtocomplete.Thetoolperformsviolationchecks,DRC(DesignRuleChecking)andreportserrorsandwarningsaftertheprocessiscomplete.Thefollowingfiguredisplaystherouteddesign.



Youcanviewdesigninformationandnetstatisticsusingoptionsin"Tools"menu.Thereisanoptiontochooseindividualnetsandobtaintheirstatistics.

RCExtractionandTimingAnalysis

Toverifyifthechipmeetstimingornotandtostudytimingslacksofpathsinthedesign,weperformparasiticextractionandstatictiminganalysis.Todothis,weusethesimple2.5DRCextractorbuiltintoSOCE.Amoreaccurate3DRCextractor(Fire'n'Ice)canbeusedtoperformsignoffqualityextraction.Forourcurrentrun,westickwiththesimpleRCextractor.Toperformextraction,choose"TimingExtractRC".

SelecttheoptionsshownaboveandthenclickOKtoperformRCextraction.Dependingonthesizeofthedesign,thismaytakesometime.AfterRCextractioniscomplete,doadelaycalculation.Tocalculatedelay,choose"TimingCalculateDelay".Storethedelayvaluestoaes_cipher_top.sdf.ThisfilewillbeusedinStaticTimingAnalysis(STA).

Thenextstepinthedesignflowistiminganalysis.Beforeperformingtiminganalysis,settheoperatingconditions.Choose"TimingSpecifyAnalysisConditionSpecifyOperatingCondition".



Choose"timinglibrary:slow"underthemaxtaband"timinglibrary:fast"formintabandclickOK.Thestatictimingtool(CommonTimingEngine)performstiminganalysisundertheseoperatingconditions.Timinganalysiscanbeperformedbyexecutingfollowingcommandsattheencountershell.

encounter>buildTimingGraph

Reporttimingslacksandviolationsafterbuildingthetiminggraphbyusingthefollowingcommands

encounter>setCteReportencounter>reportTAsummaryoutfileaes_cipher_top_TD.tarptnworst50encounter>reportTAoutfileaes_cipher_top_TD.slacknworst50

Viewthetimingandviolationreportstoobservetimingslacksforvariouspathsandseeifthedesignmettiming.Youcanviewvarious"worstcase"pathsbystartingtheslackbrowser.Choose"TimingReportTimingSlacks"firstandcreatea.slkfile.Then,youcangoto"TimingTimingDebugSlackBrowser"toinitializetheslackbrowser.Apopupwindowopensaskingfortheslackreportgeneratedinthepreviousstep.Afterthisfileisimported,youcanviewthevarioustimingpathsinthedesignbyhighlightingthepathsintheslackbrowser.

**************ENDOFTUTORIAL*******************

2.LAB

Inthispart,youwillrunSOCEonthesynthesizedAEScoretomeetvarioustimingandareaobjectiveswithanenhancedflow.Theflowandtheassociatedcommand(.tcl)filesareexplainedbelow.



Note:Individualstepsareindicatedinorangeboxes.Yellowboxesrepresentdetailedproceduresofmainstepsoutlinedbytheredboxes.

1.Step1oftheflowperformsinitializationofenvironmentvariables,setspathstodirectories.Oneimportantfilethatisusedforinitializationisaes_cipher_top.conf.Thisfileispresentinthecmd/encounterdirectoryandisusedtosetpathstolibraries,timingcostraintfiles,rowutilizationandotherparameters.Openthefileinatexteditortoviewallavailableitems.Youcanchangethisfiletosuityourexperiments.(file:cmd/encounter/01_ini.tcl)

2.Step2oftheflowsetstiminganalysisparameters(referto"setCteReport"intextcommandmanual)(file:cmd/encounter/02_timing.tcl)

3.Step3performsblockplacementandfloorplanning.Youcanchoosetoperformthesestepsmanuallytohaveabetterviewofthefloorplanandblockplacementsolutions.(file:cmd/encounter/03_floorplan.tcl)

4.Step4performspowerplanning.Itaddspowerringsandpowerstripesinthedesign.Again,youcanchoosetodothesemanually.(file:cmd/encounter/04_power.tcl)

5.Step5(redbox)doesplacementwithamoebaPlaceinthetimingdriven,congestionoptimizationmode.Thisisfollowedbytrialrouteandparasiticextraction.Thisisdoneinordertoevaluatethequalityofplacement.Timinganalysisisperformedwiththeextractedparasitics.(file:cmd/encounter/05_place.tcl)

6.Step6performsIPO(Inplaceoptimization)oftheplaceddesigninordertoimprovedesigntiming.Inthisstep,theIPOmodeissetupandsetuptimeviolationsarefixed(withoperationssuchasbuffering,resizingandcloning).Toevaluatetheimprovementintiming,trialroute,RCextraction,andthentiminganalysisareperformed.(filecmd/encounter/06_ipo1.tcl)

7.Step7performsclocktreesynthesis.ClocktreeanalysisisperformedafterCTStoevaluateitsquality.Sincetheclocktreenowexists,thedesignistrialroutedwiththeclocktreeandtiminganalyzed.(file:cmd/encounter/07_cts.tcl)

8.Step8fixesofsetupandholdtimeviolationsafterclocktreesynthesis.(file:cmd/encounter/08_ipo2.tcl)



9.Step9performsroutingofpowerandgroundwiresincellsandconnectsthemtopowerstripes.(file:cmd/encounter/09_routepower.tcl)

10.Toensurethecontinuousconnectionofpowerandgroundlinesthatrunonthetopsandbottomsofstandardcellrows,fillercellsareintroducedincellgaps.Thisisperformedinstep10.(file:cmd/encounter/10_addfiller.tcl)

11.InStep11,youspecifyvariousroutingattributesandnanoRouteoptionstoperformwirerouting.Foradetaileddescriptionofoptionsandattributes,refertotheSOCEmanualandtextcommandreference.(file:cmd/encounter/11_route.tcl)

12.Wiringconnectivityandcellgeometriesareverifiedinstep12.Violationsarereported.(file:cmd/encounter/12_verify.tcl)

13.Instep13,afinaltiminganalysisisperformedafterdetailedRCextraction.Aftertiminganalysis,theDEFfileandmodifiednetlistofthedesignareexportedtooutputdirectories.(file:cmd/encounter/13_write.tcl)

RunningSOCEfromthecommandline(encountershell)

Eachoftheabovestepscanberunsequentiallybysourcingthetclfilescorrespondingtoeachstep

encounter>sourcecmd/encounter/01_ini.tcl

Thereisafilecalled"do_encounter.tcl"thatsourcesallthesefilesandrunsthedesignthroughtheflowmentionedabove.YoumightwanttoopentheGUIsessioninparalleltoobservechangesinthedesignasitprogressesthroughvariousstages.Youcancontroltheflowbymodifyingoptionsinthetclfiles.Formoreinformationonallavailableoptionsrefertothetextcommandreferencemanual.

Experiments

Foreachquestion,pleaseexplainnotonlyWHAThappened,butWHYyouthinkithappened.

Forexample,"Changingconstraintxcausedytohappen"onlyexplainswhat,butnotwhy."Changingconstraintxmeantthatthesynthesizerhadtodoa,b,andcbecauseifitdidnot,thegoaldwouldnothavebeenmet.Aswecansee,doinga,b,andctothedesigncausedustoobserveyintheresults."ismorealongthelinesofwhatwe'relookingfor.

Youwillgetmorepointsforalogicalandwellthoughtoutobservation,evenifit'sincorrect,thanyouwillfornotprovidingoneatall.

Q1.Inthisexercise,youwillstudytheeffectofplacement(andplacementknobs)onthetimingandcongestionofthedesign.Runtheplaceandrouteflow(specifiedabove)ontheaescorewithrowutilizationsetto50%andthefollowingoptionsforamoebaPlace

1.amoebaPlacetimingdrivenlowEffort2.amoebaPlacetimingdrivenhighEffort3.amoebaPlacetimingdrivenhighEffortdoCongOpt>theflagdoCongOptperformscongestionoptimization4.amoebaPlacelowEffort

Foreachoftheseruns,dumpcongestioninformationusingthe

dumpCongestAreaallcongestionMap.txt

commandAFTERROUTING.Foreachoftheaboveruns,reporttiming,congestionandruntime(foramoebaPlace+NanoRouteonly)inatable.Youcangetruntimesfromtheencounter.logfileproducedaftereachrun.Deliverable:(a)theencounter.logfileofeachofthefourruns(b)Areportofyourobservationsexplainingthereasonforthedegradation/improvementintimingdueuseofvariousknobsinplacement.

Q2.Inthisexercise,youwillstudytheeffectofrouting(andvariousknobs)usingNanoRouteontiming,congestionandsignalintegrityofthedesign.Runtheplaceandrouteflow(specifiedabove)withthefollowingoptionsforNanoRoute.YoucanspecifyattributesforNanoRouteusingeithertheGUIorthecommandline

setNanoRouteMode

Formoreinformation,refertotheSOCEtextcommandreferencemanual.

1.FixantennaON+TimingDrivenON+TimingOptimizationOFF2.FixantennaON+TimingDrivenOFF+TimingOptimizationON+SIDrivenON(LowEffort)3.FixantennaON+TimingDrivenOFF+TimingOptimizationON+SIDrivenON(HighEffort)4.FixantennaOFF+TimingDrivenOFF+TimingOptimizationOFF+SIDrivenON(HighEffort)5.FixantennaOFF+TimingDrivenOFF+TimingOptimizationOFF+SIDrivenOFF(justplainglobalanddetailedroute)

Performatiminganalysisafterplaceandrouteineachoftheseruns.Verifyconnectivityandgeometryforeachoftheseusingthe"Verify"menuofSOCE.Obtaindesignstatisticsfrom"Tools"menuofSOCE.Foreachoftheserunscollectthefollowinginformation.

Worsttimingslack,runtime(onlyforrouting),congestioninformation,#ofviolations,totalcellarea

Deliverable:(a)encounter.logfileofeachofthefiveruns(b)Areportofyourobservationsexplainingdegradation/improvementintiming,congestion,#violationsandtotalcellareaofthedesign.Pleasetrytoprovideobservationsinatabularformforimprovedreadability.

Q3.IfyouhavesolvedQ1andQ2already,thenyouhavesomeideaof"goodpractices"formeetingtimingofadesign.Thisquestionattemptstoletyouexplorevarioustooloptionstomeettiming.

Runplaceandroutewithrowutilizations=50%,60%,70%andperformtiminganalysis.Youshouldattempttomeettimingrequirementswitha3.6nsclock.Youareprovidedwiththetimingconstraintstouseintimingdrivenplaceandroute.Toeasecongestion,performplacementinthecongestionoptimizationmode.Youmayormaynotmeettiming,butyoushouldtrytominimizeveslackasmuchaspossible.

Iwasabletomeettimingwithasmall+veslackonlyforrowutilization=50%.Meetingtimingwith60%and70%rowutilizationisnontrivial.Duetoarelativelyhighutilizationratio,therewillbeincreasedparasiticsduetowiresbeingclosetogether.whichresultsintimingdegradation.Trytoexperimentwithdifferentfloorplans(blockplacementsolutions),performcongestionoptimizationanditerativelyimproveplacementandtheroutingsolutiontoimproveparasitics.

Deliverable:(a)Commandfiles(encounter.cmd),scripts(whichyoumighthaveused)andencounter.logfilesforthebestrunyouhadforeachvalueofrowutilization.

Place and Route With SoC Encounter12313

Documents