Place and Route - LTH

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Synthesis

Placement & Routing

Backend netlist Verification

Fabrication

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Floorplan

IO Placement

Cell Placement

IO Filler Placement Connect Power Clk tree synthesis

Core Filler Placement

Design Rule Check

Tech Libraries

Netlist, GDS

Signal Route

Netlist

Power Planning

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•  Floorplan: –  Placement area –  IOs –  RAM/ROM

D+7&-(:+@(5*%&O6+J&

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•  Power Planning -  Design a power ring -  Add horizantal and

vertical power stripes

D+7&-(:+@(5*%&O6+J&

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•  Place Cells: –  Place all the standard

cells into the rows

D+7&-(:+@(5*%&O6+J&

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Clock Tree Synthesis: –  Places clock buffers –  Timing constraints

–  Skew etc

D+7&-(:+@(5*%&O6+J&

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•  Connect Power Supply: –  Core Power –  Pad Power

•  Add FILLER cells •  core filler cells •  IO filler cells

D+7&-(:+@(5*%&O6+J&

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•  Route Clock tree: –  Finds an “optimal” way –  Reduces skew

•  Route signal nets –  Final step

D+7&-(:+@(5*%&O6+J&

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2*P+&0$L+@5&

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/*:E(+6+4L&2*":%38=+(&O36*"&

LEF: Library Exchange Format

–  Technology: Design rules, Capacitance, Resistance, Antenna factor, Vias ! header.lef

–  Cells & pads: Size, Class, Placement, Pin Information, Obstructions. ! Standard_cell.lef ! IO.lef

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MACRO IV CLASS CORE ; FOREIGN IV 0.000 0.000 ; ORIGIN 0.00 0.00 ; SIZE 3.00 BY 12.00 ; SYMMETRY x y ; SITE CORE ; PIN A DIRECTION INPUT ; ANTENNASIZE 1.4 ; PORT LAYER metal1 ; RECT 0.50 5.00 1.00

5.50 ; END END A

OBS LAYER metal1 ; RECT 1.90 6.50 2.60

7.20 ; RECT 0.40 4.90 1.00

5.60 ;

Physical cell size

Terminals with physical placement

A Q

gnd!

vdd! vdd!

gnd!

A Q

!S"5%@:=+("&

Layout Abstract LEF

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Design Description Files

Enc: Encounter Format –  Netlist, Layout

DEF: Design Exchange Format (not used in our flow. –  Netlist, Layout

Verilog –  Netlist, generated from synthesis tool

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Design Import

Will be provided

Needs to be specified

12

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RAM

IO Site

rows

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;))&Na2&

If rows are flipped and abut VDD and GND can be shared by 2 rows. Default setting!

;))&

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IO to core distance

Core utilization

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Flight lines will indicate location of the pins

Block: Circuitry that is pre-routed, e.g., RAM.

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vdd

stripes gnd

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Choose upper layers (say metal 3 or 4)

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•  Initial cell placement

•  Moves, swaps changes orientation of cells to minimize required wire length

•  Optimizes for wire length and net crossings •  A post CTS optimization may be carried out

to optimize the design

Place -> Standard Cells

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Clock Skew

•  Absolute Skew -Delay from input to leaf cell

•  Relative Skew -Delay difference between leaf cells

Danger! Too much clock skew may: 1)  Force you to reduce clock rate 2)  Cause malfunction at any clock

rate

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Distributed Buffers in H-tree

Small relative skew

Absolute skew of less importance

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•  create_clock –period value –name clk_name –add [get_ports clk]

•  Generate Clock tree specification createClockTreeSpec –output file_name.ctstch -routeClknet -buffer buffer_list

•  Specify CTS file and synthesize clock tree. specifyClockTree -clkfile file_name.ctstch clockDesign –specFile file_name.ctstch –clk clk_name deleteTrialRoute

CTS commands

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Synthesized Clock tree

Clock buffers are placed in the core row gaps

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Core filler cell

Core filler cells ensure the continuity of power/ground rails and N+/P+ wells in the row.

Filler cells will close any gap it is important to perform CTS before filler cell placement.

before after

Place -> Filler -> Add filler Place -> Filler -> Add IO filler

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•  ?+@=(4&=P*&3"&"5%+(46L&)*8*()*(5&+(&5E*&)*"34(&:+P86*U35L&

Route -> Nano Route

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Verification and Tapeout

Verification (in SoCEnc) –  Connectivity, Antenna ....

Export –  Verilog (netlist) –  sdf (timing) –  GDS II

Post-layout simulation

tapeout

Verify

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