Pipelining II Andreas Klappenecker CPSC321 Computer Architecture
Pipelining - Ideal Preconditions Instruction set design
ideally, instructions are of equal length few instruction formats memory operands only in load and stores aligned data: only one memory access per load
Sources of problems instructions with variable lengths (memory
needs to be accessed multiple times) unaligned data (multiple memory accesses to
obtain single data item)
Hazards Structural Hazards
hardware cannot support the combination of instructions in the same clock cycle
e.g. accessing the memory at the same time Control Hazards
need to make decision based on results of one instruction while other is still executing
e.g. branching Data Hazards
instruction depends on results of instruction still in pipeline
Control Hazards Solutions:
stalling: delay by one cycle to wait for result
prediction: predict the result delayed decision: rearrange and
perform operations first that do not harm
Stall on Branch Assume that all branch computations
are done in stage 2 Delay by one cycle to wait for the result
Problems Write back data to register file
may create data hazard Selection of the next PC
may create a control hazard Solutions:
have a separate data path for each instruction (not really, you got to be kidding!)
chop data path into small pieces keep everything that belongs together into one
piece introduce registers to separate the stages
Store Word Instruction fetch: as before decode & register file read: as before execute and address calculation: as
before forwarding of register contents to EX/MEM
pipelining register Memory access
send data and address to memory Last step: nothing happens
Summary Some instructions do not require the
complete datapath No information transfer from one
pipeline stage to another is possible, except through pipeline registers
Everything that happened in any previous stage will be overwritten
Correction for store required: Where is the information on the write register?
Pipeline Control Data is traveling along the pipeline
stages All data belonging to one instruction
must be kept within that stage Information transfer only through
pipeline registers Control information must travel with
the instruction