PIF/AMBA Bridge Cycle Models User Guideinfocenter.arm.com/help/topic/...AMBA_Pif_Amba_Bridge_User_DUI1062A_en.pdf · 1.1 PIF/AMBA Bridge Cycle Models Overview Tensilica processors

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PIF/AMBA Bridge Cycle ModelUser Guide

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Contents

Chapter 1.Using the Cycle Model in SoC Designer

PIF/AMBA Bridge Cycle Models Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1Outbound PIF-to-AXI Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3Inbound AXI-to-PIF Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5Outbound PIF-to-AHBlite Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7Inbound AHBlite-to-PIF Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

Component Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13Component Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15Debug Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20

Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20Available Profiling Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24

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Preface

A Cycle Model component is a library that is generated through Cycle Model Studio™. The Cycle Model then can be used within a virtual platform tool, for example, SoC Designer.

About This GuideThis guide provides all the information needed to configure and use this Cycle Model in SoC Designer.

Audience

This guide is intended for experienced hardware and software developers who create compo-nents for use with SoC Designer. You should be familiar with the following products and tech-nology:

• SoC Designer

• Hardware design verification

• Verilog or SystemVerilog programming language

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Conventions

This guide uses the following conventions:

Also note the following references:

• References to C code implicitly apply to C++ as well.

• File names ending in .cc, .cpp, or .cxx indicate a C++ source file.

Convention Description Example

courier Commands, functions, variables, routines, and code examples that are set apart from ordinary text.

sparseMem_t SparseMemCreate-New();

italic New or unusual words or phrases appearing for the first time.

Transactors provide the entry and exit points for data ...

bold Action that the user per-forms.

Click Close to close the dialog.

<text> Values that you fill in, or that the system automati-cally supplies.

<platform>/ represents the name of various platforms.

[ text ] Square brackets [ ] indicate optional text.

$CARBON_HOME/bin/modelstudio [ <filename> ]

[ text1 | text2 ] The vertical bar | indicates “OR,” meaning that you can supply text1 or text 2.

$CARBON_HOME/bin/modelstudio [<name>.symtab.db | <name>.ccfg ]

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Further reading

This section lists related publications.

The following publications provide information that relate directly to SoC Designer:

• SoC Designer Installation Guide

• SoC Designer User Guide

• SoC Designer Standard Component Library Reference Manual

• SoC Designer AHBv2 Protocol Bundle User Guide

The following publications provide reference information about ARM® products:

• AMBA Design Kit Technical Reference Manual

• AMBA Specification

• AMBA AHB-Lite Protocol Specification

• AMBA AHB Protocol Specification

• Architecture Reference Manual

See http://infocenter.arm.com/help/index.jsp for access to ARM documentation.

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http://infocenter.arm.com/help/index.jsp

Glossary

Table 1:

AMBA Advanced Microcontroller Bus Architecture. The ARM open standard on-chip bus specification that describes a strategy for the interconnec-tion and management of functional blocks that make up a System-on-Chip (SoC).

AHB Advanced High-performance Bus. A bus protocol with a fixed pipeline between address/control and data phases. It only supports a subset of the functionality provided by the AMBA AXI protocol.

APB Advanced Peripheral Bus. A simpler bus protocol than AXI and AHB. It is designed for use with ancillary or general-purpose peripherals such as timers, interrupt controllers, UARTs, and I/O ports.

AXI Advanced eXtensible Interface. A bus protocol that is targeted at high performance, high clock frequency system designs and includes a num-ber of features that make it very suitable for high speed sub-micron interconnect.

Cycle Model A software object created by the Cycle Model Studio from an RTL design. The Cycle Model contains a cycle- and register-accurate model of the hardware design.

Cycle Model Studio

Graphical tool for generating, validating, and executing hardware-accurate software models. It creates a Cycle Model, and it also takes a Cycle Model as input and generates a component that can be used in SoC Designer, Platform Architect, or Accellera SystemC for simula-tion.

CASI Cycle Accurate Simulation Interface, is based on the SystemC commu-nication library and manages the interconnection of components and communication between components.

CADI Cycle Accurate Debug Interface, enables reading and writing memory and register values and also provides the interface to external debug-gers.

CAPI Cycle Accurate Profiling Interface, enables collecting historical data from a component and displaying the results in various formats.

Component Building blocks used to create simulated systems. Components are connected together with unidirectional transaction-level or signal-level connections.

ESL Electronic System Level. A type of design and verification methodol-ogy that models the behavior of an entire system using a high-level lan-guage such as C or C++.

HDL Hardware Description Language. A language for formal description of electronic circuits, for example, Verilog.

RTL Register Transfer Level. A high-level hardware description language (HDL) for defining digital circuits.

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SoC Designer The full name is SoC Designer. A high-performance, cycle accurate simulation framework which is targeted at System-on-a-Chip hardware and software debug, as well as architectural exploration.

SystemC SystemC is a single, unified design and verification language that enables verification at the system level, independent of any detailed hardware and software implementation, as well as enabling co-verifi-cation with RTL design.

Transactor Transaction adaptors. You add transactors to your component to con-nect your component directly to transaction level interface ports for your particular platform.

Table 1:

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Chapter 1

Using the Cycle Model in SoC Designer

This chapter describes the functionality of the Cycle Model, and how to use it in SoC Designer. It contains the following sections:

• PIF/AMBA Bridge Cycle Models Overview

• Component Ports

• Component Parameters

• Debug Features

• Available Profiling Data

1.1 PIF/AMBA Bridge Cycle Models OverviewTensilica processors perform traditional main memory and system accesses on a Processor Interface (PIF) port. The PIF is a configurable, high-performance, multi-master interface defini-tion. The PIF/AMBA and AMBA/PIF Bridge Cycle Models can be used to connect a Tensilica processor to AHB-Lite and AXI buses. These bridges can be used to easily integrate a Tensilica processor into an existing AMBA-based SOC system.

Several bridge Cycle Models are available to match the processor’s configuration options, including:

• Data bus widths

• Endianness

• Cache size

• Two clocking modes are supported through the Strobe signal on the component:

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– The processor and bus clocks are synchronous and the same frequency.

– The processor and bus clocks are synchronous, but the processor clock frequency is an integer multiple faster than the bus frequency. Multiples up to a 4 to 1 clock ratio are allowed.

In general, the bridges provided are shown as grey boxes in the figure below.

Figure 1-1 PIF/AMBA Bridges in a Standard Configuration

Note: You must have the Tensilica tools installed, and your LD_LIBRARY_PATH must be set to include the common iss shared libraries which handle the SystemC PIF protocol. For example, the location:

.../linux/xtensa/xtensa-2.1.3/XtDevTools/install/tools/RB-2009.5-linux/XtensaTools/lib/iss

The bus bridges are configured with the same options as the processor and are not necessarily portable across different processor configurations. They must be connected directly to a com-patible Tensilica processor to function correctly. Refer to the Tensilica Processors Bus Bridges Guide and other Tensilica documentation for more information.

The different Cycle Models are described in the following sections.

• Outbound PIF-to-AXI Bridges on page 1-3

• Inbound AXI-to-PIF Bridges on page 1-5

• Outbound PIF-to-AHBlite Bridges on page 1-7

AXI or AHB-Lite Master Device or

Bus

Tensilica PIF 3.0Processor

Outbound PIF to AMBA bridge

Inbound AMBA to PIF bridge

AXI or AHB-Lite Slave Device or

Bus


1.1.1 Outbound PIF-to-AXI Bridges

The Outbound PIF-to-AXI bridge allows designers to integrate PIF3.0 processors into AMBA 3.0 AXI systems. The PIF-to-AXI bridge handles all the logic necessary to convert requests and responses between the PIF and AXI protocols, allowing the designer to treat the Tensilica pro-cessor as any other AXI component.

The PIF-to-AXI Bridges are provided in a variety of versions that support different data bus widths and other options. The letters in each component name describe the options that must match the processor to which it will be connected:

• 32, 64, or 128 is the data bus width

• le or be stand for Little Endian or Big Endian

• nwr or wr stand for No Write Response or Write Response

• ndc stands for No Data Cache

• dc16, dc32, or dc64 stand for Data Cache with 16/32/64 Byte cache line

Table 1-1 PIF-to-AXI Outbound Bridge Components

Component Description

CM_Pif_Axi_32le_nwr 32-bit data bus, little-endian, no write response



CM_Pif_Axi_32be_nwr 32-bit data bus, big-endian, no write response



CM_Pif_Axi_32le_wr_ndc 32-bit data bus, little-endian, write response, no data cache



CM_Pif_Axi_32be_wr_ndc 32-bit data bus, big-endian, write response, no data cache



CM_Pif_Axi_32le_wr_dc16 32-bit data bus, little-endian, write response, 16-byte cache line



CM_Pif_Axi_32be_wr_dc16 32-bit data bus, big-endian, write response, 16-byte cache line





Figure 1-2 shows a simple configuration using the Outbound PIF-to-AXI Bridge.

Figure 1-2 Simple Outbound PIF-to-AXI Bridge Configuration












Table 1-1 PIF-to-AXI Outbound Bridge Components


AXI Master interface

PIF Slaveinterface

AXI Slaveinterface

AXIPIF

PIF Masterinterface

PIF-to-AXI bridge

Tensilica processor

AXI Device


1.1.2 Inbound AXI-to-PIF Bridges

The Inbound AXI-to-PIF bridge allows designers to integrate PIF3.0 processors into AMBA 3.0 AXI systems. The AXI-to-PIF bridge handles all the logic necessary to convert requests and responses between the AXI and PIF protocols, allowing the designer to treat the Tensilica pro-cessor as any other AXI component.

The AXI-to-PIF Bridges are provided in a variety of versions that support different data bus widths and other options. The letters in each component name describe the options that must match the processor to which it will be connected:




Table 1-2 AXI-to-PIF Inbound Bridge Components


CM_Axi_Pif_32le_nwr 32-bit data bus, little-endian, no write response



CM_Axi_Pif_32be_nwr 32-bit data bus, big-endian, no write response



CM_Axi_Pif_32le_wr 32-bit data bus, little-endian, write response



CM_Axi_Pif_32be_wr 32-bit data bus, big-endian, write response




Figure 1-3 shows a simple configuration using the Inbound AXI-to-PIF Bridge.

Figure 1-3 Simple Inbound AXI-to-PIF Bridge Configuration

PIF Master interface

AXI Slaveinterface

Tensilica processor

PIF Slaveinterface

PIFAXIAXI Device

AXI Masterinterface

AXI-to-PIF bridge


1.1.3 Outbound PIF-to-AHBlite Bridges

The Outbound PIF-to-AHBlite bridge allows designers to integrate PIF3.0 processors into AMBA 2.0 AHB-Lite systems. The PIF-to-AHBlite bridge handles all the logic necessary to convert requests and responses between the PIF and AHB-Lite protocols, allowing the designer to treat the Tensilica processor as any other AHB-Lite component.

The PIF-to-AHBlite Bridges are provided in a variety of versions that support different data bus widths and other options. The letters in each component name describe the options that must match the processor to which it will be connected:


• the second number reflects the maximum transfer size on the bus (32, 64, or 128)



• b2lk stands for burst 2 lock

Table 1-3 PIF-to-AHBlite Outbound Bridge Components


CM_Pif_Ahblite_32le_32_wr 32-bit data bus, little-endian, 32-bit transfer size, write response






CM_Pif_Ahblite_32le_32_wr_b2lk 32-bit data bus, little-endian, 32-bit transfer size, write response, with burst 2 lock







CM_Pif_Ahblite_32le_32_nwr 32-bit data bus, little-endian, 32-bit transfer size, no write response






CM_Pif_Ahblite_32le_32_nwr_b2lk 32-bit data bus, little-endian, 32-bit transfer size, no write response, with burst 2 lock






CM_Pif_Ahblite_32be_32_wr 32-bit data bus, big-endian, 32-bit transfer size, write response






CM_Pif_Ahblite_32be_32_wr_b2lk 32-bit data bus, big-endian, 32-bit transfer size, write response, with burst 2 lock









CM_Pif_Ahblite_32be_32_nwr 32-bit data bus, big-endian, 32-bit transfer size, no write response






CM_Pif_Ahblite_32be_32_nwr_b2lk 32-bit data bus, big-endian, 32-bit transfer size, no write response, with burst 2 lock





CM_Pif_Ahblite_128le_32_nwr_b2lk 128-bit data bus, big-endian, 32-bit transfer size, no write response, with burst 2 lock




Figure 1-4 shows a simple configuration using the Outbound PIF-to-AHBlite Bridge.

Figure 1-4 Simple Outbound PIF-to-AHBlite Bridge Configuration

1.1.3.1 Connecting with Full AHB ComponentsIf you are connecting with a full AHBv2 component, you must use a AHBv2-Lite to AHBv2 Bridge Cycle Model or AHBv2 to AHBv2-Lite Bridge Cycle Model.

Figure 1-5 shows a simple configuration using both a PIF-AHBlite bridge and an AHB-Lite to AHB Bridge.

Figure 1-5 Connecting AHB-Lite Component with an AHB Component

AHB-Lite Master interface

PIF Slaveinterface

AHB-Lite Slaveinterface

AHB-Lite

PIF

PIF Masterinterface

PIF-to-AHBlite bridge

Tensilica processor

AHB-Lite Device

AHB Slave or system

AHB-Lite to AHB bridge

AHBAHBLite

PIF-to-AHBlite bridge

PIFTensilica processor


1.1.4 Inbound AHBlite-to-PIF Bridges

The inbound AHBlite-toPIF bridge allows designers to integrate PIF3.0 processors into AMBA 2.0 AHB-Lite systems. The AHBlite-toPIFlite bridge handles all the logic necessary to convert requests and responses between the AHB-Lite and PIF protocols, allowing the designer to treat the Tensilica processor as any other AHB-Lite component.

The AHBlite-toPIF Bridges are provided in a variety of versions that support different data bus widths and other options. The letters in each component name describe the options that must match the processor to which it will be connected:






CM_Ahblite_Pif_32le_wr 32-bit data bus, little-endian, write response



CM_Ahblite_Pif_32be_wr 32-bit data bus, big-endian, write response



CM_Ahblite_Pif_32le_nwr 32-bit data bus, little-endian, no write response



CM_Ahblite_Pif_32be_nwr 32-bit data bus, big-endian, no write response




Figure 1-4 shows a simple configuration using the Inbound AHBlite-to-PIF Bridge.

Figure 1-6 Simple Outbound PIF-to-AHBlite Bridge Configuration

1.1.4.1 Connecting with Full AHB ComponentsIf you are connecting with a full AHBv2 component, you will need to use a AHBv2-Lite to AHBv2 Bridge Cycle Model or AHBv2 to AHBv2-Lite Bridge Cycle Model.

Figure 1-5 shows a simple configuration using both a PIF-AHBlite bridge and an AHB to AHB-Lite Bridge.

Figure 1-7 Connecting AHB-Lite Component with an AHB Component

AHB-Lite Slave interface

PIF Masterinterface

AHB-Lite Masterinterface

AHB-Lite

PIF

PIF Slaveinterface

AHBLite-to-PIF bridge

Tensilica processor

AHB-Lite Device

AHB Master or system

AHB to AHB-Lite bridge

AHBAHBLite

AHBlite-to-PIF bridge

PIFTensilica processor


1.2 Component PortsThis section describes the ports for each type of component.

Table 1-5 describes the ESL ports that are exposed in SoC Designer for the PIF-to-AXI Bridge.

Table 1-6 describes the ESL ports that are exposed in SoC Designer for the AXI-to-PIF Bridge.

Table 1-5 PIF-to-AXI Bridge Component Ports

ESL Port Description Direction Type

PIF_Slave_request Xtensa XTSC request interface. Input SystemC Transaction slave

Reset Reset port for resetting the Cycle Model. Input Signal slave

Strobe Indicates the phase of the AXI clock. Refer to the Tensilica Processors Bus Bridges Guide for details. Leave this signal unconnected if you want a 1:1 ratio.The MXSIGDRIVER component, described in the SoC Designer Standard Component Library Reference Manual, can be used to generate the required signal.

Input Signal slave

clk-in Input clock. The component is clocked at the fre-quency of the clock connected to the clk-in port. If the clk-in port is not connected, clocking is taken from SoC Designer System Properties.

Input Clock slave

AXIv2_Master AXIv2 transaction master port. Output Transaction master

PIF_Slave_respond Xtensa XTSC respond interface. Output SystemC Transaction master

Table 1-6 AXI-to-PIF Bridge Component Ports


AXIv2_Slave AXIv2 transaction slave port. Input Transaction slave

PIF_Master_respond Xtensa XTSC respond interface. Input SystemC Transaction slave



Input Signal slave


Table 1-7 describes the ESL ports that are exposed in SoC Designer for the PIF-to-AHBlite Bridge.

Note: Some ESL component port values can be set using a component parameter. This includes the ‘Strobe’ port. In this case, the ‘Strobe default’ parameter value will be used whenever the ESL port is not connected. If the port is connected, the connection value takes precedence over the parameter value.

clk-in Input clock. The component is clocked at the frequency of the clock connected to the clk-in port. If the clk-in port is not connected, clocking is taken from SoC Designer System Properties.

Input Clock slave

PIF_Master_request Xtensa XTSC request interface. Output SystemC Transaction master

Table 1-7 PIF-to-AHBlite Bridge Component Ports


PIF_Slave_request Xtensa XTSC request interface. Input SystemC Transaction slave



Input Signal slave

clk-in Input clock. The component is clocked at the fre-quency of the clock connected to the clk-in port. If the clk-in port is not connected, clocking is taken from SoC Designer System Properties.

Input Clock slave

AHBv2_Lite_Master AHB-Lite transaction master port. Output Transaction master

PIF_Slave_respond Xtensa XTSC respond interface. Output SystemC Transaction master

Table 1-6 AXI-to-PIF Bridge Component Ports (continued)



1.3 Component ParametersYou can change the settings of all the component parameters in SoC Designer Canvas, and of some of the parameters in SoC Designer Simulator.

The parameters for each type of component are described in separate tables. Parameters that may be modified at runtime are identified with Yes in the Runtime column, otherwise the param-eter values are fixed and must be set before the start of simulation.

Table 1-8 describes the component parameters that are available for the PIF-to-AXI Bridge.

Table 1-8 PIF-to-AXI Component Parameters

Name DescriptionAllowed Values

Default Value

Runtime

Align Waveforms When set to true, waveforms dumped from Cycle Model components are aligned with the SoC Designer simula-tion time. The reset sequence, how-ever, is not included in the dumped data.When set to false, the reset sequence is dumped to waveform data, however, the component time is not aligned with the SoC Designer time.

true, false true No

AXIv2_Master Enable Debug Messages

When set to true, writes AXI debug messages to the SoC Designer output window.

true, false false Yes

Carbon DB Path Sets the directory path to the database file.

Not Used empty No

Dump Waveforms Whether SoC Designer dumps wave-forms for this component.


Enable Debug Messages

Enable or disable the capture of debug messages for the component.


PIF_Slave Big Endian Whether PIF data is treated as big endian for this port. By default, data is sent as little endian.

true, false false No

PIF_Slave Enable Debug Messages

When set to true, writes PIF debug messages to the SoC Designer output window.


PIF_Slave Generate Write Responses

Whether to generate Responses for Write Requests (last request only). Do not change the value of this parameter.


PIF_Slave Merge RCW Responses

Whether to merge RCW Responses into a single Response. Do not change the value of this parameter.


Strobe default This is the value used when the Strobe port is not connected. It should not be changed from the default of 1.

0, 1 1 Yes


Table 1-9 describes the component parameters that are available for the AXI-to-PIF Bridge.

Waveform File 1 Name of the waveform file. string carbon_CM_Pif_Axi_<full_name>.vcd

No

Waveform Format The format of the waveform dump file. VCD, FSDB VCD No

Waveform Timescale Sets the timescale to be used in the waveform.

Many values in drop-down

1 ns No

1. When enabled, SoC Designer writes accumulated waveforms to the waveform file in the following situa-tions: when the waveform buffer fills, when validation is paused and when validation finishes, and at the end of each validation run.

Table 1-9 AXI-to-PIF Component Parameters


Default Value

Runtime

Align Waveforms When set to true, waveforms dumped from Cycle Model components are aligned with the SoC Designer simula-tion time. The reset sequence, how-ever, is not included in the dumped data.

When set to false, the reset sequence is dumped to waveform data, however, the component time is not aligned with the SoC Designer time.

true, false true No

AXIv2_Slave

axi_size[0-5] 1These parameters are obsolete and

should be left at their default values.20x0 - 0xFFFFFFFF

size 0 default is 0x100000000, size 1-5 default is 0x0

No

AXIv2_Slave axi_start[0-5]

0x0 - 0xFFFFFFFF

0x00000000 No

AXIv2_Slave Enable Debug Messages

When set to true, writes AXI debug messages to the SoC Designer output window.



Not Used empty No






PIF_Master Big Endian

Whether PIF data is treated as big endian for this port. By default, data is sent as little endian.


Table 1-8 PIF-to-AXI Component Parameters (continued)


Default Value

Runtime


PIF_Master Enable Debug Messages




0, 1 1 Yes

Waveform File 3 Name of the waveform file. string carbon_CM_Axi_Pif_<full_name>.vcd

No



1 ns No

1. The square brackets specify that a range of numbers that are available. For example, the parameter name for the start addresses “AXIv2_Slave axi_start[0-5]” will be expanded to 6 parameter name combinations that range from “AXIv2_Slave axi_start0” to “AXIv2_Slave axi_start5”. The size of a memory region depends on the “start” and “size” parameters. The end address is calculated as Start + Size -1. The size of the mem-ory region must not exceed the value of 0x100000000. If the sum of Start+Size is greater than 0x100000000, the size of the memory region is reduced to the difference: 0x100000000-Start.

2. ARM recommends using the Memory Map Editor (MME) in SoC Designer, which provides centralized viewing and management of the memory regions available to the components in a system. For information about migrating existing systems to use the MME, refer to Chapter 9 of the SoC Designer User Guide.


Table 1-9 AXI-to-PIF Component Parameters (continued)


Default Value

Runtime


Table 1-10 describes the component parameters that are available for the PIF-to-AHBlite Bridge.

Table 1-10 PIF-to-AHBlite Component Parameters


Default Value

Runtime

AHBv2_Lite_Master Align Data

Whether halfword and byte transac-tions will align data to the transaction size for the AHBv2-Lite port. By default, data is not aligned.


AHBv2_Lite_Master Big Endian

Whether AHB data is treated as big endian for this port. By default, data is sent as little endian.


AHBv2_Lite_Master Enable Debug Mes-sages

When set to true, writes AHB debug messages to the SoC Designer output window.


Align Waveforms When set to true, waveforms dumped from Cycle Model components are aligned with the SoC Designer simula-tion time. The reset sequence, how-ever, is not included in the dumped data.

When set to false, the reset sequence is dumped to waveform data, however, the component time is not aligned with the SoC Designer time.

true, false true No


Not Used empty No






HPROT Value The static value driven on the HPROT signal by the AHB-lite master. All accesses will use this value. Refer to the AHB specification for details.

0 - 15 3 No

PIF_Slave Big Endian Whether PIF data is treated as big endian for this port. By default, data is sent as little endian.


PIF_Slave Enable Debug Messages



PIF_Slave Generate Write Responses

Whether to generate Responses for Write Requests (last request only). This parameter must be set to ‘true’ for all Cycle Models that have _nwr in their names.



PIF_Slave Merge RCW Responses

Whether to merge RCW Responses into a single Response. This parameter must be set to ‘true’.



0, 1 1 Yes

Waveform File 1 Name of the waveform file. string carbon_CM_Pif_Ahblite_<full_name>.vcd

No



1 ns No


Table 1-10 PIF-to-AHBlite Component Parameters (continued)


Default Value

Runtime


1.4 Debug FeaturesThe PIF/AMBA Bridges have a debug interface (CADI) that allows you to track the values of the applicable PIF, AHB-Lite, and AXI signals. A view can be accessed in SoC Designer by right-clicking on the component and choosing the appropriate menu entry.

Transactions can be visualized using the transaction monitors attached to connections. By right clicking on any of the connections in SoC Designer, a transaction monitor probe can be attached. This functionality is available for the AMBA signals only.

1.4.1 Register Information

The available signals are listed in the following sections:

• PIF Slave Port Signal Registers

• PIF Master Port Signal Registers

• AXI Master Port and Slave Port Signal Registers

• AHB-Lite Master Port Signal Registers

1.4.1.1 PIF Slave Port Signal RegistersTable 1-11 shows the PIF slave port signals. See the Tensilica Processors Bus Bridges Guide for more information about these signals.

Table 1-11 PIF Slave Port Signal Registers

Name Description Type

PIReqAdrs Transaction-request address. Address is aligned to the transfer size.

read-only

PIReqCntl Encodes the bus-transaction request type and block size for block requests.

read-only

PIReqData Data lines used by requests that require data during the request phase. These requests include single data write, block write, and read-conditional-write requests. The data bus is configu-rable to 32, 64, or 128-bits.

read-only

PIReqDataBE Indicates valid bytes lanes during requests that use PIReqData, or byte lanes expected to be valid during responses that use PORespData.

read-only

PIReqId Request ID. Responses are expected to be tagged with the same ID as the request on PORespId. IDs support multiple out-standing requests. No restrictions or orderings are placed on the usage or uniqueness of IDs.

read-only

PIReqPriority Request priority allows PIF slaves and interconnection net-works to make priority judgments when arbitrating bus-trans-action requests. 0x0 is low-priority, and 0x3 is high-priority.

read-only

PIReqValid Indicates that there is a valid bus-transaction input request. All other signals prefixed with PIReq are qualified by PIReqValid.

read-only


1.4.1.2 PIF Master Port Signal RegistersTable 1-12 shows the PIF master port signals. See the Tensilica Processors Bus Bridges Guide for more information about these signals.

PIRespRdy Indicates that the master is ready to accept responses. A response transfer completes when PORespValid and PIRe-spRdy are asserted in the same cycle.

read-only

POReqRdy Indicates that the slave is ready to accept requests. A request transfer completes if POReqRdy and PIReqValid are both asserted during the same cycle.

read-only

PORespCntl Encodes the response type and any error status on requests. read-only

PORespData Response data. The data bus is configurable to 32, 64, or 128-bits and is equal in width to the request data bus.

read-only

PORespId Response ID. Matches the ID of the corresponding request. read-only

PORespPriority Response priority. Matches the priority of the corresponding request.

read-only

PORespValid Indicates that there is a valid response. All other signals pre-fixed with POResp are qualified by PORespValid.

read-only

Table 1-12 PIF Master Port Signal Registers


POReqAdrs Transaction-request address. Address is aligned to the transfer size.

read-only

POReqCntl Encodes the bus-transaction request type and block size for block requests.

read-only

POReqData Data lines used by requests that require data during the request phase. These requests include single data write, block write, and read-conditional-write requests. The data bus is configurable to 32, 64, or 128-bits.

read-only

POReqDataBE Indicates valid bytes lanes during requests that use POReqData, or byte lanes expected to be valid during responses that use PIRe-spData.

read-only

POReqId Request ID. Responses are expected to be tagged with the same ID as the request on PIRespId. IDs support multiple outstanding requests. No restrictions or orderings are placed on the usage or uniqueness of IDs.

read-only

POReqPriority Request priority allows PIF slaves and interconnection networks to make priority judgments when arbitrating bus-transaction requests. 0x0 is low-priority, and 0x3 is high-priority.

read-only

POReqValid Indicates that there is a valid bus-transaction input request. All other signals prefixed with POReq are qualified by POReqValid.

read-only

Table 1-11 PIF Slave Port Signal Registers (continued)



1.4.1.3 AXI Master Port and Slave Port Signal RegistersTable 1-13 shows the AXI master port and slave port signals. See the ARM AMBA AXI Protocol Specification for more information about these signals.

PORespRdy Indicates that the master is ready to accept responses. A response transfer completes when PIRespValid and PORespRdy are asserted in the same cycle.

read-only

PIReqRdy Indicates that the slave is ready to accept requests. A request transfer completes if PIReqRdy and POReqValid are both asserted during the same cycle.

read-only

PIRespCntl Encodes the response type and any error status on requests. read-only

PIRespData Response data. The data bus is configurable to 32, 64, or 128-bits and is equal in width to the request data bus.

read-only

PIRespId Response ID. Matches the ID of the corresponding request. read-only

PIRespPriority Response priority. Matches the priority of the corresponding request.

read-only

PIRespValid Indicates that there is a valid response. All other signals prefixed with PIResp are qualified by PIRespValid.

read-only

Table 1-13 AXI Master Port and Slave Port Signal Registers


ARID The read address ID. read-only

ARADDR The read address. read-only

ARVALID Indicates whether the read address is available. read-only

ARREADY Indicates whether the slave is ready to accept the read address. read-only

ARLEN The burst length. read-only

ARSIZE The burst size. read-only

ARBURST The burst type. read-only

ARLOCK The lock type. read-only

ARCACHE The cache type. read-only

ARPROT The protection type. read-only

AWID The write address ID. read-only

AWADDR The write address. read-only

AWVALID Indicates whether the write address is available. read-only

AWREADY Indicates whether the slave is ready to accept the write address. read-only

AWLEN The burst length. read-only

AWSIZE The burst size. read-only

AWBURST The burst type. read-only

Table 1-12 PIF Master Port Signal Registers (continued)



1.4.1.4 AHB-Lite Master Port Signal RegistersTable 1-14 shows the AHB-Lite master port signals. See the ARM AMBA AHB Protocol Specifi-cation for more information about these signals.

AWLOCK The lock type. read-only

AWCACHE The cache type. read-only

AWPROT The protection type. read-only

WID The write ID tag. read-only

WDATA The write data. read-only

WSTRB The write strobes. read-only

WLAST The last transfer in a write burst. read-only

WVALID Indicates whether the write data and strobes are available. read-only

WREADY Indicates whether the slave is ready to accept the write data. read-only

RID The read ID tag. read-only

RDATA The read data. read-only

RLAST The last transfer in a read burst. read-only

RVALID Indicates whether the read data is available. read-only

RREADY Indicates whether the master is ready to accept the read data and response information.

read-only

RRESP The read response. read-only

BID The response ID. read-only

BRESP The write response. read-only

BVALID Indicates whether the write response is available. read-only

BREADY Indicates whether the master is ready to accept the response information.

read-only

Table 1-14 AHB-Lite Master Port Signal Registers


HADDR The 32-bit system address bus. read-only

HBURST Indicates if the transfer forms part of a burst. Four, eight, and sixteen beat bursts are supported.

read-only

HLOCK When HIGH, this signal indicates that the master requires locked access to the bus and no other master must be granted the bus until this signal is LOW.

read-only

HMASTLOCK Indicates that the current master is performing a locked sequence of transfers.

read-only

Table 1-13 AXI Master Port and Slave Port Signal Registers (continued)



1.5 Available Profiling DataThis Cycle Model does not provide profiling streams, and hence, does not provide profiling information. Transaction related information can be retrieved from the respective bus compo-nents.

HPROT The protection control signals provide additional information about a bus access, and are primarily intended for use by any module that wishes to implement some level of protection.

read-only

HRDATA The read data bus is used to transfer data from bus slaves to the bus master during read operations.

read-only

HREADY When HIGH, the HREADY signal indicates that a transfer has finished on the bus. This signal may be driven LOW to extend a transfer.

read-only

HRESP The transfer response provides additional information on the status of a transfer. Four responses are provided, OKAY, ERROR, RETRY, and SPLIT.

read-only

HSIZE Indicates the size of the transfer, which is typically byte (8-bit), halfword (16-bit), or word (32-bit).

read-only

HTRANS Indicates the type of the current transfer, which can be NON-SEQUENTIAL, SEQUENTIAL, IDLE, or BUSY.

read-only

HWDATA The write data bus is used to transfer data from the master to the bus slaves during write operations.

read-only

HWRITE When HIGH, this signal indicates a write transfer. When LOW, it indicates a read transfer.

read-only

Table 1-14 AHB-Lite Master Port Signal Registers (continued)



PIF/AMBA Bridge Cycle Models User Guideinfocenter.arm.com/help/topic/...AMBA_Pif_Amba_Bridge_User_DUI1062A_en.pdf · 1.1 PIF/AMBA Bridge Cycle Models Overview Tensilica processors

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