Pico-Sec Simulation Worksho p University of Chicago 1 2/12/06 Simulating Front-end Simulating Front-end Electronics and Integration Electronics and Integration with End-to-end Simulation with End-to-end Simulation Fukun Tang Fukun Tang Enrico Fermi Institute Enrico Fermi Institute University of Chicago University of Chicago With Karen Byrum and Gary Drake (ANL) Henry Frisch, Mary Heintz and Harold Sanders (UC)
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Pico-Sec Simulation Workshop University of Chicago 12/12/06 Simulating Front-end Electronics and Integration with End-to-end Simulation Fukun Tang Enrico.
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Pico-Sec Simulation Workshop University of Chicago 12/12/06
Simulating Front-end Simulating Front-end Electronics and Integration Electronics and Integration
with End-to-end Simulationwith End-to-end Simulation
Fukun TangFukun Tang
Enrico Fermi Institute Enrico Fermi Institute University of Chicago University of Chicago
With Karen Byrum and Gary Drake (ANL) Henry Frisch, Mary Heintz and Harold Sanders (UC)
Pico-Sec Simulation Workshop University of Chicago 12/12/06
Harold’s TOF Harold’s TOF SystemSystem
dumdum
Time Stretcher TDC
psFront-end
Start
Stop500pS
Tw
MCP_PMT Output Signal
Reference Clock
“fine” time interval
IBM SiGe BiCMOS 8HP IBM SiGe BiCMOS 8HP ProcessProcess
ffTT (high breakdown): 57GHz, BVceo=3.55V, BVcbo=12V (high breakdown): 57GHz, BVceo=3.55V, BVcbo=12V High-Q Inductors and Metal-Isolator-Metal CapacitorsHigh-Q Inductors and Metal-Isolator-Metal Capacitors 4 Types of Low-tolerance Resistors with Low and High Sheet 4 Types of Low-tolerance Resistors with Low and High Sheet
ResistivityResistivity n+ Diffusion, Tantalum Nitride, p+ Polisilicon and p- Polisiliconn+ Diffusion, Tantalum Nitride, p+ Polisilicon and p- Polisilicon
Electrically Writable e-FuseElectrically Writable e-Fuse CMOS Transistors (VDD=1.2V or 2.5/3.3V)CMOS Transistors (VDD=1.2V or 2.5/3.3V)
Twin-well CMOSTwin-well CMOS Hyperabrupt Junction and MOS VaractorsHyperabrupt Junction and MOS Varactors
Deep Trench and Shallow Trench IsolationsDeep Trench and Shallow Trench Isolations 3 to 5 Copper Layers and 2 Aluminum Layers (up to 3 thick layers)3 to 5 Copper Layers and 2 Aluminum Layers (up to 3 thick layers) Wire-bond or Controlled Collapse Chip Connect (C4) Solder-bump Wire-bond or Controlled Collapse Chip Connect (C4) Solder-bump
TerminalsTerminals
Cadence Custom IC Design Flow for Cadence Custom IC Design Flow for IBM 8HPIBM 8HP
Design SpecificationVirtuoso Schematic
Analog Design Environment (ADE) AMS Design Environment (AMS)
Virtuoso XL Layout Chip Assembly Router
Assura DRC/LVC, RCX
Schematic Capture
Circuit Simulations
Cell/Chip Layout Verification and RF Parasitic Extraction
ADE, AMS Simulations
Post-Layout Simulations Mask Generation
GDSII Stream Out
DRC, Filler Generation
Validation
Tape-Out
IBM 8HP PDK
Library, tech files
Models
Tech File, DRC, PCell
Tech File , DRC
Models, RCX
Tech File
Tech, Foundry Rules
Interface to Other Simulation Interface to Other Simulation ToolsTools