2009-2013 Microchip Technology Inc. DS60001156H-page 1 PIC32MX5XX/6XX/7XX Operating Conditions • 2.3V to 3.6V, -40ºC to +105ºC, DC to 80 MHz Core: 80 MHz/105 DMIPS MIPS32 ® M4K ® • MIPS16e ® mode for up to 40% smaller code size • Code-efficient (C and Assembly) architecture • Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply Clock Management • 0.9% internal oscillator • Programmable PLLs and oscillator clock sources • Fail-Safe Clock Monitor (FSCM) • Independent Watchdog Timer • Fast wake-up and start-up Power Management • Low-power management modes (Sleep and Idle) • Integrated Power-on Reset, Brown-out Reset • 0.5 mA/MHz dynamic current (typical) • 41 μA IPD current (typical) Graphics Features • External graphics interface with up to 34 Parallel Master Port (PMP) pins: - Interface to external graphics controller - Capable of driving LCD directly with DMA and internal or external memory Analog Features • ADC Module: - 10-bit 1 Msps rate with one Sample and Hold (S&H) - 16 analog inputs - Can operate during Sleep mode • Flexible and independent ADC trigger sources • Comparators: - Two dual-input Comparator modules - Programmable references with 32 voltage points Timers/Output Compare/Input Capture • Five General Purpose Timers: - Five 16-bit and up to two 32-bit Timers/Counters • Five Output Compare (OC) modules • Five Input Capture (IC) modules • Real-Time Clock and Calendar (RTCC) module Communication Interfaces • USB 2.0-compliant Full-Speed OTG controller • 10/100 Mbps Ethernet MAC with MII and RMII interface • CAN module: - 2.0B Active with DeviceNet™ addressing support • Six UART modules (20 Mbps): - Supports LIN 1.2 protocols and IrDA ® support • Up to four 4-wire SPI modules (25 Mbps) • Up to five I 2 C modules (up to 1 Mbaud) with SMBus support • Parallel Master Port (PMP) Direct Memory Access (DMA) • Up to eight channels of hardware DMA with automatic data size detection • 32-bit Programmable Cyclic Redundancy Check (CRC) • Six additional channels dedicated to USB, Ethernet and CAN modules Input/Output • 15 mA or 10 mA source/sink for standard VOH/VOL and up to 22 mA for non-standard VOH1 • 5V-tolerant pins • Selectable open drain and pull-ups • External interrupts Qualification and Class B Support • AEC-Q100 REVG (Grade 2 -40ºC to +105ºC) planned • Class B Safety Library, IEC 60730 Debugger Development Support • In-circuit and in-application programming • 4-wire MIPS ® Enhanced JTAG interface • Unlimited program and six complex data breakpoints • IEEE 1149.2-compatible (JTAG) boundary scan Packages Type QFN TQFP TFBGA VTLA Pin Count 64 64 100 100 121 124 I/O Pins (up to) 51 51 83 83 83 83 Contact/Lead Pitch 0.50 0.50 0.40 0.50 0.80 0.50 Dimensions 9x9x0.9 10x10x1 12x12x1 14x14x1 10x10x1.1 9x9x0.9 Note: All dimensions are in millimeters (mm) unless specified. 32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM) with Graphics Interface, USB, CAN, and Ethernet
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PIC32MX5XX/6XX/7XX32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM)
with Graphics Interface, USB, CAN, and Ethernet
Operating Conditions• 2.3V to 3.6V, -40ºC to +105ºC, DC to 80 MHz
Core: 80 MHz/105 DMIPS MIPS32® M4K®
• MIPS16e® mode for up to 40% smaller code size• Code-efficient (C and Assembly) architecture• Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply
Clock Management• 0.9% internal oscillator• Programmable PLLs and oscillator clock sources• Fail-Safe Clock Monitor (FSCM)• Independent Watchdog Timer• Fast wake-up and start-up
Power Management• Low-power management modes (Sleep and Idle)• Integrated Power-on Reset, Brown-out Reset• 0.5 mA/MHz dynamic current (typical)• 41 µA IPD current (typical)
Graphics Features• External graphics interface with up to 34 Parallel Master
Port (PMP) pins:- Interface to external graphics controller- Capable of driving LCD directly with DMA and
internal or external memory
Analog Features• ADC Module:
- 10-bit 1 Msps rate with one Sample and Hold (S&H)- 16 analog inputs- Can operate during Sleep mode
• Flexible and independent ADC trigger sources• Comparators:
- Two dual-input Comparator modules- Programmable references with 32 voltage points
Timers/Output Compare/Input Capture• Five General Purpose Timers:
- Five 16-bit and up to two 32-bit Timers/Counters• Five Output Compare (OC) modules• Five Input Capture (IC) modules• Real-Time Clock and Calendar (RTCC) module
Communication Interfaces• USB 2.0-compliant Full-Speed OTG controller• 10/100 Mbps Ethernet MAC with MII and RMII interface• CAN module:
- 2.0B Active with DeviceNet™ addressing support• Six UART modules (20 Mbps):
- Supports LIN 1.2 protocols and IrDA® support• Up to four 4-wire SPI modules (25 Mbps)• Up to five I2C modules (up to 1 Mbaud) with SMBus
support• Parallel Master Port (PMP)
Direct Memory Access (DMA)• Up to eight channels of hardware DMA with automatic
data size detection• 32-bit Programmable Cyclic Redundancy Check (CRC)• Six additional channels dedicated to USB, Ethernet and
CAN modules
Input/Output• 15 mA or 10 mA source/sink for standard VOH/VOL and
up to 22 mA for non-standard VOH1 • 5V-tolerant pins• Selectable open drain and pull-ups• External interrupts
Qualification and Class B Support• AEC-Q100 REVG (Grade 2 -40ºC to +105ºC) planned• Class B Safety Library, IEC 60730
Debugger Development Support• In-circuit and in-application programming• 4-wire MIPS® Enhanced JTAG interface• Unlimited program and six complex data breakpoints• IEEE 1149.2-compatible (JTAG) boundary scan
Note 1: This device features 12 KB boot Flash memory.2: CTS and RTS pins may not be available for all UART modules. Refer to the “Pin Diagrams” section for more
information.3: Some pins between the UART, SPI and I2C modules may be shared. Refer to the “Pin Diagrams” section for more
information.4: Refer to Section33.0 “Packaging Information” for more information.5: 100-pin devices in the VTLA package are available upon request. Please contact your local Microchip Sales Office for
details.
DS60001156H-page 2 2009-2013 Microchip Technology Inc.
Note 1: This device features 12 KB boot Flash memory.2: CTS and RTS pins may not be available for all UART modules. Refer to the “Pin Diagrams” section for more
information.3: Some pins between the UART, SPI and I2C modules may be shared. Refer to the “Pin Diagrams” section for more
information.4: Refer to Section33.0 “Packaging Information” for more information.5: 100-pin devices other than those listed here are available in the VTLA package upon request. Please contact your local
Microchip Sales Office for details.
2009-2013 Microchip Technology Inc. DS60001156H-page 3
Note 1: This device features 12 KB boot Flash memory.2: CTS and RTS pins may not be available for all UART modules. Refer to the “Pin Diagrams” section for more
information.3: Some pins between the UART, SPI and I2C modules may be shared. Refer to the “Pin Diagrams” section for more
information.4: Refer to Section 33.0 “Packaging Information” for more information.5: 100-pin devices other than those listed here are available in the VTLA package upon request. Please contact your local
Microchip Sales Office for details.
DS60001156H-page 4 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Pin Diagrams
64-Pin QFN(1) = Pins are up to 5V tolerant
Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
TABLE 8: PIN NAMES: PIC32MX675F512L, PIC32MX695F512L, AND PIC32MX795F512L DEVICES
Package Bump #
Full Pin NamePackage Bump #
Full Pin Name
Note 1: This pin is only available on PIC32MX795F512L devices.
DS60001156H-page 28 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 332.0 Guidelines for Getting Started with 32-bit MCUs........................................................................................................................ 453.0 CPU............................................................................................................................................................................................ 494.0 Memory Organization ................................................................................................................................................................. 555.0 Flash Program Memory............................................................................................................................................................ 1236.0 Resets ...................................................................................................................................................................................... 1277.0 Interrupt Controller ................................................................................................................................................................... 1318.0 Oscillator Configuration ............................................................................................................................................................ 1419.0 Prefetch Cache......................................................................................................................................................................... 14710.0 Direct Memory Access (DMA) Controller ................................................................................................................................. 15711.0 USB On-The-Go (OTG)............................................................................................................................................................ 17312.0 I/O Ports ................................................................................................................................................................................... 19313.0 Timer1 ...................................................................................................................................................................................... 19714.0 Timer2/3, Timer4/5 ................................................................................................................................................................... 20115.0 Input Capture............................................................................................................................................................................ 20516.0 Output Compare....................................................................................................................................................................... 20917.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 21118.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 21719.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 22320.0 Parallel Master Port (PMP)....................................................................................................................................................... 22921.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 23722.0 10-bit Analog-to-Digital Converter (ADC) ................................................................................................................................. 24723.0 Controller Area Network (CAN) ................................................................................................................................................ 25524.0 Ethernet Controller ................................................................................................................................................................... 28925.0 Comparator .............................................................................................................................................................................. 33126.0 Comparator Voltage Reference (CVREF) ................................................................................................................................. 33527.0 Power-Saving Features ........................................................................................................................................................... 33728.0 Special Features ...................................................................................................................................................................... 33929.0 Instruction Set .......................................................................................................................................................................... 35330.0 Development Support............................................................................................................................................................... 35531.0 Electrical Characteristics .......................................................................................................................................................... 35932.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 40733.0 Packaging Information.............................................................................................................................................................. 409The Microchip Web Site..................................................................................................................................................................... 443Customer Change Notification Service .............................................................................................................................................. 443Customer Support .............................................................................................................................................................................. 443Reader Response .............................................................................................................................................................................. 444Product Identification System ............................................................................................................................................................ 445
2009-2013 Microchip Technology Inc. DS60001156H-page 29
PIC32MX5XX/6XX/7XX
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use ofyour Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our pub-lications will be refined and enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing CommunicationsDepartment via E-mail at [email protected] or fax the Reader Response Form in the back of this datasheet to (480) 792-4150. We welcome your feedback.
Most Current Data Sheet
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You can determine the version of a data sheet by examining its literature number found on the bottom outside cornerof any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A ofdocument DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, mayexist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. Theerrata will specify the revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literaturenumber) you are using.
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DS60001156H-page 30 2009-2013 Microchip Technology Inc.
This device data sheet is based on the followingindividual chapters of the “PIC32 Family ReferenceManual”. These documents should be considered asthe general reference for the operation of a particularmodule or device feature.
• Section 33. “Programming and Diagnostics” (DS60001129)
• Section 34. “Controller Area Network (CAN)” (DS60001154)
• Section 35. “Ethernet Controller” (DS60001155)
Note 1: To access the documents listed below,browse to the documentation section ofthe PIC32MX795F512L product page onthe Microchip web site(www.microchip.com) or select a familyreference manual section from thefollowing list.
In addition to parameters, features, andother documentation, the resulting pageprovides links to the related familyreference manual sections.
2009-2013 Microchip Technology Inc. DS60001156H-page 31
DS60001156H-page 32 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
1.0 DEVICE OVERVIEW This document contains device-specific information forPIC32MX5XX/6XX/7XX devices.
Figure 1-1 illustrates a general block diagram of thecore and peripheral modules in the PIC32MX5XX/6XX/7XX family of devices.
Table 1-1 lists the functions of the various pins shownin the pinout diagrams.
FIGURE 1-1: BLOCK DIAGRAM(1,2)
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to the related section of the“PIC32 Family Reference Manual”, whichis available from the Microchip web site(www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
Note 1: Some features are not available on all devices.
2: BOR functionality is provided when the on-board voltage regulator is enabled.
UART1-6
Comparators
PORTA
PORTD
PORTE
PORTF
PORTG
PORTB
CN1-22
JTAGPriority
DM
AC
ICD
MIPS32® M4K®
IS DS
EJTAG INT
Bus Matrix
PrefetchData RAM
Peripheral Bridge
128
128-bit Wide
Fla
sh
32
32 32
32 32
Pe
riph
era
l Bu
s C
lock
ed b
y P
BC
LK
Program Flash Memory
Co
ntr
olle
r
32
Module
32 32
InterruptControllerBSCAN
PORTC
PMP
I2C1-5
SPI1-4
IC1-5
PWMOC1-5
OSC1/CLKIOSC2/CLKO
VDD, VSS
TimingGeneration
MCLR
Power-upTimer
OscillatorStart-up Timer
Power-onReset
WatchdogTimer
Brown-outReset
Precision
ReferenceBand Gap
FRC/LPRCOscillators
RegulatorVoltage
VCAPOSC/SOSCOscillators
PLL
Dividers
SYSCLKPBCLK
Peripheral Bus Clocked by SYSCLK
US
B
PLL-USBUSBCLK
32
RTCC
10-bit ADC
Timer1-5
32
32
CA
N1,
CA
N2
ET
HE
RN
ET
32 32
CPU Core
2009-2013 Microchip Technology Inc. DS60001156H-page 33
CMOSExternal clock source input. Always associated with OSC1 pin function.
CLKO 40 64 F11 A42 O —
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function.
OSC1 39 63 F9 B34 IST/
CMOS
Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.
OSC2 40 64 F11 A42 I/O —
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = PowerST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Pin Diagrams” section for device pin availability.2: See Section 24.0 “Ethernet Controller” for more information.
DS60001156H-page 34 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
CN0 48 74 B11 B40 I ST Change notification inputs. Can be software programmed for internal weak pull-ups on all inputs.
CN1 47 73 C10 A47 I ST
CN2 16 25 K2 B14 I ST
CN3 15 24 K1 A15 I ST
CN4 14 23 J2 B13 I ST
CN5 13 22 J1 A13 I ST
CN6 12 21 H2 B11 I ST
CN7 11 20 H1 A12 I ST
CN8 4 10 E3 A7 I ST
CN9 5 11 F4 B6 I ST
CN10 6 12 F2 A8 I ST
CN11 8 14 F3 A9 I ST
CN12 30 44 L8 A29 I ST
CN13 52 81 C8 B44 I ST
CN14 53 82 B8 A55 I ST
CN15 54 83 D7 B45 I ST
CN16 55 84 C7 A56 I ST
CN17 31 49 L10 B27 I ST
CN18 32 50 L11 A32 I ST
CN19 — 80 D8 A54 I ST
CN20 — 47 L9 B26 I ST
CN21 — 48 K9 A31 I ST
IC1 42 68 E9 B37 I ST Capture Inputs 1-5
IC2 43 69 E10 A45 I ST
IC3 44 70 D11 B38 I ST
IC4 45 71 C11 A46 I ST
IC5 52 79 A9 A60 I ST
OCFA 17 26 L1 A20 I ST Output Compare Fault A Input
OC1 46 72 D9 B39 O — Output Compare Output 1
OC2 49 76 A11 A52 O — Output Compare Output 2
OC3 50 77 A10 B42 O — Output Compare Output 3
OC4 51 78 B9 A53 O — Output Compare Output 4
OC5 52 81 C8 B44 O — Output Compare Output 5
OCFB 30 44 L8 A29 I ST Output Compare Fault B Input
INT0 46 72 D9 B39 I ST External Interrupt 0
INT1 42 18 G1 A11 I ST External Interrupt 1
INT2 43 19 G2 B10 I ST External Interrupt 2
INT3 44 66 E11 B36 I ST External Interrupt 3
INT4 45 67 E8 A44 I ST External Interrupt 4
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number(1)
PinType
BufferType
Description64-PinQFN/TQFP
100-PinTQFP
121-PinTFBGA
124-pin VTLA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = PowerST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Pin Diagrams” section for device pin availability.2: See Section 24.0 “Ethernet Controller” for more information.
2009-2013 Microchip Technology Inc. DS60001156H-page 35
PIC32MX5XX/6XX/7XX
RA0 — 17 G3 B9 I/O ST PORTA is a bidirectional I/O port
RA1 — 38 J6 A26 I/O ST
RA2 — 58 H11 A39 I/O ST
RA3 — 59 G10 B32 I/O ST
RA4 — 60 G11 A40 I/O ST
RA5 — 61 G9 B33 I/O ST
RA6 — 91 C5 B51 I/O ST
RA7 — 92 B5 A62 I/O ST
RA9 — 28 L2 A21 I/O ST
RA10 — 29 K3 B17 I/O ST
RA14 — 66 E11 B36 I/O ST
RA15 — 67 E8 A44 I/O ST
RB0 16 25 K2 B14 I/O ST PORTB is a bidirectional I/O port
RB1 15 24 K1 A15 I/O ST
RB2 14 23 J2 B13 I/O ST
RB3 13 22 J1 A13 I/O ST
RB4 12 21 H2 B11 I/O ST
RB5 11 20 H1 A12 I/O ST
RB6 17 26 L1 A20 I/O ST
RB7 18 27 J3 B16 I/O ST
RB8 21 32 K4 A23 I/O ST
RB9 22 33 L4 B19 I/O ST
RB10 23 34 L5 A24 I/O ST
RB11 24 35 J5 B20 I/O ST
RB12 27 41 J7 B23 I/O ST
RB13 28 42 L7 A28 I/O ST
RB14 29 43 K7 B24 I/O ST
RB15 30 44 L8 A29 I/O ST
RC1 — 6 D1 A5 I/O ST PORTC is a bidirectional I/O port
RC2 — 7 E4 B4 I/O ST
RC3 — 8 E2 A6 I/O ST
RC4 — 9 E1 B5 I/O ST
RC12 39 63 F9 B34 I/O ST
RC13 47 73 C10 A47 I/O ST
RC14 48 74 B11 B40 I/O ST
RC15 40 64 F11 A42 I/O ST
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number(1)
PinType
BufferType
Description64-PinQFN/TQFP
100-PinTQFP
121-PinTFBGA
124-pin VTLA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = PowerST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Pin Diagrams” section for device pin availability.2: See Section 24.0 “Ethernet Controller” for more information.
DS60001156H-page 36 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
RD0 46 72 D9 B39 I/O ST PORTD is a bidirectional I/O port
RD1 49 76 A11 A52 I/O ST
RD2 50 77 A10 B42 I/O ST
RD3 51 78 B9 A53 I/O ST
RD4 52 81 C8 B44 I/O ST
RD5 53 82 B8 A55 I/O ST
RD6 54 83 D7 B45 I/O ST
RD7 55 84 C7 A56 I/O ST
RD8 42 68 E9 B37 I/O ST
RD9 43 69 E10 A45 I/O ST
RD10 44 70 D11 B38 I/O ST
RD11 45 71 C11 A46 I/O ST
RD12 — 79 A9 B43 I/O ST
RD13 — 80 D8 A54 I/O ST
RD14 — 47 L9 B26 I/O ST
RD15 — 48 K9 A31 I/O ST
RE0 60 93 A4 B52 I/O ST PORTE is a bidirectional I/O port
RE1 61 94 B4 A64 I/O ST
RE2 62 98 B3 A66 I/O ST
RE3 63 99 A2 B56 I/O ST
RE4 64 100 A1 A67 I/O ST
RE5 1 3 D3 B2 I/O ST
RE6 2 4 C1 A4 I/O ST
RE7 3 5 D2 B3 I/O ST
RE8 — 18 G1 A11 I/O ST
RE9 — 19 G2 B10 I/O ST
RF0 58 87 B6 B49 I/O ST PORTF is a bidirectional I/O port
RF1 59 88 A6 A60 I/O ST
RF2 — 52 K11 A36 I/O ST
RF3 33 51 K10 A35 I/O ST
RF4 31 49 L10 B27 I/O ST
RF5 32 50 L11 A32 I/O ST
RF8 — 53 J10 B29 I/O ST
RF12 — 40 K6 A27 I/O ST
RF13 — 39 L6 B22 I/O ST
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number(1)
PinType
BufferType
Description64-PinQFN/TQFP
100-PinTQFP
121-PinTFBGA
124-pin VTLA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = PowerST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Pin Diagrams” section for device pin availability.2: See Section 24.0 “Ethernet Controller” for more information.
2009-2013 Microchip Technology Inc. DS60001156H-page 37
PIC32MX5XX/6XX/7XX
RG0 — 90 A5 A61 I/O ST PORTG is a bidirectional I/O port
RG1 — 89 E6 B50 I/O ST
RG6 4 10 E3 A7 I/O ST
RG7 5 11 F4 B6 I/O ST
RG8 6 12 F2 A8 I/O ST
RG9 8 14 F3 A9 I/O ST
RG12 — 96 C3 A65 I/O ST
RG13 — 97 A3 B55 I/O ST
RG14 — 95 C4 B54 I/O ST
RG15 — 1 B2 A2 I/O ST
RG2 37 57 H10 B31 I ST PORTG input pins
RG3 36 56 J11 A38 I ST
T1CK 48 74 B11 B40 I ST Timer1 external clock input
T2CK — 6 D1 A5 I ST Timer2 external clock input
T3CK — 7 E4 B4 I ST Timer3 external clock input
T4CK — 8 E2 A6 I ST Timer4 external clock input
T5CK — 9 E1 B5 I ST Timer5 external clock input
U1CTS 43 47 L9 B26 I ST UART1 clear to send
U1RTS 49 48 K9 A31 O — UART1 ready to send
U1RX 50 52 K11 A36 I ST UART1 receive
U1TX 51 53 J10 B29 O — UART1 transmit
U3CTS 8 14 F3 A9 I ST UART3 clear to send
U3RTS 4 10 E3 A7 O — UART3 ready to send
U3RX 5 11 F4 B6 I ST UART3 receive
U3TX 6 12 F2 A8 O — UART3 transmit
U2CTS 21 40 K6 A27 I ST UART2 clear to send
U2RTS 29 39 L6 B22 O — UART2 ready to send
U2RX 31 49 L10 B27 I ST UART2 receive
U2TX 32 50 L11 A32 O — UART2 transmit
U4RX 43 47 L9 B26 I ST UART4 receive
U4TX 49 48 K9 A31 O — UART4 transmit
U6RX 8 14 F3 A9 I ST UART6 receive
U6TX 4 10 E3 A7 O — UART6 transmit
U5RX 21 40 K6 A27 I ST UART5 receive
U5TX 29 39 L6 B22 O — UART5 transmit
SCK1 — 70 D11 B38 I/O STSynchronous serial clock input/output for SPI1
SDI1 — 9 E1 B5 I ST SPI1 data in
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number(1)
PinType
BufferType
Description64-PinQFN/TQFP
100-PinTQFP
121-PinTFBGA
124-pin VTLA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = PowerST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Pin Diagrams” section for device pin availability.2: See Section 24.0 “Ethernet Controller” for more information.
DS60001156H-page 38 2009-2013 Microchip Technology Inc.
SCL1 44 66 E11 B36 I/O STSynchronous serial clock input/output for I2C1
SDA1 43 67 E8 A44 I/O STSynchronous serial data input/output for I2C1
SCL3 51 53 J10 B29 I/O STSynchronous serial clock input/output for I2C3
SDA3 50 52 K11 A36 I/O STSynchronous serial data input/output for I2C3
SCL2 — 58 H11 A39 I/O STSynchronous serial clock input/output for I2C2
SDA2 — 59 G10 B32 I/O STSynchronous serial data input/output for I2C2
SCL4 6 12 F2 A8 I/O STSynchronous serial clock input/output for I2C4
SDA4 5 11 F4 B6 I/O STSynchronous serial data input/output for I2C4
SCL5 32 50 L11 A32 I/O STSynchronous serial clock input/output for I2C5
SDA5 31 49 L10 B27 I/O STSynchronous serial data input/output for I2C5
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number(1)
PinType
BufferType
Description64-PinQFN/TQFP
100-PinTQFP
121-PinTFBGA
124-pin VTLA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = PowerST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Pin Diagrams” section for device pin availability.2: See Section 24.0 “Ethernet Controller” for more information.
2009-2013 Microchip Technology Inc. DS60001156H-page 39
CVREF- 15 28 L2 A21 I Analog Comparator Voltage Reference (low)
CVREF+ 16 29 K3 B17 I Analog Comparator Voltage Reference (high)
CVREFOUT 23 34 L5 A24 O Analog Comparator Voltage Reference output
C1IN- 12 21 H2 B11 I Analog Comparator 1 negative input
C1IN+ 11 20 H1 A12 I Analog Comparator 1 positive input
C1OUT 21 32 K4 A23 O — Comparator 1 output
C2IN- 14 23 J2 B13 I Analog Comparator 2 negative input
C2IN+ 13 22 J1 A13 I Analog Comparator 2 positive input
C2OUT 22 33 L4 B19 O — Comparator 2 output
PMA0 30 44 L8 A29 I/O TTL/STParallel Master Port Address bit 0 input (Buffered Slave modes) and output (Master modes)
PMA1 29 43 K7 B24 I/O TTL/STParallel Master Port Address bit 1 input (Buffered Slave modes) and output (Master modes)
PMA2 8 14 F3 A9 O — Parallel Master Port address (Demultiplexed Master modes)PMA3 6 12 F2 A8 O —
PMA4 5 11 F4 B6 O —
PMA5 4 10 E3 A7 O —
PMA6 16 29 K3 B17 O —
PMA7 22 28 L2 A21 O —
PMA8 32 50 L11 A32 O —
PMA9 31 49 L10 B27 O —
PMA10 28 42 L7 A28 O —
PMA11 27 41 J7 B23 O —
PMA12 24 35 J5 B20 O —
PMA13 23 34 L5 A24 O —
PMA14 45 71 C11 A46 O —
PMA15 44 70 D11 B38 O —
PMCS1 45 71 C11 A46 O —Parallel Master Port Chip Select 1 strobe
PMCS2 44 70 D11 B38 O —Parallel Master Port Chip Select 2 strobe
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number(1)
PinType
BufferType
Description64-PinQFN/TQFP
100-PinTQFP
121-PinTFBGA
124-pin VTLA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = PowerST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Pin Diagrams” section for device pin availability.2: See Section 24.0 “Ethernet Controller” for more information.
DS60001156H-page 40 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
PMD0 60 93 A4 B52 I/O TTL/ST Parallel Master Port data (Demultiplexed Master mode) or address/data (Multiplexed Master modes)
PMD1 61 94 B4 A64 I/O TTL/ST
PMD2 62 98 B3 A66 I/O TTL/ST
PMD3 63 99 A2 B56 I/O TTL/ST
PMD4 64 100 A1 A67 I/O TTL/ST
PMD5 1 3 D3 B2 I/O TTL/ST
PMD6 2 4 C1 A4 I/O TTL/ST
PMD7 3 5 D2 B3 I/O TTL/ST
PMD8 — 90 A5 A61 I/O TTL/ST
PMD9 — 89 E6 B50 I/O TTL/ST
PMD10 — 88 A6 A60 I/O TTL/ST
PMD11 — 87 B6 B49 I/O TTL/ST
PMD12 — 79 A9 B43 I/O TTL/ST
PMD13 — 80 D8 A54 I/O TTL/ST
PMD14 — 83 D7 B45 I/O TTL/ST
PMD15 — 84 C7 A56 I/O TTL/ST
PMALL 30 44 L8 A29 O —Parallel Master Port address latch enable low byte (Multiplexed Master modes)
PMALH 29 43 K7 B24 O —Parallel Master Port address latch enable high byte (Multiplexed Master modes)
PMRD 53 82 B8 A55 O — Parallel Master Port read strobe
PMWR 52 81 C8 B44 O — Parallel Master Port write strobe
VBUS 34 54 H8 A37 I Analog USB bus power monitor
VUSB3V3 35 55 H9 B30 P —USB internal transceiver supply. If the USB module is not used, this pin must be connected to VDD.
VBUSON 11 20 H1 A12 O —USB Host and OTG bus power control output
D+ 37 57 H10 B31 I/O Analog USB D+
D- 36 56 J11 A38 I/O Analog USB D-
USBID 33 51 K10 A35 I ST USB OTG ID detect
C1RX 58 87 B6 B49 I ST CAN1 bus receive pin
C1TX 59 88 A6 A60 O — CAN1 bus transmit pin
AC1RX 32 40 K6 A27 I ST Alternate CAN1 bus receive pin
AC1TX 31 39 L6 B22 O — Alternate CAN1 bus transmit pin
C2RX 29 90 A5 A61 I ST CAN2 bus receive pin
C2TX 21 89 E6 B50 O — CAN2 bus transmit pin
AC2RX — 8 E2 A6 1 ST Alternate CAN2 bus receive pin
AC2TX — 7 E4 B4 O — Alternate CAN2 bus transmit pin
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number(1)
PinType
BufferType
Description64-PinQFN/TQFP
100-PinTQFP
121-PinTFBGA
124-pin VTLA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = PowerST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Pin Diagrams” section for device pin availability.2: See Section 24.0 “Ethernet Controller” for more information.
2009-2013 Microchip Technology Inc. DS60001156H-page 41
PIC32MX5XX/6XX/7XX
ERXD0 61 41 J7 B23 I ST Ethernet Receive Data 0(2)
ERXD1 60 42 L7 A28 I ST Ethernet Receive Data 1(2)
ERXD2 59 43 K7 B24 I ST Ethernet Receive Data 2(2)
ERXD3 58 44 L8 A29 I ST Ethernet Receive Data 3(2)
ERXERR 64 35 J5 B20 I ST Ethernet receive error input(2)
ERXDV 62 12 F2 A8 I ST Ethernet receive data valid(2)
ECRSDV 62 12 F2 A8 I ST Ethernet carrier sense data valid(2)
ERXCLK 63 14 F3 A9 I ST Ethernet receive clock(2)
EREFCLK 63 14 F3 A9 I ST Ethernet reference clock(2)
ETXD0 2 88 A6 A60 O — Ethernet Transmit Data 0(2)
ETXD1 3 87 B6 B49 O — Ethernet Transmit Data 1(2)
ETXD2 43 79 A9 B43 O — Ethernet Transmit Data 2(2)
ETXD3 42 80 D8 A54 O — Ethernet Transmit Data 3(2)
ETXERR 54 89 E6 B50 O — Ethernet transmit error(2)
ETXEN 1 83 D7 B45 O — Ethernet transmit enable(2)
ETXCLK 55 84 C7 A56 I ST Ethernet transmit clock(2)
ECOL 44 10 E3 A7 I ST Ethernet collision detect(2)
ECRS 45 11 F4 B6 I ST Ethernet carrier sense(2)
EMDC 30 71 C11 A46 O — Ethernet management data clock(2)
AETXCLK — 66 E11 B36 I ST Alternate Ethernet transmit clock(2)
AECOL — 42 L7 A28 I ST Alternate Ethernet collision detect(2)
AECRS — 41 J7 B23 I ST Alternate Ethernet carrier sense(2)
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number(1)
PinType
BufferType
Description64-PinQFN/TQFP
100-PinTQFP
121-PinTFBGA
124-pin VTLA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = PowerST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Pin Diagrams” section for device pin availability.2: See Section 24.0 “Ethernet Controller” for more information.
DS60001156H-page 42 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
AEMDC 30 71 C11 A46 O —Alternate Ethernet Management Data clock(2)
PGED1 16 25 K2 B14 I/O STData I/O pin for Programming/Debugging Communication Channel 1
PGEC1 15 24 K1 A15 I STClock input pin for Programming/Debugging Communication Channel 1
PGED2 18 27 J3 B16 I/O STData I/O pin for Programming/Debugging Communication Channel 2
PGEC2 17 26 L1 A20 I STClock input pin for Programming/Debugging Communication Channel 2
MCLR 7 13 F1 B7 I/P STMaster Clear (Reset) input. This pin is an active-low Reset to the device.
AVDD 19 30 J4 A22 P PPositive supply for analog modules. This pin must be connected at all times.
AVSS 20 31 L3 B18 P P Ground reference for analog modules
VDD10, 26, 38,
572, 16, 37, 46, 62, 86
A7, C2, C9, E5, K8, F8, G5, H4,
H6
A10, A14, A30, A41, A48, A59, B1, B21,
B53
P —
Positive supply for peripheral logic and I/O pins
VCAP 56 85 B7 B48 P — Capacitor for Internal Voltage Regulator
VSS 9, 25, 4115, 36, 45,
65, 75
A8, B10, D4, D5, E7, F5,
F10, G6, G7, H3
A3, A25, A43, A63, B8, B12,
B25, B41, B46
P —
Ground reference for logic and I/O pins. This pin must be connected at all times.
VREF+ 16 29 K3 B17 I Analog Analog voltage reference (high) input
VREF- 15 28 L2 A21 I Analog Analog voltage reference (low) input
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number(1)
PinType
BufferType
Description64-PinQFN/TQFP
100-PinTQFP
121-PinTFBGA
124-pin VTLA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = PowerST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Pin Diagrams” section for device pin availability.2: See Section 24.0 “Ethernet Controller” for more information.
2009-2013 Microchip Technology Inc. DS60001156H-page 43
PIC32MX5XX/6XX/7XX
NOTES:
DS60001156H-page 44 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
2.0 GUIDELINES FOR GETTING STARTED WITH 32-BIT MCUS
2.1 Basic Connection Requirements
Getting started with the PIC32MX5XX/6XX/7XX familyof 32-bit Microcontrollers (MCUs) requires attention toa minimal set of device pin connections before pro-ceeding with development. The following is a list of pinnames, which must always be connected:
• All VDD and VSS pins (see 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins even if the ADC module is not used (see 2.2 “Decoupling Capacitors”)
• VCAP pin (see 2.3 “Capacitor on Internal Voltage Regulator (VCAP)”)
• MCLR pin (see 2.4 “Master Clear (MCLR) Pin”)• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes (see 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins when external oscillator source is used (see 2.8 “External Oscillator Pins”)
The following pin may be required, as well: VREF+/VREF- pins used when external voltage reference forADC module is implemented.
2.2 Decoupling Capacitors
The use of decoupling capacitors on power supplypins, such as VDD, VSS, AVDD and AVSS is required.See Figure 2-1.
Consider the following criteria when using decouplingcapacitors:
• Value and type of capacitor: A value of 0.1 µF (100 nF), 10-20V is recommended. The capacitor should be a low Equivalent Series Resistance (low-ESR) capacitor and have resonance fre-quency in the range of 20 MHz and higher. It is further recommended to use ceramic capacitors.
• Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended that the capacitors be placed on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length.
• Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB track inductance.
FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION
2.2.1 BULK CAPACITORS
The use of a bulk capacitor is recommended to improvepower supply stability. Typical values range from 4.7 µFto 47 µF. This capacitor should be located as close tothe device as possible.
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to the related section of the“PIC32 Family Reference Manual”, whichis available from the Microchip web site(www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
Note: The AVDD and AVSS pins must beconnected, regardless of the ADC useand the ADC voltage reference source.
PIC32MX
VD
D
VS
S
VDD
VSS
VSS
VDD
AV
DD
AV
SS
VD
D
VS
S
C
R
VDD
MCLR
0.1 µFCeramic
VC
AP
10
R1
CBP
0.1 µFCeramicCBP
0.1 µFCeramicCBP
0.1 µFCeramicCBP
0.1 µFCeramicCBP
CEFC
VUSB3V3(1)
Note 1: If the USB module is used, this pin must be connected to VDD.
2009-2013 Microchip Technology Inc. DS60001156H-page 45
2.3 Capacitor on Internal Voltage Regulator (VCAP)
2.3.1 INTERNAL REGULATOR MODE
A low-ESR (1 ohm) capacitor is required on the VCAP
pin, which is used to stabilize the internal voltage regu-lator output. The VCAP pin must not be connected toVDD, and must have a CEFC capacitor, with at least a6V rating, connected to ground. The type can beceramic or tantalum. Refer to Section 31.0 “ElectricalCharacteristics” for additional information on CEFC
specifications.
2.4 Master Clear (MCLR) Pin
The MCLR pin provides two specific devicefunctions:
• Device Reset• Device Programming and Debugging
Pulling The MCLR pin low generates a device Reset.Figure 2-2 illustrates a typical MCLR circuit. Duringdevice programming and debugging, the resistanceand capacitance that can be added to the pin mustbe considered. Device programmers and debuggersdrive the MCLR pin. Consequently, specific voltagelevels (VIH and VIL) and fast signal transitions mustnot be adversely affected. Therefore, specific valuesof R and C will need to be adjusted based on theapplication and PCB requirements.
For example, as illustrated in Figure 2-2, it isrecommended that the capacitor C, be isolated fromthe MCLR pin during programming and debuggingoperations.
Place the components illustrated in Figure 2-2 withinone-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS
2.5 ICSP Pins
The PGECx and PGEDx pins are used for In-CircuitSerial Programming™ (ICSP™) and debugging pur-poses. It is recommended to keep the trace lengthbetween the ICSP connector and the ICSP pins on thedevice as short as possible. If the ICSP connector isexpected to experience an ESD event, a series resistoris recommended, with the value in the range of a fewtens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes and capacitors on thePGECx and PGEDx pins are not recommended as theywill interfere with the programmer/debugger communi-cations to the device. If such discrete components arean application requirement, they should be removedfrom the circuit during programming and debugging.Alternatively, refer to the AC/DC characteristics andtiming requirements information in the respectivedevice Flash programming specification for informationon capacitive loading limits and pin input voltage high(VIH) and input low (VIL) requirements.
Ensure that the “Communication Channel Select” (i.e.,PGECx/PGEDx pins) programmed into the devicematches the physical connections for the ICSP toMPLAB® ICD 3 or MPLAB® REAL ICE™.
For more information on ICD 3 and REAL ICE connec-tion requirements, refer to the following documents thatare available on the Microchip web site.
• “Using MPLAB® ICD 3” (poster) (DS50001765)
• “MPLAB® ICD 3 Design Advisory” (DS50001764)
• “MPLAB® REAL ICE™ In-Circuit Emulator User’s Guide” (DS50001616)
• “Using MPLAB® REAL ICE™ Emulator” (poster) (DS50001749)
2.6 JTAG
The TMS, TDO, TDI and TCK pins are used for testingand debugging according to the Joint Test ActionGroup (JTAG) standard. It is recommended to keep thetrace length between the JTAG connector and theJTAG pins on the device as short as possible. If theJTAG connector is expected to experience an ESDevent, a series resistor is recommended, with the valuein the range of a few tens of Ohms, not to exceed 100Ohms.
Pull-up resistors, series diodes and capacitors on theTMS, TDO, TDI and TCK pins are not recommendedas they will interfere with the programmer/debuggercommunications to the device. If such discrete compo-nents are an application requirement, they should beremoved from the circuit during programming anddebugging. Alternatively, refer to the AC/DC character-istics and timing requirements information in therespective device Flash programming specification forinformation on capacitive loading limits and pin inputvoltage high (VIH) and input low (VIL) requirements.
Note 1: R 10 k is recommended. A suggestedstarting value is 10 k. Ensure that the MCLRpin VIH and VIL specifications are met.
2: R1 470 will limit any current flowing intoMCLR from the external capacitor C, in theevent of MCLR pin breakdown, due toElectrostatic Discharge (ESD) or ElectricalOverstress (EOS). Ensure that the MCLR pinVIH and VIL specifications are met.
3: The capacitor can be sized to prevent uninten-tional Resets from brief glitches or to extendthe device Reset period during the POR.
C(3)
R1(2)R(1)
VDD
MCLR
PIC32JP
DS60001156H-page 46 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
2.7 Trace
The trace pins can be connected to a hardware-trace-enabled programmer to provide a compress real timeinstruction trace. When used for trace the TRD3,TRD2, TRD1, TRD0 and TRCLK pins should bededicated for this use. The trace hardware requiresa 22 series resistor between the trace pins and thetrace connector.
2.8 External Oscillator Pins
Many MCUs have options for at least two oscillators: ahigh-frequency primary oscillator and a low-frequencysecondary oscillator. Refer to Section 8.0 “OscillatorConfiguration” for details.
The oscillator circuit should be placed on the same sideof the board as the device. Also, place the oscillator cir-cuit close to the respective oscillator pins, not exceed-ing one-half inch (12 mm) distance between them. Theload capacitors should be placed next to the oscillatoritself, on the same side of the board. Use a groundedcopper pour around the oscillator circuit to isolate themfrom surrounding circuits. The grounded copper pourshould be routed directly to the MCU ground. Do notrun any signal traces or power traces inside the groundpour. Also, if using a two-sided board, avoid any traceson the other side of the board where the crystal isplaced. A suggested layout is illustrated in Figure 2-3.
2.9 Configuration of Analog and Digital Pins During ICSP Operations
If MPLAB ICD 3 or REAL ICE is selected as adebugger, it automatically initializes all of the Analog-to-Digital input pins (ANx) as “digital” pins by settingall bits in the AD1PCFG register.
The bits in this register that correspond to the Analog-to-Digital pins that are initialized by MPLAB ICD 3 orREAL ICE, must not be cleared by the user applicationfirmware; otherwise, communication errors will resultbetween the debugger and the device.
If your application needs to use certain ADC pins asanalog input pins during the debug session, the userapplication must clear the corresponding bits in theAD1PCFG register during initialization of the ADCmodule.
When MPLAB ICD 3 or REAL ICE is used as a pro-grammer, the user application firmware must correctlyconfigure the AD1PCFG register. Automatic initializa-tion of this register is only done during debugger oper-ation. Failure to correctly configure the register(s) willresult in all ADC pins being recognized as analog inputpins, resulting in the port value being read as a logic ‘0’,which may affect user application functionality.
2.10 Unused I/Os
Unused I/O pins should not be allowed to float asinputs. They can be configured as outputs and drivento a logic-low state.
Alternatively, inputs can be reserved by connecting thepin to VSS through a 1k to 10k resistor and configuringthe pin as an input.
Main Oscillator
Guard Ring
Guard Trace
SecondaryOscillator
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NOTES:
DS60001156H-page 48 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
3.0 CPU
The MIPS32® M4K® Processor core is the heart of thePIC32MX5XX/6XX/7XX family processor. The CPUfetches instructions, decodes each instruction, fetchessource operands, executes each instruction and writesthe results of instruction execution to the properdestinations.
3.1 Features
• 5-stage pipeline• 32-bit address and data paths• MIPS32® Enhanced Architecture (Release 2)
- Multiply-accumulate and multiply-subtract instructions
- Atomic interrupt enable/disable- GPR shadow registers to minimize latency
for interrupt handlers- Bit field manipulation instructions
• MIPS16e® code compression- 16-bit encoding of 32-bit instructions to
improve code density- Special PC-relative instructions for efficient
loading of addresses and constants- SAVE and RESTORE macro instructions for
setting up and tearing down stack frames within subroutines
- Improved support for handling 8-bit and 16-bit data types
• Simple Fixed Mapping Translation (FMT)mechanism
• Simple dual bus interface- Independent 32-bit address and data busses- Transactions can be aborted to improve
interrupt latency• Autonomous multiply/divide unit
- Maximum issue rate of one 32x16 multiply per clock
- Maximum issue rate of one 32x32 multiply every other clock
- Early-in iterative divide. Minimum 11 and maximum 33 clock latency (dividend (rs) sign extension-dependent)
• Power control- Minimum frequency: 0 MHz- Low-Power mode (triggered by WAIT
instruction)- Extensive use of local gated clocks
• EJTAG debug and instruction trace- Support for single stepping- Virtual instruction and data address/value- Breakpoints- PC tracing with trace compression
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 2. “CPU”(DS60001113) in the “PIC32 FamilyReference Manual”, which is availablefrom the Microchip web site (www.micro-chip.com/PIC32). Resources for theMIPS32® M4K® Processor Core areavailable at http://www.mips.com.
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
CPU
MDU
Execution Core(RF/ALU/Shift)
FMT
TAP
EJTAG
Bus Interface
PowerManagement
SystemCo-processor
Off-chip Debug Interface
Bus MatrixDual Bus Interface
2009-2013 Microchip Technology Inc. DS60001156H-page 49
The MIPS® M4K® processor core contains severallogic blocks working together in parallel, providing anefficient high-performance computing engine. Thefollowing blocks are included with the core:
• Execution Unit• Multiply/Divide Unit (MDU)• System Control Coprocessor (CP0)• Fixed Mapping Translation (FMT)• Dual Internal Bus interfaces• Power Management• MIPS16e® Support• Enhanced JTAG (EJTAG) Controller
3.2.1 EXECUTION UNIT
The MIPS® M4K® processor core execution unit imple-ments a load/store architecture with single-cycle ALUoperations (logical, shift, add, subtract) and an autono-mous multiply/divide unit. The core contains thirty-two32-bit General Purpose Registers (GPRs) used forinteger operations and address calculation. One addi-tional register file shadow set (containing thirty-two reg-isters) is added to minimize context switching overheadduring interrupt/exception processing. The register fileconsists of two read ports and one write port and is fullybypassed to minimize operation latency in the pipeline.
The execution unit includes:
• 32-bit adder used for calculating the data address• Address unit for calculating the next instruction
address• Logic for branch determination and branch target
address calculation• Load aligner• Bypass multiplexers used to avoid stalls when
executing instruction streams where data producing instructions are followed closely by consumers of their results
• Leading Zero/One detect unit for implementing the CLZ and CLO instructions
• Arithmetic Logic Unit (ALU) for performing bit-wise logical operations
• Shifter and store aligner
3.2.2 MULTIPLY/DIVIDE UNIT (MDU)
MIPS® M4K® processor core includes a Multiply/DivideUnit (MDU) that contains a separate pipeline for multi-ply and divide operations. This pipeline operates in par-allel with the Integer Unit (IU) pipeline and does not stallwhen the IU pipeline stalls. This allows MDU opera-tions to be partially masked by system stalls and/orother integer unit instructions.
The high-performance MDU consists of a 32x16 boothrecoded multiplier, result/accumulation registers (HIand LO), a divide state machine, and the necessarymultiplexers and control logic. The first number shown(‘32’ of 32x16) represents the rs operand. The secondnumber (‘16’ of 32x16) represents the rt operand. ThePIC32 core only checks the value of the latter (rt)operand to determine how many times the operationmust pass through the multiplier. The 16x16 and 32x16operations pass through the multiplier once. A 32x32operation passes through the multiplier twice.
The MDU supports execution of one 16x16 or 32x16multiply operation every clock cycle; 32x32 multiplyoperations can be issued every other clock cycle.Appropriate interlocks are implemented to stall theissuance of back-to-back 32x32 multiply operations.The multiply operand size is automatically determinedby logic built into the MDU.
Divide operations are implemented with a simple 1 bitper clock iterative algorithm. An early-in detectionchecks the sign extension of the dividend (rs) operand.If rs is 8 bits wide, 23 iterations are skipped. For a 16 bitwide rs, 15 iterations are skipped and for a 24 bit wide rs,7 iterations are skipped. Any attempt to issue asubsequent MDU instruction while a divide is still activecauses an IU pipeline stall until the divide operation iscompleted.
Table 3-1 lists the repeat rate (peak issue rate of cyclesuntil the operation can be reissued) and latency (num-ber of cycles until a result is available) for the PIC32core multiply and divide instructions. The approximatelatency and repeat rates are listed in terms of pipelineclocks.
TABLE 3-1: MIPS® M4K® CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES
DS60001156H-page 50 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
The MIPS® architecture defines that the result of amultiply or divide operation be placed in the HI and LOregisters. Using the Move-From-HI (MFHI) and Move-From-LO (MFLO) instructions, these values can betransferred to the General Purpose Register file.
In addition to the HI/LO targeted operations, theMIPS32® architecture also defines a multiply instruc-tion, MUL, which places the least significant results inthe primary register file instead of the HI/LO registerpair. By avoiding the explicit MFLO instruction requiredwhen using the LO register, and by supporting multipledestination registers, the throughput of multiply-inten-sive operations is increased.
Two other instructions, Multiply-Add (MADD) andMultiply-Subtract (MSUB), are used to perform themultiply-accumulate and multiply-subtract operations.The MADD instruction multiplies two numbers and thenadds the product to the current contents of the HI andLO registers. Similarly, the MSUB instruction multipliestwo operands and then subtracts the product from theHI and LO registers. The MADD and MSUB operationsare commonly used in DSP algorithms.
3.2.3 SYSTEM CONTROL COPROCESSOR (CP0)
In the MIPS® architecture, CP0 is responsible for thevirtual-to-physical address translation, the exceptioncontrol system, the processor’s diagnostics capability,the operating modes (Kernel, User and Debug) andwhether interrupts are enabled or disabled. Configura-tion information, such as presence of options likeMIPS16e®, is also available by accessing the CP0registers, listed in Table 3-2.
TABLE 3-2: COPROCESSOR 0 REGISTERS
RegisterNumber
Register Name
Function
0-6 Reserved Reserved.
7 HWREna Enables access via the RDHWR instruction to selected hardware registers.
8 BadVAddr(1) Reports the address for the most recent address-related exception.
9 Count(1) Processor cycle count.
10 Reserved Reserved.
11 Compare(1) Timer interrupt control.
12 Status(1) Processor status and control.
12 IntCtl(1) Interrupt system status and control.
12 SRSCtl(1) Shadow register set status and control.
12 SRSMap(1) Provides mapping from vectored interrupt to a shadow set.
13 Cause(1) Cause of last general exception.
14 EPC(1) Program counter at last exception.
15 PRId Processor identification and revision.
15 Ebase Exception vector base register.
16 Config Configuration register.
16 Config1 Configuration Register 1.
16 Config2 Configuration Register 2.
16 Config3 Configuration Register 3.
17-22 Reserved Reserved.
23 Debug(2) Debug control and exception status.
24 DEPC(2) Program counter at last debug exception.
25-29 Reserved Reserved.
30 ErrorEPC(1) Program counter at last error.
31 DESAVE(2) Debug handler scratchpad register.
Note 1: Registers used in exception processing.
2: Registers used during debug.
2009-2013 Microchip Technology Inc. DS60001156H-page 51
PIC32MX5XX/6XX/7XX
Coprocessor 0 also contains the logic for identifyingand managing exceptions. Exceptions can be causedby a variety of sources, including alignment errors indata, external events or program errors. Table 3-3 liststhe exception types in order of priority.
TABLE 3-3: PIC32MX5XX/6XX/7XX FAMILY CORE EXCEPTION TYPES
Exception Description
Reset Assertion MCLR or a Power-on Reset (POR).
DSS EJTAG debug single step.
DINT EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the EjtagBrk bit in the ECR register.
NMI Assertion of NMI signal.
Interrupt Assertion of unmasked hardware or software interrupt signal.
AdEL Fetch address alignment error.Fetch reference to protected address.
IBE Instruction fetch bus error.
DBp EJTAG breakpoint (execution of SDBBP instruction).
Sys Execution of SYSCALL instruction.
Bp Execution of BREAK instruction.
RI Execution of a reserved instruction.
CpU Execution of a coprocessor instruction for a coprocessor that is not enabled.
CEU Execution of a CorExtend instruction when CorExtend is not enabled.
Ov Execution of an arithmetic instruction that overflowed.
Tr Execution of a trap (when trap condition is true).
DDBL/DDBS EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value).
AdEL Load address alignment error.Load reference to protected address.
AdES Store address alignment error.Store to protected address.
DBE Load or store bus error.
DDBL EJTAG data hardware breakpoint matched in load data compare.
DS60001156H-page 52 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
3.3 Power Management
The MIPS® M4K® Processor core offers a number ofpower management features, including low-powerdesign, active power management and power-downmodes of operation. The core is a static design thatsupports slowing or halting the clocks, which reducessystem power consumption during idle periods.
3.3.1 INSTRUCTION-CONTROLLED POWER MANAGEMENT
The mechanism for invoking Power-Down mode isthrough execution of the WAIT instruction. For moreinformation on power management, see Section 27.0“Power-Saving Features”.
3.3.2 LOCAL CLOCK GATING
The majority of the power consumed by the PIC32MX-5XX/6XX/7XX family core is in the clock tree and clock-ing registers. The PIC32 family uses extensive use oflocal gated clocks to reduce this dynamic power con-sumption.
3.4 EJTAG Debug Support
The MIPS® M4K® Processor core provides for anEnhanced JTAG (EJTAG) interface for use in thesoftware debug of application and kernel code. Inaddition to standard User mode and Kernel modes ofoperation, the MIPS® M4K® core provides a Debugmode that is entered after a debug exception (derivedfrom a hardware breakpoint, single-step exception,etc.) is taken and continues until a Debug ExceptionReturn (DERET) instruction is executed. During thistime, the processor executes the debug exceptionhandler routine.
The EJTAG interface operates through the Test AccessPort (TAP), a serial communication port used fortransferring test data in and out of the MIPS® M4K®
processor core. In addition to the standard JTAGinstructions, special instructions defined in the EJTAGspecification define which registers are selected andhow they are used.
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PIC32MX5XX/6XX/7XX
NOTES:
DS60001156H-page 54 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
4.0 MEMORY ORGANIZATION
PIC32MX5XX/6XX/7XX microcontrollers provide 4 GBof unified virtual memory address space. All memoryregions, including program, data memory, SFRs andConfiguration registers, reside in this address space attheir respective unique addresses. The program anddata memories can be optionally partitioned into userand kernel memories. In addition, the data memory canbe made executable, allowing PIC32MX5XX/6XX/7XXdevices to execute from data memory.
Key features include:
• 32-bit native data width
• Separate User (KUSEG) and Kernel (KSEG0/KSEG1) mode address space
• Flexible program Flash memory partitioning
• Flexible data RAM partitioning for data and program space
• Separate boot Flash memory for protected code
• Robust bus exception handling to intercept runaway code
• Simple memory mapping with Fixed Mapping Translation (FMT) unit
• Cacheable (KSEG0) and non-cacheable (KSEG1) address regions
4.1 Memory Layout
PIC32MX5XX/6XX/7XX microcontrollers implementtwo address schemes: virtual and physical. Allhardware resources, such as program memory, datamemory and peripherals, are located at their respectivephysical addresses. Virtual addresses are exclusivelyused by the CPU to fetch and execute instructions aswell as access peripherals. Physical addresses areused by bus master peripherals, such as DMA and theFlash controller, that access memory independently ofthe CPU.
The memory maps for the PIC32MX5XX/6XX/7XXdevices are illustrated in Figure 4-1 through Figure 4-6.
4.1.1 PERIPHERAL REGISTERS LOCATIONS
Table 4-1 through Table 4-44 contain the peripheraladdress maps for the PIC32MX5XX/6XX/7XXdevices.
Note: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Fordetailed information, refer to Section 3.“Memory Organization” (DS60001115)in the “PIC32 Family Reference Manual”,which is available from the Microchipweb site (www.microchip.com/PIC32).
2009-2013 Microchip Technology Inc. DS60001156H-page 55
FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX564F064H, PIC32MX564F064L, PIC32MX664F064H AND PIC32MX664F064L DEVICES
VirtualMemory Map(1)
Physical Memory Map(1)
0xFFFFFFFFReserved
Reserved
0xFFFFFFFF
0xBFC03000
0xBFC02FFF Device Configuration
Registers0xBFC02FF0
0xBFC02FEF
Boot Flash
0xBFC00000
Reserved0xBF900000
0xBF8FFFFF
SFRs
0xBF800000
Reserved0xBD010000
0xBD00FFFF
Program Flash(2)
0xBD000000
Reserved0xA0008000
0xA0007FFF
RAM(2)
0xA0000000 0x1FC03000
Reserved DeviceConfiguration
Registers
0x1FC02FFF
0x9FC03000
0x9FC02FFF DeviceConfiguration
Registers
0x1FC02FF0
Boot Flash
0x1FC02FEF
0x9FC02FF0
0x9FC02FEF
Boot Flash
0x1FC00000
Reserved0x9FC00000 0x1F900000
Reserved SFRs
0x1F8FFFFF
0x9D010000 0x1F800000
0x9D00FFFF
Program Flash(2) Reserved
0x9D000000 0x1D010000
ReservedProgram Flash(2)
0x1D00FFFF
0x80008000
0x80007FFF
RAM(2)0x1D000000
Reserved0x80000000 0x00008000
Reserved RAM(2) 0x00007FFF
0x00000000 0x00000000
Note 1: Memory areas are not shown to scale.
2: The size of this memory region is programmable (see Section 3. “Memory Organization”(DS60001115)) and can be changed by initialization code provided by end userdevelopment tools (refer to the specific development tool documentation for information).
KS
EG
1K
SE
G0
DS60001156H-page 56 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX534F064H AND PIC32MX534F064L DEVICES
VirtualMemory Map(1)
Physical Memory Map(1)
0xFFFFFFFFReserved
Reserved
0xFFFFFFFF
0xBFC03000
0xBFC02FFF Device Configuration
Registers0xBFC02FF0
0xBFC02FEF
Boot Flash
0xBFC00000
Reserved0xBF900000
0xBF8FFFFF
SFRs
0xBF800000
Reserved0xBD010000
0xBD00FFFF
Program Flash(2)
0xBD000000
Reserved0xA0004000
0xA0003FFF
RAM(2)
0xA0000000 0x1FC03000
Reserved DeviceConfiguration
Registers
0x1FC02FFF
0x9FC03000
0x9FC02FFF DeviceConfiguration
Registers
0x1FC02FF0
Boot Flash
0x1FC02FEF
0x9FC02FF0
0x9FC02FEF
Boot Flash
0x1FC00000
Reserved0x9FC00000 0x1F900000
Reserved SFRs
0x1F8FFFFF
0x9D010000 0x1F800000
0x9D00FFFF
Program Flash(2) Reserved
0x9D000000 0x1D010000
ReservedProgram Flash(2)
0x1D00FFFF
0x80004000
0x80003FFF
RAM(2)0x1D000000
Reserved0x80000000 0x00004000
Reserved RAM(2) 0x00003FFF
0x00000000 0x00000000
Note 1: Memory areas are not shown to scale.
2: The size of this memory region is programmable (see Section 3. “Memory Organization”(DS60001115)) and can be changed by initialization code provided by end userdevelopment tools (refer to the specific development tool documentation for information).
KS
EG
1K
SE
G0
2009-2013 Microchip Technology Inc. DS60001156H-page 57
PIC32MX5XX/6XX/7XX
FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX564F128H, PIC32MX564F128L, PIC32MX664F128H, PIC32MX664F128L, PIC32MX764F128H AND PIC32MX764F128L DEVICES
VirtualMemory Map(1)
Physical Memory Map(1)
0xFFFFFFFFReserved
Reserved
0xFFFFFFFF
0xBFC03000
0xBFC02FFF Device Configuration
Registers0xBFC02FF0
0xBFC02FEF
Boot Flash
0xBFC00000
Reserved0xBF900000
0xBF8FFFFF
SFRs
0xBF800000
Reserved0xBD020000
0xBD01FFFF
Program Flash(2)
0xBD000000
Reserved0xA0008000
0xA0007FFF
RAM(2)
0xA0000000 0x1FC03000
Reserved DeviceConfiguration
Registers
0x1FC02FFF
0x9FC03000
0x9FC02FFF DeviceConfiguration
Registers
0x1FC02FF0
Boot Flash
0x1FC02FEF
0x9FC02FF0
0x9FC02FEF
Boot Flash
0x1FC00000
Reserved0x9FC00000 0x1F900000
Reserved SFRs
0x1F8FFFFF
0x9D020000 0x1F800000
0x9D01FFFF
Program Flash(2) Reserved
0x9D000000 0x1D020000
ReservedProgram Flash(2)
0x1D01FFFF
0x80008000
0x80007FFF
RAM(2)0x1D000000
Reserved0x80000000 0x00008000
Reserved RAM(2) 0x00007FFF
0x00000000 0x00000000
Note 1: Memory areas are not shown to scale.
2: The size of this memory region is programmable (see Section 3. “Memory Organization”(DS60001115)) and can be changed by initialization code provided by end userdevelopment tools (refer to the specific development tool documentation for information).
KS
EG
1K
SE
G0
DS60001156H-page 58 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 4-4: MEMORY MAP ON RESET FOR PIC32MX575F256H, PIC32MX575F256L, PIC32MX675F256H, PIC32MX675F256L, PIC32MX775F256H AND PIC32MX775F256L DEVICES
VirtualMemory Map(1)
Physical Memory Map(1)
0xFFFFFFFFReserved
Reserved
0xFFFFFFFF
0xBFC03000
0xBFC02FFF Device Configuration
Registers0xBFC02FF0
0xBFC02FEF
Boot Flash
0xBFC00000
Reserved0xBF900000
0xBF8FFFFF
SFRs
0xBF800000
Reserved0xBD040000
0xBD03FFFF
Program Flash(2)
0xBD000000
Reserved0xA0010000
0xA000FFFF
RAM(2)
0xA0000000 0x1FC03000
Reserved DeviceConfiguration
Registers
0x1FC02FFF
0x9FC03000
0x9FC02FFF DeviceConfiguration
Registers
0x1FC02FF0
Boot Flash
0x1FC02FEF
0x9FC02FF0
0x9FC02FEF
Boot Flash
0x1FC00000
Reserved0x9FC00000 0x1F900000
Reserved SFRs
0x1F8FFFFF
0x9D040000 0x1F800000
0x9D03FFFF
Program Flash(2) Reserved
0x9D000000 0x1D040000
ReservedProgram Flash(2)
0x1D03FFFF
0x80008000
0x80007FFF
RAM(2)0x1D000000
Reserved0x80000000 0x00010000
Reserved RAM(2) 0x0000FFFF
0x00000000 0x00000000
Note 1: Memory areas are not shown to scale.
2: The size of this memory region is programmable (see Section 3. “Memory Organization”(DS60001115)) and can be changed by initialization code provided by end userdevelopment tools (refer to the specific development tool documentation for information).
KS
EG
1K
SE
G0
2009-2013 Microchip Technology Inc. DS60001156H-page 59
PIC32MX5XX/6XX/7XX
FIGURE 4-5: MEMORY MAP ON RESET FOR PIC32MX575F512H, PIC32MX575F512L, PIC32MX675F512H, PIC32MX675F512L, PIC32MX775F512H AND PIC32MX775F512L DEVICES
VirtualMemory Map(1)
Physical Memory Map(1)
0xFFFFFFFFReserved
Reserved
0xFFFFFFFF
0xBFC03000
0xBFC02FFF Device Configuration
Registers0xBFC02FF0
0xBFC02FEF
Boot Flash
0xBFC00000
Reserved0xBF900000
0xBF8FFFFF
SFRs
0xBF800000
Reserved0xBD080000
0xBD07FFFF
Program Flash(2)
0xBD000000
Reserved0xA0010000
0xA000FFFF
RAM(2)
0xA0000000 0x1FC03000
Reserved DeviceConfiguration
Registers
0x1FC02FFF
0x9FC03000
0x9FC02FFF DeviceConfiguration
Registers
0x1FC02FF0
Boot Flash
0x1FC02FEF
0x9FC02FF0
0x9FC02FEF
Boot Flash
0x1FC00000
Reserved0x9FC00000 0x1F900000
Reserved SFRs
0x1F8FFFFF
0x9D080000 0x1F800000
0x9D07FFFF
Program Flash(2) Reserved
0x9D000000 0x1D080000
ReservedProgram Flash(2)
0x1D07FFFF
0x80010000
0x8000FFFF
RAM(2)0x1D000000
Reserved0x80000000 0x00010000
Reserved RAM(2) 0x0000FFFF
0x00000000 0x00000000
Note 1: Memory areas are not shown to scale.
2: The size of this memory region is programmable (see Section 3. “Memory Organization”(DS60001115)) and can be changed by initialization code provided by end userdevelopment tools (refer to the specific development tool documentation for information).
KS
EG
1K
SE
G0
DS60001156H-page 60 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 4-6: MEMORY MAP ON RESET FOR PIC32MX695F512H, PIC32MX695F512L, PIC32MX795F512H AND PIC32MX795F512L DEVICES
VirtualMemory Map(1)
Physical Memory Map(1)
0xFFFFFFFFReserved
Reserved
0xFFFFFFFF
0xBFC03000
0xBFC02FFF Device Configuration
Registers0xBFC02FF0
0xBFC02FEF
Boot Flash
0xBFC00000
Reserved0xBF900000
0xBF8FFFFF
SFRs
0xBF800000
Reserved0xBD080000
0xBD07FFFF
Program Flash(2)
0xBD000000
Reserved0xA0020000
0xA001FFFF
RAM(2)
0xA0000000 0x1FC03000
Reserved DeviceConfiguration
Registers
0x1FC02FFF
0x9FC03000
0x9FC02FFF DeviceConfiguration
Registers
0x1FC02FF0
Boot Flash
0x1FC02FEF
0x9FC02FF0
0x9FC02FEF
Boot Flash
0x1FC00000
Reserved0x9FC00000 0x1F900000
Reserved SFRs
0x1F8FFFFF
0x9D080000 0x1F800000
0x9D07FFFF
Program Flash(2) Reserved
0x9D000000 0x1D080000
ReservedProgram Flash(2)
0x1D07FFFF
0x80020000
0x8001FFFF
RAM(2)0x1D000000
Reserved0x80000000 0x00020000
Reserved RAM(2) 0x0001FFFF
0x00000000 0x00000000
Note 1: Memory areas are not shown to scale.
2: The size of this memory region is programmable (see Section 3. “Memory Organization”(DS60001115)) and can be changed by initialization code provided by end userdevelopment tools (refer to the specific development tool documentation for information).
KS
EG
1K
SE
G0
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32MX
5XX
/6XX
/7XX
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All
Res
ets
19/3 18/2 17/1 16/0
BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F
— BMXARB<2:0> 0041
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
xxxx
xxxx
BMXPUPBA<19:16> 0000
0000
xxxx
xxxx
0000
3000
n 12.1.1 “CLR, SET and INV Registers” for more information.
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Sectio
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-2013 Microchip T
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5XX
/6XX
/7XX
T 128H, PIC32MX575F256H AND
All
Res
ets
20/4 19/3 18/2 17/1 16/0
— — — — SS0 0000
NT4EP INT3EP INT2EP INT1EP INT0EP 0000
— — — — — 0000
VEC<5:0> 0000
0000
0000
T5IF INT4IF OC4IF IC4IF T4IF 0000
T1IF INT0IF CS1IF CS0IF CTIF 0000
MA4IF(2) DMA3IF DMA2IF DMA1IF DMA0IF 0000
MP2IF CMP1IF PMPIF AD1IF CNIF 0000
— — — — — 0000
4RXIF U4EIF PMPEIF IC5EIF IC4EIF 0000
T5IE INT4IE OC4IE IC4IE T4IE 0000
T1IE INT0IE CS1IE CS0IE CTIE 0000
MA4IE(2) DMA3IE DMA2IE DMA1IE DMA0IE 0000
MP2IE CMP1IE PMPIE AD1IE CNIE 0000
— — — — — 0000
4RXIE U4EIE PMPEIE IC5EIE IC4EIE 0000
CS1IP<2:0> CS1IS<1:0> 0000
CTIP<2:0> CTIS<1:0> 0000
OC1IP<2:0> OC1IS<1:0> 0000
T1IP<2:0> T1IS<1:0> 0000
and 0xC, respectively. See Section 12.1.1 “CLR, SET
ABLE 4-2: INTERRUPT REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564FPIC32MX575F512H DEVICES
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8and INV Registers” for more information.
2: These bits are not available on PIC32MX534/564/664/764 devices.3: This register does not have associated CLR, SET, and INV registers.
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5XX
/6XX
/7XX
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OC2IP<2:0> OC2IS<1:0> 0000
T2IP<2:0> T2IS<1:0> 0000
OC3IP<2:0> OC3IS<1:0> 0000
T3IP<2:0> T3IS<1:0> 0000
OC4IP<2:0> OC4IS<1:0> 0000
T4IP<2:0> T4IS<1:0> 0000
OC5IP<2:0> OC5IS<1:0> 0000
T5IP<2:0> T5IS<1:0> 0000
CNIP<2:0> CNIS<1:0> 0000
U1IP<2:0> U1IS<1:0>
0000SPI3IP<2:0> SPI3IS<1:0>
I2C3IP<2:0> I2C3IS<1:0>
CMP2IP<2:0> CMP2IS<1:0> 0000
PMPIP<2:0> PMPIS<1:0> 0000
FSCMIP<2:0> FSCMIS<1:0> 0000
U2IP<2:0> U2IS<1:0>
0000SPI4IP<2:0> SPI4IS<1:0>
I2C5IP<2:0> I2C5IS<1:0>
DMA2IP<2:0> DMA2IS<1:0> 0000
DMA0IP<2:0> DMA0IS<1:0> 0000
DMA6IP<2:0>(2) DMA6IS<1:0>(2) 0000
DMA4IP<2:0>(2) DMA4IS<1:0>(2) 0000
CAN1IP<2:0> CAN1IS<1:0> 0000
FCEIP<2:0> FCEIS<1:0> 0000
U6IP<2:0> U6IS<1:0> 0000
— — — — — 0000
64F128H, PIC32MX575F256H AND
All
Res
ets
20/4 19/3 18/2 17/1 16/0
4 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0xand INV Registers” for more information.
2: These bits are not available on PIC32MX534/564/664/764 devices.3: This register does not have associated CLR, SET, and INV registers.
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC reRegisters” for more information.
2: These bits are not available on PIC32MX664 devices.3: This register does not have associated CLR, SET, and INV registers.
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/6XX
/7XX
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OC4IP<2:0> OC4IS<1:0> 0000
T4IP<2:0> T4IS<1:0> 0000
OC5IP<2:0> OC5IS<1:0> 0000
T5IP<2:0> T5IS<1:0> 0000
CNIP<2:0> CNIS<1:0> 0000
U1IP<2:0> U1IS<1:0>
0000SPI3IP<2:0> SPI3IS<1:0>
I2C3IP<2:0> I2C3IS<1:0>
CMP2IP<2:0> CMP2IS<1:0> 0000
PMPIP<2:0> PMPIS<1:0> 0000
FSCMIP<2:0> FSCMIS<1:0> 0000
U2IP<2:0> U2IS<1:0>
0000SPI4IP<2:0> SPI4IS<1:0>
I2C5IP<2:0> I2C5IS<1:0>
DMA2IP<2:0> DMA2IS<1:0> 0000
DMA0IP<2:0> DMA0IS<1:0> 0000
DMA6IP<2:0>(2) DMA6IS<1:0>(2) 0000
DMA4IP<2:0>(2) DMA4IS<1:0>(2) 0000
— — — — — 0000
FCEIP<2:0> FCEIS<1:0> 0000
U6IP<2:0> U6IS<1:0> 0000
ETHIP<2:0> ETHIS<1:0> 0000
75F256H, PIC32MX675F512H AND
All
Res
ets
20/4 19/3 18/2 17/1 16/0
0xC respectively. See Section 12.1.1 “CLR, SET and INV
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and Registers” for more information.
2: These bits are not available on PIC32MX664 devices.3: This register does not have associated CLR, SET, and INV registers.
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, rRegisters” for more information.
2: This bit is unimplemented on PIC32MX764F128H device.3: This register does not have associated CLR, SET, and INV registers.
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/6XX
/7XX
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OC4IP<2:0> OC4IS<1:0> 0000
T4IP<2:0> T4IS<1:0> 0000
OC5IP<2:0> OC5IS<1:0> 0000
T5IP<2:0> T5IS<1:0> 0000
CNIP<2:0> CNIS<1:0> 0000
U1IP<2:0> U1IS<1:0>
0000SPI3IP<2:0> SPI3IS<1:0>
I2C3IP<2:0> I2C3IS<1:0>
CMP2IP<2:0> CMP2IS<1:0> 0000
PMPIP<2:0> PMPIS<1:0> 0000
FSCMIP<2:0> FSCMIS<1:0> 0000
U2IP<2:0> U2IS<1:0>
0000SPI4IP<2:0> SPI4IS<1:0>
I2C5IP<2:0> I2C5IS<1:0>
DMA2IP<2:0> DMA2IS<1:0> 0000
DMA0IP<2:0> DMA0IS<1:0> 0000
DMA6IP<2:0>(2) DMA6IS<1:0>(2) 0000
DMA4IP<2:0>(2) DMA4IS<1:0>(2) 0000
CAN1IP<2:0> CAN1IS<1:0> 0000
FCEIP<2:0> FCEIS<1:0> 0000
U6IP<2:0> U6IS<1:0> 0000
ETHIP<2:0> ETHIS<1:0> 0000
75F512H AND
All
Re
sets
20/4 19/3 18/2 17/1 16/0
0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and Registers” for more information.
2: This bit is unimplemented on PIC32MX764F128H device.3: This register does not have associated CLR, SET, and INV registers.
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32MX
5XX
/6XX
/7XX
T 128L PIC32MX575F512L AND
All
Re
sets
4 19/3 18/2 17/1 16/0
— — — SS0 0000
EP INT3EP INT2EP INT1EP INT0EP 0000
— — — — 0000
VEC<5:0> 0000
0000
0000
F INT4IF OC4IF IC4IF T4IF 0000
F INT0IF CS1IF CS0IF CTIF 0000
IF(2) DMA3IF DMA2IF DMA1IF DMA0IF 0000
IF CMP1IF PMPIF AD1IF CNIF 0000
— — — — 0000
IF U4EIF PMPEIF IC5EIF IC4EIF 0000
INT4IE OC4IE IC4IE T4IE 0000
INT0IE CS1IE CS0IE CTIE 0000
IE(2) DMA3IE DMA2IE DMA1IE DMA0IE 0000
IE CMP1IE PMPIE AD1IE CNIE 0000
— — — — 0000
IE U4EIE PMPEIE IC5EIE IC4EIE 0000
CS1IP<2:0> CS1IS<1:0> 0000
CTIP<2:0> CTIS<1:0> 0000
OC1IP<2:0> OC1IS<1:0> 0000
T1IP<2:0> T1IS<1:0> 0000
OC2IP<2:0> OC2IS<1:0> 0000
T2IP<2:0> T2IS<1:0> 0000
OC3IP<2:0> OC3IS<1:0> 0000
T3IP<2:0> T3IS<1:0> 0000
L
N espectively. See Section 12.1.1 “CLR, SET and INV
ABLE 4-5: INTERRUPT REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564FPIC32MX575F256L DEVICES
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, rRegisters” for more information.
2: These bits are not available on PIC32MX534/564 devices.3: This register does not have associated CLR, SET, and INV registers.
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/6XX
/7XX
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OC4IP<2:0> OC4IS<1:0> 0000
T4IP<2:0> T4IS<1:0> 0000
OC5IP<2:0> OC5IS<1:0> 0000
T5IP<2:0> T5IS<1:0> 0000
CNIP<2:0> CNIS<1:0> 0000
U1IP<2:0> U1IS<1:0>
0000SPI3IP<2:0> SPI3IS<1:0>
I2C3IP<2:0> I2C3IS<1:0>
CMP2IP<2:0> CMP2IS<1:0> 0000
PMPIP<2:0> PMPIS<1:0> 0000
FSCMIP<2:0> FSCMIS<1:0> 0000
U2IP<2:0> U2IS<1:0>
0000SPI4IP<2:0> SPI4IS<1:0>
I2C5IP<2:0> I2C5IS<1:0>
DMA2IP<2:0> DMA2IS<1:0> 0000
DMA0IP<2:0> DMA0IS<1:0> 0000
DMA6IP<2:0>(2) DMA6IS<1:0>(2) 0000
DMA4IP<2:0>(2) DMA4IS<1:0>(2) 0000
CAN1IP<2:0> CAN1IS<1:0> 0000
FCEIP<2:0> FCEIS<1:0> 0000
U6IP<2:0> U6IS<1:0> 0000
— — — — — 0000
64F128L PIC32MX575F512L AND
All
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sets
20/4 19/3 18/2 17/1 16/0
0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and Registers” for more information.
2: These bits are not available on PIC32MX534/564 devices.3: This register does not have associated CLR, SET, and INV registers.
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, rRegisters” for more information.
2: These bits are not available on PIC32MX664 devices.3: This register does note have associated CLR, SET, and INV registers.
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5XX
/6XX
/7XX
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OC4IP<2:0> OC4IS<1:0> 0000
T4IP<2:0> T4IS<1:0> 0000
OC5IP<2:0> OC5IS<1:0> 0000
T5IP<2:0> T5IS<1:0> 0000
CNIP<2:0> CNIS<1:0> 0000
U1IP<2:0> U1IS<1:0>
0000SPI3IP<2:0> SPI3IS<1:0>
I2C3IP<2:0> I2C3IS<1:0>
CMP2IP<2:0> CMP2IS<1:0> 0000
PMPIP<2:0> PMPIS<1:0> 0000
FSCMIP<2:0> FSCMIS<1:0> 0000
U2IP<2:0> U2IS<1:0>
0000SPI4IP<2:0> SPI4IS<1:0>
I2C5IP<2:0> I2C5IS<1:0>
DMA2IP<2:0> DMA2IS<1:0> 0000
DMA0IP<2:0> DMA0IS<1:0> 0000
DMA6IP<2:0>(2) DMA6IS<1:0>(2) 0000
DMA4IP<2:0>(2) DMA4IS<1:0>(2) 0000
— — — — — 0000
FCEIP<2:0> FCEIS<1:0> 0000
U6IP<2:0> U6IS<1:0> 0000
ETHIP<2:0> ETHIS<1:0> 0000
75F256L, PIC32MX675F512L AND
All
Re
sets
20/4 19/3 18/2 17/1 16/0
0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and Registers” for more information.
2: These bits are not available on PIC32MX664 devices.3: This register does note have associated CLR, SET, and INV registers.
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, rRegisters” for more information.
2: This bit is unimplemented on PIC32MX764F128L device.3: This register does not have associated CLR, SET, and INV registers.
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5XX
/6XX
/7XX
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OC4IP<2:0> OC4IS<1:0> 0000
T4IP<2:0> T4IS<1:0> 0000
OC5IP<2:0> OC5IS<1:0> 0000
T5IP<2:0> T5IS<1:0> 0000
CNIP<2:0> CNIS<1:0> 0000
U1IP<2:0> U1IS<1:0>
0000SPI3IP<2:0> SPI3IS<1:0>
I2C3IP<2:0> I2C3IS<1:0>
CMP2IP<2:0> CMP2IS<1:0> 0000
PMPIP<2:0> PMPIS<1:0> 0000
FSCMIP<2:0> FSCMIS<1:0> 0000
U2IP<2:0> U2IS<1:0>
0000SPI4IP<2:0> SPI4IS<1:0>
I2C5IP<2:0> I2C5IS<1:0>
DMA2IP<2:0> DMA2IS<1:0> 0000
DMA0IP<2:0> DMA0IS<1:0> 0000
DMA6IP<2:0>(2) DMA6IS<1:0>(2) 0000
DMA4IP<2:0>(2) DMA4IS<1:0>(2) 0000
CAN1IP<2:0> CAN1IS<1:0> 0000
FCEIP<2:0> FCEIS<1:0> 0000
U6IP<2:0> U6IS<1:0> 0000
ETHIP<2:0> ETHIS<1:0> 0000
TABLE 4-7: INTERRUPT REGISTER MAP FOR PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND
All
Re
sets
20/4 19/3 18/2 17/1 16/0
xC, respectively. See Section 12.1.1 “CLR, SET and INV
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0Registers” for more information.
2: This bit is unimplemented on PIC32MX764F128L device.3: This register does not have associated CLR, SET, and INV registers.
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-2013 Microchip T
echnology Inc.
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PIC
32MX
5XX
/6XX
/7XX
T
All
Re
sets
19/3 18/2 17/1 16/0
— — — — 0000
— TSYNC TCS — 0000
— — — — 0000
0000
— — — — 0000
FFFF
— — — — 0000
T32 — TCS(2) — 0000
— — — — 0000
0000
— — — — 0000
FFFF
— — — — 0000
— — TCS(2) — 0000
— — — — 0000
0000
— — — — 0000
FFFF
— — — — 0000
T32 — TCS(2) — 0000
— — — — 0000
0000
— — — — 0000
FFFF
— — — — 0000
— — TCS(2) — 0000
— — — — 0000
0000
— — — — 0000
FFFF
L
N tion 12.1.1 “CLR, SET and INV Registers” for more
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Secinformation.
2: These bits are not available on 64-pin devices.
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “
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-2013 Microchip T
echnology Inc.
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PIC
32MX
5XX
/6XX
/7XX
T
All
Re
sets
19/3 18/2 17/1 16/0
— — — — 0000
OCTSEL OCM<2:0> 0000
xxxx
xxxx
xxxx
xxxx
— — — — 0000
OCTSEL OCM<2:0> 0000
xxxx
xxxx
xxxx
xxxx
— — — — 0000
OCTSEL OCM<2:0> 0000
xxxx
xxxx
xxxx
xxxx
— — — — 0000
OCTSEL OCM<2:0> 0000
xxxx
xxxx
xxxx
xxxx
— — — — 0000
OCTSEL OCM<2:0> 0000
xxxx
xxxx
xxxx
xxxx
L
N tion 12.1.1 “CLR, SET and INV Registers” for more
ABLE 4-10: OUTPUT COMPARE 1-OUTPUT COMPARE 5 REGISTER MAPV
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Secinformation.
PIC
32MX
5XX
/6XX
/7XX
DS
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All
Re
sets
20/4 19/3 18/2 17/1 16/0
— — — — — 0000
ACKEN RCEN PEN RSEN SEN 1000
— — — — — 0000
P S R/W RBF TBF 0000
— — — — — 0000
:0> 0000
— — — — — 0000
:0> 0000
— — — — — 0000
r 0000
— — — — — 0000
Transmit Register 0000
— — — — — 0000
Receive Register 0000
— — — — — 0000
ACKEN RCEN PEN RSEN SEN 1000
— — — — — 0000
P S R/W RBF TBF 0000
— — — — — 0000
:0> 0000
— — — — — 0000
:0> 0000
— — — — — 0000
r 0000
— — — — — 0000
Transmit Register 0000
— — — — — 0000
Receive Register 0000
— — — — — 0000
ACKEN RCEN PEN RSEN SEN 1000
— — — — — 0000
P S R/W RBF TBF 0000
respectively. See Section 12.1.1 “CLR, SET and INV Registers”
TABLE 4-11: I2C1, I2C3, I2C4 AND I2C5 REGISTER MAPV
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC,for more information.
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-2013 Microchip T
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PIC
32MX
5XX
/6XX
/7XX
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
mit Register 0000
— — — — 0000
ive Register 0000
— — — — 0000
N RCEN PEN RSEN SEN 1000
— — — — 0000
S R/W RBF TBF 0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
mit Register 0000
— — — — 0000
ive Register 0000
T
All
Re
sets
19/3 18/2 17/1 16/0
L
N ctively. See Section 12.1.1 “CLR, SET and INV Registers”
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respefor more information.
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC,for more information.
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CL
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5XX
/6XX
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— — — — — 0000
Receive Register 0000
— — — — — 0000
0000
— — — — — 0000
RXINV BRGH PDSEL<1:0> STSEL 0000
ADDR<7:0> 0000
RIDLE PERR FERR OERR URXDA 0110
— — — — — 0000
Transmit Register 0000
— — — — — 0000
Receive Register 0000
— — — — — 0000
0000
— — — — — 0000
RXINV BRGH PDSEL<1:0> STSEL 0000
ADDR<7:0> 0000
RIDLE PERR FERR OERR URXDA 0110
— — — — — 0000
Transmit Register 0000
— — — — — 0000
Receive Register 0000
— — — — — 0000
0000
All
Re
sets
20/4 19/3 18/2 17/1 16/0
.1 “CLR, SET and INV Registers” for more information.
6630 U6RXREG31:16 — — — — — — — — — — —
15:0 — — — — — — — RX8
6640 U6BRG(1) 31:16 — — — — — — — — — — —
15:0 BRG<15:0>
6800 U2MODE(1) 31:16 — — — — — — — — — — —
15:0 ON — SIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1
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PIC
32MX
5XX
/6XX
/7XX
T
All
Re
sets
19/3 18/2 17/1 16/0
— — SPIFE ENHBUF 0000
STXISEL<1:0> SRXISEL<1:0> 0000
TXBUFELM<4:0> 0000
SPITBE — SPITBF SPIRBF 0008
0000
0000
— — — — 0000
0> 0000
— — SPIFE ENHBUF 0000
STXISEL<1:0> SRXISEL<1:0> 0000
TXBUFELM<4:0> 0000
SPITBE — SPITBF SPIRBF 0008
0000
0000
— — — — 0000
0> 0000
— — SPIFE ENHBUF 0000
STXISEL<1:0> SRXISEL<1:0> 0000
TXBUFELM<4:0> 0000
SPITBE — SPITBF SPIRBF 0008
0000
0000
— — — — 0000
0> 0000
L
N ctively. See Section 12.1.1 “CLR, SET and INV Registers”
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respefor more information.
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table except SPI1BUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC,for more information.
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-2013 Microchip T
echnology Inc.
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PIC
32MX
5XX
/6XX
/7XX
T
All
Re
sets
19/3 18/2 17/1 16/0
— — — — 0000
M — ASAM SAMP DONE 0000
— — — — 0000
PI<3:0> BUFM ALTS 0000
— — — — 0000
CS<7:0> 0000
CH0SA<3:0> 0000
— — — — 0000
— — — — 0000
4 PCFG3 PCFG2 PCFG1 PCFG0 0000
— — — — 0000
CSSL3 CSSL2 CSSL1 CSSL0 0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
L
N LR, SET and INV Registers” for more information.
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “C
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32MX
5XX
/6XX
/7XX
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0000
0000
0000
0000
0000
0000
0000
0000
All
Re
sets
20/4 19/3 18/2 17/1 16/0
.1.1 “CLR, SET and INV Registers” for more information.
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12
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PIC
32MX
5XX
/6XX
/7XX
T
All
Re
sets
19/3 18/2 17/1 16/0
— — — — 0000
— — — — 0000
— — — — 0000
RDWR DMACH<2:0>(2) 0000
0000
0000
L
N R, SET and INV Registers” for more information.
T
All
Re
set
s
19/3 18/2 17/1 16/0
— — — — 0000
— CRCCH<2:0> 0000
0000
0000
0000
0000
L
N tion 12.1.1 “CLR, SET and INV Registers” for more
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CL2: DMACH<3> bit is not available on PIC32MX534/564/664/764 devices.
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Secinformation.
PIC
32MX
5XX
/6XX
/7XX
DS
60001156H
-page 88
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icrochip Technolo
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All
Re
sets
20/4 19/3 18/2 17/1 16/0
— — — — — 0000
CHAEN — CHEDET CHPRI<1:0> 0000
CHAIRQ<7:0> 00FF
IRQEN AIRQEN — — — FF00
HDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
0000
0000
0000
0000
— — — — — 0000
0000
— — — — — 0000
0000
— — — — — 0000
0000
— — — — — 0000
0000
— — — — — 0000
0000
— — — — — 0000
0000
— — — — — 0000
CHPDAT<7:0> 0000
— — — — — 0000
CHAEN — CHEDET CHPRI<1:0> 0000
CHAIRQ<7:0> 00FF
IRQEN AIRQEN — — — FF00
HDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
0000
0000
0000
0000
— — — — — 0000
0000
e Section 12.1.1 “CLR, SET and INV Registers” for more
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. Seinformation.
2: DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices.
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-2013 Microchip T
echnology Inc.
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PIC
32MX
5XX
/6XX
/7XX
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
DAT<7:0> 0000
— — — — 0000
N — CHEDET CHPRI<1:0> 0000
AIRQ<7:0> 00FF
N AIRQEN — — — FF00
IE CHBCIE CHCCIE CHTAIE CHERIE 0000
IF CHBCIF CHCCIF CHTAIF CHERIF 0000
0000
0000
0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
T
All
Re
sets
19/3 18/2 17/1 16/0
L
N tion 12.1.1 “CLR, SET and INV Registers” for more
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Secinformation.
2: DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices.
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5XX
/6XX
/7XX
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— — — — — 0000
CHPDAT<7:0> 0000
— — — — — 0000
CHAEN — CHEDET CHPRI<1:0> 0000
CHAIRQ<7:0> 00FF
IRQEN AIRQEN — — — FF00
HDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
0000
0000
0000
0000
— — — — — 0000
0000
— — — — — 0000
0000
— — — — — 0000
0000
— — — — — 0000
0000
— — — — — 0000
0000
— — — — — 0000
0000
— — — — — 0000
CHPDAT<7:0> 0000
— — — — — 0000
CHAEN — CHEDET CHPRI<1:0> 0000
CHAIRQ<7:0> 00FF
IRQEN AIRQEN — — — FF00
HDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
0000
0000
0000
0000
All
Re
sets
20/4 19/3 18/2 17/1 16/0
e Section 12.1.1 “CLR, SET and INV Registers” for more
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. Seinformation.
2: DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices.
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-2013 Microchip T
echnology Inc.
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PIC
32MX
5XX
/6XX
/7XX
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
DAT<7:0> 0000
— — — — 0000
N — CHEDET CHPRI<1:0> 0000
AIRQ<7:0> 00FF
N AIRQEN — — — FF00
IE CHBCIE CHCCIE CHTAIE CHERIE 0000
IF CHBCIF CHCCIF CHTAIF CHERIF 0000
0000
0000
0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
T
All
Re
sets
19/3 18/2 17/1 16/0
L
N tion 12.1.1 “CLR, SET and INV Registers” for more
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Secinformation.
2: DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices.
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/6XX
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— — — — — 0000
CHPDAT<7:0> 0000
— — — — — 0000
CHAEN — CHEDET CHPRI<1:0> 0000
CHAIRQ<7:0> 00FF
IRQEN AIRQEN — — — FF00
HDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
0000
0000
0000
0000
— — — — — 0000
0000
— — — — — 0000
0000
— — — — — 0000
0000
— — — — — 0000
0000
— — — — — 0000
0000
— — — — — 0000
0000
— — — — — 0000
CHPDAT<7:0> 0000
— — — — — 0000
CHAEN — CHEDET CHPRI<1:0> 0000
CHAIRQ<7:0> 00FF
IRQEN AIRQEN — — — FF00
HDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
0000
0000
0000
0000
All
Re
sets
20/4 19/3 18/2 17/1 16/0
e Section 12.1.1 “CLR, SET and INV Registers” for more
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. Seinformation.
2: DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices.
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-2013 Microchip T
echnology Inc.
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32MX
5XX
/6XX
/7XX
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
DAT<7:0> 0000
T
All
Re
sets
19/3 18/2 17/1 16/0
L
N tion 12.1.1 “CLR, SET and INV Registers” for more
35F0 DCH7SSIZ31:16 — — — — — — — — — — — —
15:0 CHSSIZ<15:0>
3600 DCH7DSIZ31:16 — — — — — — — — — — — —
15:0 CHDSIZ<15:0>
3610 DCH7SPTR31:16 — — — — — — — — — — — —
15:0 CHSPTR<15:0>
3620 DCH7DPTR31:16 — — — — — — — — — — — —
15:0 CHDPTR<15:0>
3630 DCH7CSIZ31:16 — — — — — — — — — — — —
15:0 CHCSIZ<15:0>
3640 DCH7CPTR31:16 — — — — — — — — — — — —
15:0 CHCPTR<15:0>
3650 DCH7DAT31:16 — — — — — — — — — — — —
15:0 — — — — — — — — CHP
ABLE 4-19: DMA CHANNELS 0-7 REGISTER MAP (CONTINUED)V
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Secinformation.
2: DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices.
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32MX
5XX
/6XX
/7XX
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All
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sets
20/4 19/3 18/2 17/1 16/0
— — — — — 0000
CREF — — CCH<1:0> 00C3
— — — — — 0000
CREF — — CCH<1:0> 00C3
— — — — — 0000
— — — C2OUT C1OUT 0000
ctively. See Section 12.1.1 “CLR, SET and INV Registers”
All
Re
set
s
20/4 19/3 18/2 17/1 16/0
— — — — — 0000
CVRSS CVR<3:0> 0100
ctively. See Section 12.1.1 “CLR, SET and INV Registers”
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respefor more information.
TABLE 4-21: COMPARATOR VOLTAGE REFERENCE REGISTER MAP
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respefor more information.
2: These bits are not available on PIC32MX575/675/695/775/795 devices. On these devices, reset value for CVRCON is ‘0000’.
2009
-2013 Microchip T
echnology Inc.
DS
60001156H
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PIC
32MX
5XX
/6XX
/7XX
T
All
Re
sets
19/3 18/2 17/1 16/0
— — — — 0000
NVMOP<3:0> 0000
0000
0000
0000
0000
0000
0000
0000
0000
L
N LR, SET and INV Registers” for more information.
T
All
Re
se
ts(2
)
19/3 18/2 17/1 16/0
DIV<1:0> PLLMULT<2:0> 0000
CF UFRCEN SOSCEN OSWEN 0000
— — — — 0000
TUN<5:0> 0000
— — — — 0000
4:0> — WDTCLR 0000
— — — — 0000
SLEEP IDLE BOR POR 0000
— — — — 0000
— — — SWRST 0000
0000
0000
L
N tion 12.1.1 “CLR, SET and INV Registers” for more
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “C
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Secinformation.
2: Reset values are dependent on the DEVCFGx Configuration bits and the type of Reset.
e Section 12.1.1 “CLR, SET and INV Registers” for more
All
Res
ets
0/4 19/3 18/2 17/1 16/0
— — — — — 0000
ISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF
— — — — — 0000
RB4 RB3 RB2 RB1 RB0 xxxx
— — — — — 0000
ATB4 LATB3 LATB2 LATB1 LATB0 xxxx
— — — — — 0000
DCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000
e Section 12.1.1 “CLR, SET and INV Registers” for more
TABLE 4-24: PORTA REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F1PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC3PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L D
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. Seinformation.
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. Seinformation.
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-2013 Microchip T
echnology Inc.
DS
60001156H
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PIC
32MX
5XX
/6XX
/7XX
T , PIC32MX575F256H, X675F512H, PIC32MX695F512H, ICES
All
Re
sets
19/3 18/2 17/1 16/0
— — — — 0000
— — — — F000
— — — — 0000
— — — — xxxx
— — — — 0000
— — — — xxxx
— — — — 0000
— — — — 0000
L
N tion 12.1.1 “CLR, SET and INV Registers” for more
T , PIC32MX575F256L, 675F512L, PIC32MX695F512L, CES
All
Res
ets
19/3 18/2 17/1 16/0
— — — — 0000
TRISC3 TRISC2 TRISC1 — F00F
— — — — 0000
RC3 RC2 RC1 — xxxx
— — — — 0000
LATC3 LATC2 LATC1 — xxxx
— — — — 0000
ODCC3 ODCC2 ODCC1 — 0000
L
N tion 12.1.1 “CLR, SET and INV Registers” for more
ABLE 4-26: PORTC REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128HPIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MPIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEV
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Secinformation.
ABLE 4-27: PORTC REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128LPIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MXPIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVI
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Secinformation.
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. Seinformation.
TABLE 4-29: PORTD REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F1PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC3PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L D
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. Seinformation.
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-2013 Microchip T
echnology Inc.
DS
60001156H
-page 99
PIC
32MX
5XX
/6XX
/7XX
T , PIC32MX575F256H, X675F512H, PIC32MX695F512H,
All
Re
sets
19/3 18/2 17/1 16/0
— — — — 0000
TRISE3 TRISE2 TRISE1 TRISE0 00FF
— — — — 0000
RE3 RE2 RE1 RE0 xxxx
— — — — 0000
LATE3 LATE2 LATE1 LATE0 xxxx
— — — — 0000
ODCE3 ODCE2 ODCE1 ODCE0 0000
L
N tion 12.1.1 “CLR, SET and INV Registers” for more
T , PIC32MX575F256L, 675F512L, PIC32MX695F512L, CES
All
Res
ets
19/3 18/2 17/1 16/0
— — — — 0000
TRISE3 TRISE2 TRISE1 TRISE0 03FF
— — — — 0000
RE3 RE2 RE1 RE0 xxxx
— — — — 0000
LATE3 LATE2 LATE1 LATE0 xxxx
— — — — 0000
ODCE3 ODCE2 ODCE1 ODCE0 0000
L
N tion 12.1.1 “CLR, SET and INV Registers” for more
ABLE 4-30: PORTE REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128HPIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MPIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Secinformation.
ABLE 4-31: PORTE REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128LPIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MXPIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVI
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Secinformation.
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. Seinformation.
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. Seinformation.
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-2013 Microchip T
echnology Inc.
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PIC
32MX
5XX
/6XX
/7XX
T , PIC32MX575F256H, X675F512H, PIC32MX695F512H, ICES
All
Re
sets
19/3 18/2 17/1 16/0
— — — — 0000
TRISG3 TRISG2 — — 03CC
— — — — 0000
RG3 RG2 — — xxxx
— — — — 0000
LATG3 LATG2 — — xxxx
— — — — 0000
ODCG3 ODCG2 — — 0000
L
N tion 12.1.1 “CLR, SET and INV Registers” for more
T , PIC32MX575F256L, 675F512L, PIC32MX695F512L, CES
All
Res
ets
19/3 18/2 17/1 16/0
— — — — 0000
TRISG3 TRISG2 TRISG1 TRISG0 F3CF
— — — — 0000
RG3 RG2 RG1 RG0 xxxx
— — — — 0000
LATG3 LATG2 LATG1 LATG0 xxxx
— — — — 0000
ODCG3 ODCG2 ODCG1 ODCG0 0000
L
N tion 12.1.1 “CLR, SET and INV Registers” for more
ABLE 4-34: PORTG REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128HPIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MPIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEV
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Secinformation.
ABLE 4-35: PORTG REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128LPIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MXPIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVI
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Secinformation.
e Section 12.1.1 “CLR, SET and INV Registers” for more
TABLE 4-36: CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX534F064L, PIC32MX5PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC3PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512 AND P
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. Seinformation.
TABLE 4-37: CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX575F256H, PIC32MXPIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. Seinformation.
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-2013 Microchip T
echnology Inc.
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PIC
32MX
5XX
/6XX
/7XX
T
All
Re
sets
19/3 18/2 17/1 16/0
— — — — 0000
CS1P — WRSP RDSP 0000
— — — — 0000
ITM<3:0> WAITE<1:0> 0000
— — — — 0000
0000
0000
0000
0000
0000
— — — — 0000
0000
— — — — 0000
OB3E OB2E OB1E OB0E 008F
L
N tion 12.1.1 “CLR, SET and INV Registers” for more
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ote 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Secinformation.
ABLE 4-39: PROGRAMMING AND DIAGNOSTICS REGISTER MAP
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.12: Reset value is dependent on DEVCFGx configuration.
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.ote 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Sectio
information.
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32MX
5XX
/6XX
/7XX
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icrochip Technolo
gy Inc.
All
Re
sets
20/4 19/3 18/2 17/1 16/0
— — FSRSSEL<2:0> xxxx
xxxx
— — FPLLODIV<2:0> xxxx
— FPLLIDIV<2:0> xxxx
WDTPS<4:0> xxxx
— — FNOSC<2:0> xxxx
— PWP<7:4> xxxx
— ICESEL — DEBUG<1:0> xxxx
All
Re
sets
(1)
20/4 19/3 18/2 17/1 16/0
xxxx
xxxx
0) for more information.
TABLE 4-42: DEVCFG: DEVICE CONFIGURATION WORD SUMMARYV
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.Note 1: Reset values are dependent on the device variant. Refer to “PIC32MX5XX/6XX/7XX Family Silicon Errata and Data Sheet Clarification” (DS8000048
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-2013 Microchip T
echnology Inc.
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-page 107
PIC
32MX
5XX
/6XX
/7XX
T
All
Re
sets
19/3 18/2 17/1 16/0
— — — — 0000
SESVDIF SESENDIF — VBUSVDIF 0000
— — — — 0000
SESVDIE SESENDIE — VBUSVDIE 0000
— — — — 0000
SESVD SESEND — VBUSVD 0000
— — — — 0000
N VBUSON OTGEN VBUSCHG VBUSDIS 0000
— — — — 0000
USBBUSY — USUSPEND USBPWR 0000
— — — — 0000
TRNIF SOFIF UERRIFURSTIF 0000
DETACHIF 0000
— — — — 0000
TRNIE SOFIE UERRIEURSTIE 0000
DETACHIE 0000
— — — — 0000
DFN8EF CRC16EFCRC5EF
PIDEF0000
EOFEF 0000
— — — — 0000
DFN8EE CRC16EECRC5EE
PIDEE0000
EOFEE 0000
— — — — 0000
DIR PPBI — — 0000
— — — — 0000
HOSTEN RESUME PPBRSTUSBEN 0000
SOFEN 0000
— — — — 0000
EVADDR<6:0> 0000
— — — — 0000
1> — 0000
— — — — 0000
L<7:0> 0000
LN ively. See Section 12.1.1 “CLR, SET and INV Registers” for
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.ote 1: All registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respect
more information.2: This register does not have associated SET and INV registers.3: This register does not have associated CLR, SET and INV registers.4: Reset value for this bit is undefined.
PIC
32MX
5XX
/6XX
/7XX
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2009-2013 M
icrochip Technolo
gy Inc.
— — — — — 0000
— — FRMH<2:0> 0000
— — — — — 0000
EP<3:0> 0000
— — — — — 0000
CNT<7:0> 0000
— — — — — 0000
DTPTRH<7:0> 0000
— — — — — 0000
DTPTRU<7:0> 0000
— — — — — 0000
BSIDL — — — UASUSPND 0001
— — — — — 0000
ONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
— — — — — 0000
ONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
— — — — — 0000
ONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
— — — — — 0000
ONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
— — — — — 0000
ONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
— — — — — 0000
ONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
— — — — — 0000
ONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
— — — — — 0000
ONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
— — — — — 0000
ONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
— — — — — 0000
ONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
— — — — — 0000
ONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
All
Re
sets
0/4 19/3 18/2 17/1 16/0
spectively. See Section 12.1.1 “CLR, SET and INV Registers” for
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.Note 1: All registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC re
more information.2: This register does not have associated SET and INV registers.3: This register does not have associated CLR, SET and INV registers.4: Reset value for this bit is undefined.
2009
-2013 Microchip T
echnology Inc.
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PIC
32MX
5XX
/6XX
/7XX
— — — — 0000
S EPRXEN EPTXEN EPSTALL EPHSHK 0000
— — — — 0000
S EPRXEN EPTXEN EPSTALL EPHSHK 0000
— — — — 0000
S EPRXEN EPTXEN EPSTALL EPHSHK 0000
— — — — 0000
S EPRXEN EPTXEN EPSTALL EPHSHK 0000
— — — — 0000
S EPRXEN EPTXEN EPSTALL EPHSHK 0000
T
All
Re
sets
19/3 18/2 17/1 16/0
LN ively. See Section 12.1.1 “CLR, SET and INV Registers” for
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.ote 1: All registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respect
more information.2: This register does not have associated SET and INV registers.3: This register does not have associated CLR, SET and INV registers.4: Reset value for this bit is undefined.
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. Se
information.
2009
-2013 Microchip T
echnology Inc.
DS
60001156H
-page 111
PIC
32MX
5XX
/6XX
/7XX
FSEL18<4:0> 0000
FSEL16<4:0> 0000
FSEL22<4:0> 0000
FSEL20<4:0> 0000
FSEL26<4:0> 0000
FSEL24<4:0> 0000
FSEL30<4:0> 0000
FSEL28<4:0> 0000
EXID — EID<17:16> xxxx
xxxx
0000
0000
FSIZE<4:0> 0000
RR TXREQ RTREN TXPRI<1:0> 0000
RXOVFLIE RXFULLIE RXHALFIERXN
EMPTYIE0000
RXOVFLIF RXFULLIF RXHALFIFRXN
EMPTYIF0000
0000
0000
— — — — 0000
C1FIFOCI<4:0> 0000
T 128H, PIC32MX575F256H, X795F512H, PIC32MX534F064L, 764F128L, PIC32MX775F256L,
All
Re
sets
/4 19/3 18/2 17/1 16/0
LN tion 12.1.1 “CLR, SET and INV Registers” for more
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.ote 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Sec
information.
PIC
32MX
5XX
/6XX
/7XX
DS
60001156H
-page 112
2009-2013 M
icrochip Technolo
gy Inc.
95F512H, PIC32MX775F256L,
All
Re
sets
20/4 19/3 18/2 17/1 16/0
CANCAP — — — — 0480
DNCNT<4:0> 0000
— — SEG2PH<2:0> 0000
BRP<5:0> 0000
— MODIE CTMRIE RBIE TBIE 0000
— MODIF CTMRIF RBIF TBIF 0000
— — — — — 0000
ICODE<6:0> 0040
TXBP RXBP TXWARN RXWARN EWARN 0000
RERRCNT<7:0> 0000
FIFOIP20 FIFOIP19 FIFOIP18 FIFOIP17 FIFOIP16 0000
FIFOIP4 FIFOIP3 FIFOIP2 FIFOIP1 FIFOIP0 0000
RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000
0000
0000
-— MIDE — EID<17:16> xxxx
xxxx
-— MIDE — EID<17:16> xxxx
xxxx
-— MIDE — EID<17:16> xxxx
xxxx
-— MIDE — EID<17:16> xxxx
xxxx
FSEL2<4:0> 0000
FSEL0<4:0> 0000
FSEL6<4:0> 0000
FSEL4<4:0> 0000
FSEL10<4:0> 0000
FSEL8<4:0> 0000
FSEL14<4:0> 0000
FSEL12<4:0> 0000
e Section 12.1.1 “CLR, SET and INV Registers” for more
TABLE 4-46: CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX7PIC32MX775F512L AND PIC32MX795F512L DEVICES
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. Se
information.
2009
-2013 Microchip T
echnology Inc.
DS
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32MX
5XX
/6XX
/7XX
FSEL18<4:0> 0000
FSEL16<4:0: 0000
FSEL22<4:0> 0000
FSEL20<4:0> 0000
FSEL26<4:0> 0000
FSEL24<4:0> 0000
FSEL30<4:0> 0000
FSEL28<4:0> 0000
EXID — EID<17:16> xxxx
xxxx
0000
0000
FSIZE<4:0> 0000
R TXREQ RTREN TXPRI<1:0> 0000
RXOVFLIE RXFULLIE RXHALFIERXN
EMPTYIE0000
RXOVFLIF RXFULLIF RXHALFIFRXN
EMPTYIF0000
0000
0000
— — — — 0000
C2FIFOCI<4:0> 0000
T 512H, PIC32MX775F256L,
All
Re
sets
4 19/3 18/2 17/1 16/0
LN tion 12.1.1 “CLR, SET and INV Registers” for more
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.ote 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Sec
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.Note 1: All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0
INV Registers” for more information.2: Reset values default to the factory programmed value.
2009
-2013 Microchip T
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5XX
/6XX
/7XX
FCNT<7:0> 0000
— — — — 0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
0000
— — — — 0000
CK TXPAUSE RXPAUSE PASSALL RXENABLE 800D
— — — — 0000
EDELAYCRC HUGEFRM LENGTHCK FULLDPLX 4082
— — — — 0000
B2BIPKTGP<6:0> 0012
— — — — 0000
NB2BIPKTGP2<6:0> 0C12
— — — — 0000
RETX<3:0> 370F
— — — — 0000
05EE
T F128H, PIC32MX664F064L, 775F256H, PIC32MX775F512H, 764F128H, PIC32MX764F128L,
All
Re
sets
19/3 18/2 17/1 16/0
LN and 0xC, respectively. See Section 12.1.1 “CLR, SET and
egend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.ote 1: All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8
INV Registers” for more information.2: Reset values default to the factory programmed value.
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.Note 1: All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0
INV Registers” for more information.2: Reset values default to the factory programmed value.
PIC32MX5XX/6XX/7XX
4.2 Control Registers
Register 4-1 through Register 4-8 are used for settingthe RAM and Flash memory partitions for data andcode.
REGISTER 4-1: BMXCON: BUS MATRIX CONFIGURATION REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — —BMX
ERRIXIBMX
ERRICDBMX
ERRDMABMX
ERRDSBMX
ERRIS
15:8U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 R/W-1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-1
—BMX
WSDRM— — — BMXARB<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
bit 31-21 Unimplemented: Read as ‘0’
bit 20 BMXERRIXI: Enable Bus Error from IXI bit
1 = Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus0 = Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus
bit 19 BMXERRICD: Enable Bus Error from ICD Debug Unit bit
1 = Enable bus error exceptions for unmapped address accesses initiated from ICD0 = Disable bus error exceptions for unmapped address accesses initiated from ICD
bit 18 BMXERRDMA: Bus Error from DMA bit
1 = Enable bus error exceptions for unmapped address accesses initiated from DMA0 = Disable bus error exceptions for unmapped address accesses initiated from DMA
bit 17 BMXERRDS: Bus Error from CPU Data Access bit (disabled in Debug mode)
1 = Enable bus error exceptions for unmapped address accesses initiated from CPU data access0 = Disable bus error exceptions for unmapped address accesses initiated from CPU data access
bit 16 BMXERRIS: Bus Error from CPU Instruction Access bit (disabled in Debug mode)
1 = Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access0 = Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access
bit 15-7 Unimplemented: Read as ‘0’
bit 6 BMXWSDRM: CPU Instruction or Data Access from Data RAM Wait State bit
1 = Data RAM accesses from CPU have one wait state for address setup0 = Data RAM accesses from CPU have zero wait states for address setup
bit 5-3 Unimplemented: Read as ‘0’
bit 2-0 BMXARB<2:0>: Bus Matrix Arbitration Mode bits
111 = Reserved (using these Configuration modes will produce undefined behavior)•••
011 = Reserved (using these Configuration modes will produce undefined behavior)010 = Arbitration Mode 2001 = Arbitration Mode 1 (default)000 = Arbitration Mode 0
2009-2013 Microchip Technology Inc. DS60001156H-page 117
PIC32MX5XX/6XX/7XX
REGISTER 4-2: BMXDKPBA: DATA RAM KERNEL PROGRAM BASE ADDRESS REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0
BMXDKPBA<15:8>
7:0R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
BMXDKPBA<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-10 BMXDKPBA<15:10>: DRM Kernel Program Base Address bits
When non-zero, this value selects the relative base address for kernel program space in RAM
bit 9-0 BMXDKPBA<9:0>: DRM Kernel Program Base Address Read-Only bits
Value is always ‘0’, which forces 1 KB increments
Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal mode data usage.
2: The value in this register must be less than or equal to BMXDRMSZ.
DS60001156H-page 118 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 4-3: BMXDUDBA: DATA RAM USER DATA BASE ADDRESS REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0
BMXDUDBA<15:8>
7:0R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
BMXDUDBA<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-10 BMXDUDBA<15:10>: DRM User Data Base Address bits
When non-zero, the value selects the relative base address for User mode data space in RAM, the valuemust be greater than BMXDKPBA.
bit 9-0 BMXDUDBA<9:0>: DRM User Data Base Address Read-Only bits
Value is always ‘0’, which forces 1 KB increments
Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal mode data usage.
2: The value in this register must be less than or equal to BMXDRMSZ.
2009-2013 Microchip Technology Inc. DS60001156H-page 119
PIC32MX5XX/6XX/7XX
REGISTER 4-4: BMXDUPBA: DATA RAM USER PROGRAM BASE ADDRESS REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0
BMXDUPBA<15:8>
7:0R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
BMXDUPBA<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-10 BMXDUPBA<15:10>: DRM User Program Base Address bits
When non-zero, the value selects the relative base address for User mode program space in RAM,BMXDUPBA must be greater than BMXDUDBA.
bit 9-0 BMXDUPBA<9:0>: DRM User Program Base Address Read-Only bits
Value is always ‘0’, which forces 1 KB increments
Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal mode data usage.
2: The value in this register must be less than or equal to BMXDRMSZ.
DS60001156H-page 120 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 4-5: BMXDRMSZ: DATA RAM SIZE REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24R R R R R R R R
BMXDRMSZ<31:24>
23:16R R R R R R R R
BMXDRMSZ<23:16>
15:8R R R R R R R R
BMXDRMSZ<15:8>
7:0R R R R R R R R
BMXDRMSZ<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 BMXDRMSZ<31:0>: Data RAM Memory (DRM) Size bits
Static value that indicates the size of the Data RAM in bytes:0x00004000 = device has 16 KB RAM0x00008000 = device has 32 KB RAM0x00010000 = device has 64 KB RAM
REGISTER 4-6: BMXPUPBA: PROGRAM FLASH (PFM) USER PROGRAM BASE ADDRESS REGISTER(1,2)
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — BMXPUPBA<19:16>
15:8R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0
BMXPUPBA<15:8>
7:0R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
BMXPUPBA<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-20 Unimplemented: Read as ‘0’
bit 19-11 BMXPUPBA<19:11>: Program Flash (PFM) User Program Base Address bits
bit 10-0 BMXPUPBA<10:0>: Program Flash (PFM) User Program Base Address Read-Only bits
Value is always ‘0’, which forces 2 KB increments
Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal mode data usage.
2: The value in this register must be less than or equal to BMXPFMSZ.
2009-2013 Microchip Technology Inc. DS60001156H-page 121
PIC32MX5XX/6XX/7XX
REGISTER 4-7: BMXPFMSZ: PROGRAM FLASH (PFM) SIZE REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24R R R R R R R R
BMXPFMSZ<31:24>
23:16R R R R R R R R
BMXPFMSZ<23:16>
15:8R R R R R R R R
BMXPFMSZ<15:8>
7:0R R R R R R R R
BMXPFMSZ<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 BMXPFMSZ<31:0>: Program Flash Memory (PFM) Size bits
Static value that indicates the size of the PFM in bytes:0x00010000 = device has 64 KB Flash0x00020000 = device has 128 KB Flash0x00040000 = device has 256 KB Flash0x00080000 = device has 512 KB Flash
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 BMXBOOTSZ<31:0>: Boot Flash Memory (BFM) Size bits
Static value that indicates the size of the Boot PFM in bytes:0x00003000 = device has 12 KB boot Flash
DS60001156H-page 122 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
5.0 FLASH PROGRAM MEMORY PIC32MX5XX/6XX/7XX devices contain an internalFlash program memory for executing user code. Thereare three methods by which the user can program thismemory:
• Run-Time Self-Programming (RTSP)
• EJTAG Programming
• In-Circuit Serial Programming™ (ICSP™)
RTSP is performed by software executing from eitherFlash or RAM memory. Information about RTSPtechniques is available in Section 5. “Flash ProgramMemory” (DS60001121) in the “PIC32 FamilyReference Manual”.
EJTAG is performed using the EJTAG port of thedevice and an EJTAG capable programmer.
ICSP is performed using a serial data connection to thedevice and allows much faster programming times thanRTSP.
The EJTAG and ICSP methods are described in the“PIC32 Flash Programming Specification”(DS60001145), which can be downloaded from theMicrochip web site.
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 5. “FlashProgram Memory” (DS60001121) in the“PIC32 Family Reference Manual”, whichis available from the Microchip web site(www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
Note: For PIC32MX5XX/6XX/7XX devices, theFlash page size is 4 KB and the row sizeis 512 bytes (1024 IW and 128 IW,respectively).
2009-2013 Microchip Technology Inc. DS60001156H-page 123
Legend: U = Unimplemented bit, read as ‘0’ HSC = Set and Cleared by hardwareR = Readable bit W = Writable bit HS = Set by hardware HC = Cleared by hardware-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’bit 15 WR: Write Control bit
This bit is writable when WREN = 1 and the unlock sequence is followed.
1 = Initiate a Flash operation. Hardware clears this bit when the operation completes0 = Flash operation complete or inactive
bit 14 WREN: Write Enable bit1 = Enable writes to WR bit and enables LVD circuit0 = Disable writes to WR bit and disables LVD circuit
Note: This is the only bit in this register that is reset by a device Reset.bit 13 WRERR: Write Error bit(1)
This bit is read-only and is automatically set by hardware.
1 = Program or erase sequence did not complete successfully0 = Program or erase sequence completed normally
bit 12 LVDERR: Low-Voltage Detect Error bit (LVD circuit must be enabled)(1)
This bit is read-only and is automatically set by hardware.
1 = Low-voltage detected (possible data corruption, if WRERR is set)0 = Voltage level is acceptable for programming
bit 11 LVDSTAT: Low-Voltage Detect Status bit (LVD circuit must be enabled)(1)
This bit is read-only and is automatically set, and cleared, by hardware.
1 = Low-voltage event is active0 = Low-voltage event is not active
bit 10-4 Unimplemented: Read as ‘0’bit 3-0 NVMOP<3:0>: NVM Operation bits
These bits are writable when WREN = 0.
1111 = Reserved•••
0111 = Reserved0110 = No operation0101 = Program Flash (PFM) erase operation: erases PFM, if all pages are not write-protected0100 = Page erase operation: erases page selected by NVMADDR, if it is not write-protected0011 = Row program operation: programs row selected by NVMADDR, if it is not write-protected0010 = No operation0001 = Word program operation: programs word selected by NVMADDR, if it is not write-protected0000 = No operation
Note 1: This bit is cleared by setting NVMOP == 0000b, and initiating a Flash operation (i.e., WR).
DS60001156H-page 124 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 5-2: NVMKEY: PROGRAMMING UNLOCK REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
NVMKEY<31:24>
23:16W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
NVMKEY<23:16>
15:8W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
NVMKEY<15:8>
7:0W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
NVMKEY<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 NVMKEY<31:0>: Unlock Register bits
These bits are write-only, and read as ‘0’ on any read.
Note: This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM.
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 NVMADDR<31:0>: Flash Address bits
Bulk/Chip/PFM Erase: Address is ignored.Page Erase: Address identifies the page to erase.Row Program: Address identifies the row to program.Word Program: Address identifies the word to program.
2009-2013 Microchip Technology Inc. DS60001156H-page 125
PIC32MX5XX/6XX/7XX
REGISTER 5-4: NVMDATA: FLASH PROGRAM DATA REGISTER
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 NVMSRCADDR<31:0>: Source Data Address bits
The system physical address of the data to be programmed into the Flash when the NVMOP<3:0> bits (NVMCON<3:0>) are set to perform row programming.
DS60001156H-page 126 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
6.0 RESETS The Reset module combines all Reset sources andcontrols the device Master Reset signal, SYSRST. Thefollowing is a list of device Reset sources:
• Power-on Reset (POR)
• Master Clear Reset pin (MCLR)
• Software Reset (SWR)
• Watchdog Timer Reset (WDTR)
• Brown-out Reset (BOR)
• Configuration Mismatch Reset (CMR)
A simplified block diagram of the Reset module isillustrated in Figure 6-1.
FIGURE 6-1: SYSTEM RESET BLOCK DIAGRAM
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 7. “Resets”(DS60001118) in the “PIC32 FamilyReference Manual”, which is availablefrom the Microchip web site(www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
MCLR
VDDVDD Rise
Detect
POR
Sleep or Idle
Brown-outReset
WDTTime-out
Glitch Filter
BOR
Configuration
SYSRST
Software Reset
Power-upTimer
Voltage
Enabled
Reset
WDTR
SWR
CMR
MCLR
Mismatch
Regulator
2009-2013 Microchip Technology Inc. DS60001156H-page 127
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-10 Unimplemented: Read as ‘0’
bit 9 CMR: Configuration Mismatch Reset Flag bit 1 = Configuration mismatch Reset has occurred0 = Configuration mismatch Reset has not occurred
bit 8 VREGS: Voltage Regulator Standby Enable bit1 = Regulator is enabled and is on during Sleep mode0 = Regulator is disabled and is off during Sleep mode
bit 7 EXTR: External Reset (MCLR) Pin Flag bit1 = Master Clear (pin) Reset has occurred0 = Master Clear (pin) Reset has not occurred
bit 6 SWR: Software Reset Flag bit1 = Software Reset was executed0 = Software Reset was not executed
bit 5 Unimplemented: Read as ‘0’
bit 4 WDTO: Watchdog Timer Time-out Flag bit1 = WDT Time-out has occurred0 = WDT Time-out has not occurred
bit 3 SLEEP: Wake From Sleep Flag bit1 = Device was in Sleep mode0 = Device was not in Sleep mode
bit 2 IDLE: Wake From Idle Flag bit1 = Device was in Idle mode0 = Device was not in Idle mode
bit 1 BOR: Brown-out Reset Flag bit(1)
1 = Brown-out Reset has occurred 0 = Brown-out Reset has not occurred
bit 0 POR: Power-on Reset Flag bit(1)
1 = Power-on Reset has occurred0 = Power-on Reset has not occurred
Note 1: User software must clear this bit to view the next detection.
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REGISTER 6-2: RSWRST: SOFTWARE RESET REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0U-0 U-0 U-0 U-0 U-0 U-0 U-0 W-0, HC
— — — — — — — SWRST(1)
Legend: HC = Cleared by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-1 Unimplemented: Read as ‘0’
bit 0 SWRST: Software Reset Trigger bit(1)
1 = Enable software Reset event0 = No effect
Note 1: The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section 6. “Oscillator” (DS60001112) in the “PIC32 Family Reference Manual” for details.
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NOTES:
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7.0 INTERRUPT CONTROLLER
PIC32MX5XX/6XX/7XX devices generate interruptrequests in response to interrupt events from peripheralmodules. The interrupt control module exists externallyto the CPU logic and prioritizes the interrupt eventsbefore presenting them to the CPU.
The Interrupt Controller module includes the followingfeatures:
• Up to 96 interrupt sources
• Up to 64 interrupt vectors
• Single and multi-vector mode operations
• Five external interrupts with edge polarity control
• Interrupt proximity timer
• Seven user-selectable priority levels for each vector
• Four user-selectable subpriority levels within each priority
• Dedicated shadow set for user-selectable priority level
A simplified block diagram of the Interrupt Controllermodule is illustrated in Figure 7-1.
FIGURE 7-1: INTERRUPT CONTROLLER MODULE
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 8. “Interrupts”(DS60001108) in the “PIC32 FamilyReference Manual”, which is availablefrom the Microchip web site(www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
Interrupt ControllerInterrupt Requests
Vector Number
CPU CorePriority Level
Shadow Set Number
2009-2013 Microchip Technology Inc. DS60001156H-page 131
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32 USB and CAN – Features”, TABLE 2: “PIC32 USB and Ethernet – Features” and TABLE 3: “PIC32 USB, Ethernet and CAN – Features” for the list of available peripherals.
DS60001156H-page 132 2009-2013 Microchip Technology Inc.
TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1) IRQ Number
Vector Number
Interrupt Bit Location
Flag Enable Priority Sub-Priority
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32 USB and CAN – Features”, TABLE 2: “PIC32 USB and Ethernet – Features” and TABLE 3: “PIC32 USB, Ethernet and CAN – Features” for the list of available peripherals.
2009-2013 Microchip Technology Inc. DS60001156H-page 133
TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1) IRQ Number
Vector Number
Interrupt Bit Location
Flag Enable Priority Sub-Priority
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32 USB and CAN – Features”, TABLE 2: “PIC32 USB and Ethernet – Features” and TABLE 3: “PIC32 USB, Ethernet and CAN – Features” for the list of available peripherals.
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7.1 Control Registers
REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — SS0
15:8U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
— — — MVEC — TPC<2:0>
7:0U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — INT4EP INT3EP INT2EP INT1EP INT0EP
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-17 Unimplemented: Read as ‘0’
bit 16 SS0: Single Vector Shadow Register Set bit1 = Single vector is presented with a shadow register set0 = Single vector is not presented with a shadow register set
bit 15-13 Unimplemented: Read as ‘0’
bit 12 MVEC: Multiple Vector Configuration bit
1 = Interrupt controller configured for Multi-vector mode0 = Interrupt controller configured for Single-vector mode
bit 11 Unimplemented: Read as ‘0’
bit 10-8 TPC<2:0>: Interrupt Proximity Timer Control bits
111 = Interrupts of group priority 7 or lower start the Interrupt Proximity timer110 = Interrupts of group priority 6 or lower start the Interrupt Proximity timer101 = Interrupts of group priority 5 or lower start the Interrupt Proximity timer100 = Interrupts of group priority 4 or lower start the Interrupt Proximity timer011 = Interrupts of group priority 3 or lower start the Interrupt Proximity timer010 = Interrupts of group priority 2 or lower start the Interrupt Proximity timer001 = Interrupts of group priority 1 start the Interrupt Proximity timer000 = Disables Interrupt Proximity timer
bit 7-5 Unimplemented: Read as ‘0’
bit 4 INT4EP: External Interrupt 4 Edge Polarity Control bit
1 = Rising edge0 = Falling edge
bit 3 INT3EP: External Interrupt 3 Edge Polarity Control bit
1 = Rising edge0 = Falling edge
bit 2 INT2EP: External Interrupt 2 Edge Polarity Control bit
1 = Rising edge0 = Falling edge
bit 1 INT1EP: External Interrupt 1 Edge Polarity Control bit
1 = Rising edge0 = Falling edge
bit 0 INT0EP: External Interrupt 0 Edge Polarity Control bit
1 = Rising edge0 = Falling edge
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REGISTER 7-2: INTSTAT: INTERRUPT STATUS REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — RIPL<2:0>(1)
7:0U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — VEC<5:0>(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-11 Unimplemented: Read as ‘0’
bit 10-8 RIPL<2:0>: Requested Priority Level bits(1)
111-000 = The priority level of the latest interrupt presented to the CPU
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 VEC<5:0>: Interrupt Vector bits(1)
11111-00000 = The interrupt vector that is presented to the CPU
Note 1: This value should only be used when the interrupt controller is configured for Single-vector mode.
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 TPTMR<31:0>: Temporal Proximity Timer Reload bitsUsed by the Temporal Proximity Timer as a reload value when the Temporal Proximity timer is triggered by an interrupt event.
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REGISTER 7-4: IFSx: INTERRUPT FLAG STATUS REGISTER
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 IEC31-IEC00: Interrupt Enable bits1 = Interrupt is enabled0 = Interrupt is disabled
Note: This register represents a generic definition of the IECx register. Refer to Table 7-1 for the exact bitdefinitions.
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REGISTER 7-6: IPCx: INTERRUPT PRIORITY CONTROL REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — IP03<2:0> IS03<1:0>
23:16U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — IP02<2:0> IS02<1:0>
15:8U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — IP01<2:0> IS01<1:0>
7:0U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — IP00<2:0> IS00<1:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-26 IP03<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7•••
010 = Interrupt priority is 2001 = Interrupt priority is 1000 = Interrupt is disabled
bit 25-24 IS03<1:0>: Interrupt Subpriority bits
11 = Interrupt subpriority is 310 = Interrupt subpriority is 201 = Interrupt subpriority is 100 = Interrupt subpiority is 0
bit 23-21 Unimplemented: Read as ‘0’
bit 20-18 IP02<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7•••
010 = Interrupt priority is 2001 = Interrupt priority is 1000 = Interrupt is disabled
bit 17-16 IS02<1:0>: Interrupt Subpriority bits
11 = Interrupt subpriority is 310 = Interrupt subpriority is 201 = Interrupt subpriority is 100 = Interrupt subpriority is 0
bit 15-13 Unimplemented: Read as ‘0’
Note: This register represents a generic definition of the IPCx register. Refer to Table 7-1 for the exact bitdefinitions.
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bit 12-10 IP01<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7•••
010 = Interrupt priority is 2001 = Interrupt priority is 1000 = Interrupt is disabled
bit 9-8 IS01<1:0>: Interrupt Subpriority bits
11 = Interrupt subpriority is 310 = Interrupt subpriority is 201 = Interrupt subpriority is 100 = Interrupt subpriority is 0
bit 7-5 Unimplemented: Read as ‘0’
bit 4-2 IP00<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7•••
010 = Interrupt priority is 2001 = Interrupt priority is 1000 = Interrupt is disabled
bit 1-0 IS00<1:0>: Interrupt Subpriority bits
11 = Interrupt subpriority is 310 = Interrupt subpriority is 201 = Interrupt subpriority is 100 = Interrupt subpriority is 0
REGISTER 7-6: IPCx: INTERRUPT PRIORITY CONTROL REGISTER (CONTINUED)
Note: This register represents a generic definition of the IPCx register. Refer to Table 7-1 for the exact bitdefinitions.
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NOTES:
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8.0 OSCILLATOR CONFIGURATION
The Oscillator module has the following features:
• A total of four external and internal oscillator options as clock sources
• On-chip PLL with user-selectable input divider, multiplier and output divider to boost operating frequency on select internal and external oscillator sources
• On-chip user-selectable divisor postscaler on select oscillator sources
• Software-controllable switching between various clock sources
• A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown
• Dedicated On-Chip PLL for USB peripheral
Figure 8-1shows the Oscillator module block diagram.
FIGURE 8-1: OSCILLATOR BLOCK DIAGRAM
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 6. “Oscillator”(DS60001112) in the “PIC32 FamilyReference Manual”, which is availablefrom the Microchip web site(www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
Timer1, RTCC
Clock Control Logic
Fail-SafeClock
Monitor
FSCM INT
FSCM Event
COSC<2:0>NOSC<2:0>
OSWENFSCMEN<1:0>
PLL
Secondary Oscillator (SOSC)
SOSCEN and FSOSCEN
SOSCO
SOSCI
XTPLL, HSPLL,
XT, HS, EC
CPU and Select Peripherals
Peripherals
FRCDIV<2:0>
WDT, PWRT
8 MHz typical FRC
31.25 kHz typical
FRCOscillator
LPRCOscillator
SOSC
LPRC
FRCDIV
ECPLL, FRCPLL
TUN<5:0> div 16
Postscaler
FPLLIDIV<2:0> PBDIV<1:0>
FRC/16
Postscaler
PLL MultiplierCOSC<2:0>
FINdiv x div y
PLL Output DividerPLLODIV<2:0>
PLL Input Divider
div x
32.768 kHz
PLLMULT<2:0>
PBCLK
UFIN 4 MHz
PLL x24USB Clock (48 MHz)
div 2
UPLLEN
UFRCENdiv x
UPLLIDIV<2:0>
UFIN
4 MHz FIN 5 MHz
USB PLL
SYSCLK
Primary Oscillator
C1(3)
C2(3)
XTAL
RS(1)Enable
OSC2(4)
OSC1
RF(2)
To InternalLogic
(POSC)
RP(1)
Notes: 1. A series resistor, RS, may be required for AT strip cut crystals or eliminate clipping. Alternately, to increase oscillator circuit gain, add a parallel resistor, RP, with a value of 1 M
2. The internal feedback resistor, RF, is typically in the range of 2 to 10 M3. Refer to the “PIC32 Family Reference Manual” Section 6. “Oscillator
Configuration” (DS60001112) for help determining the best oscillator components.
4. PBCLK out is available on the OSC2 pin in certain clock modes.
2009-2013 Microchip Technology Inc. DS60001156H-page 141
Legend: y = Value set from Configuration bits on POR
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29-27 PLLODIV<2:0>: Output Divider for PLL
111 = PLL output divided by 256110 = PLL output divided by 64101 = PLL output divided by 32100 = PLL output divided by 16011 = PLL output divided by 8010 = PLL output divided by 4001 = PLL output divided by 2000 = PLL output divided by 1
bit 26-24 FRCDIV<2:0>: Internal Fast RC (FRC) Oscillator Clock Divider bits
111 = FRC divided by 256110 = FRC divided by 64101 = FRC divided by 32100 = FRC divided by 16011 = FRC divided by 8010 = FRC divided by 4001 = FRC divided by 2 (default setting)000 = FRC divided by 1
bit 23 Unimplemented: Read as ‘0’
bit 22 SOSCRDY: Secondary Oscillator (SOSC) Ready Indicator bit
1 = Indicates that the Secondary Oscillator is running and is stable0 = Secondary Oscillator is still warming up or is turned off
bit 21 PBDIVRDY: Peripheral Bus Clock (PBCLK) Divisor Ready bit
1 = PBDIV<1:0> bits can be written0 = PBDIV<1:0> bits cannot be written
bit 20-19 PBDIV<1:0>: Peripheral Bus Clock (PBCLK) Divisor bits
11 = PBCLK is SYSCLK divided by 8 (default)10 = PBCLK is SYSCLK divided by 401 = PBCLK is SYSCLK divided by 200 = PBCLK is SYSCLK divided by 1
Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the“PIC32 Family Reference Manual” for details.
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bit 18-16 PLLMULT<2:0>: Phase-Locked Loop (PLL) Multiplier bits
111 = Clock is multiplied by 24110 = Clock is multiplied by 21101 = Clock is multiplied by 20100 = Clock is multiplied by 19011 = Clock is multiplied by 18010 = Clock is multiplied by 17001 = Clock is multiplied by 16000 = Clock is multiplied by 15
bit 15 Unimplemented: Read as ‘0’
bit 14-12 COSC<2:0>: Current Oscillator Selection bits
111 = Internal Fast RC (FRC) Oscillator divided by OSCCON<FRCDIV> bits110 = Internal Fast RC (FRC) Oscillator divided by 16101 = Internal Low-Power RC (LPRC) Oscillator100 = Secondary Oscillator (SOSC)011 = Primary Oscillator (POSC) with PLL module (XTPLL, HSPLL or ECPLL)010 = Primary Oscillator (POSC) (XT, HS or EC)001 = Internal Fast RC Oscillator with PLL module via Postscaler (FRCPLL)000 = Internal Fast RC (FRC) Oscillator
bit 11 Unimplemented: Read as ‘0’
bit 10-8 NOSC<2:0>: New Oscillator Selection bits
111 = Internal Fast RC Oscillator (FRC) divided by OSCCON<FRCDIV> bits110 = Internal Fast RC Oscillator (FRC) divided by 16101 = Internal Low-Power RC (LPRC) Oscillator100 = Secondary Oscillator (SOSC)011 = Primary Oscillator with PLL module (XTPLL, HSPLL or ECPLL)010 = Primary Oscillator (XT, HS or EC)001 = Internal Fast Internal RC Oscillator with PLL module via Postscaler (FRCPLL)000 = Internal Fast Internal RC Oscillator (FRC)
On Reset, these bits are set to the value of the FNOSC Configuration bits (DEVCFG1<2:0>).
bit 7 CLKLOCK: Clock Selection Lock Enable bit
If clock switching and monitoring is disabled (FCKSM<1:0> = 1x):1 = Clock and PLL selections are locked0 = Clock and PLL selections are not locked and may be modified
If clock switching and monitoring is enabled (FCKSM<1:0> = 0x):Clock and PLL selections are never locked and may be modified.
bit 6 ULOCK: USB PLL Lock Status bit
1 = Indicates that the USB PLL module is in lock or USB PLL module start-up timer is satisfied0 = Indicates that the USB PLL module is out of lock or USB PLL module start-up timer is in progress or
USB PLL is disabled
bit 5 SLOCK: PLL Lock Status bit
1 = PLL module is in lock or PLL module start-up timer is satisfied0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled
bit 4 SLPEN: Sleep Mode Enable bit
1 = Device will enter Sleep mode when a WAIT instruction is executed0 = Device will enter Idle mode when a WAIT instruction is executed
bit 3 CF: Clock Fail Detect bit
1 = FSCM has detected a clock failure0 = No clock failure has been detected
REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the“PIC32 Family Reference Manual” for details.
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bit 2 UFRCEN: USB FRC Clock Enable bit
1 = Enable FRC as the clock source for the USB clock source0 = Use the Primary Oscillator or USB PLL as the USB clock source
bit 1 SOSCEN: Secondary Oscillator (SOSC) Enable bit
1 = Initiate an oscillator switch to selection specified by NOSC<2:0> bits0 = Oscillator switch is complete
REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the“PIC32 Family Reference Manual” for details.
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REGISTER 8-2: OSCTUN: FRC TUNING REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — TUN<5:0>(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-6 Unimplemented: Read as ‘0’
bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1)
100000 = Center frequency -12.5%100001 = •••111111 =000000 = Center frequency; Oscillator runs at minimal frequency (8 MHz)000001 =•••011110 =011111 = Center frequency +12.5%
Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on theFRC frequency over a wide range of temperatures. The tuning step size is an approximation, and is neithercharacterized, nor tested.
Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the“PIC32 Family Reference Manual” for details.
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9.0 PREFETCH CACHE Prefetch cache increases performance for applicationsexecuting out of the cacheable program Flash memoryregions by implementing instruction caching, constantdata caching and instruction prefetching.
9.1 Features
• 16 fully-associative lockable cache lines
• 16-byte cache lines
• Up to four cache lines allocated to data
• Two cache lines with address mask to hold repeated instructions
• Pseudo-LRU replacement policy
• All cache lines are software writable
• 16-byte parallel memory fetch
• Predictive instruction prefetch
A simplified block diagram of the Prefetch Cachemodule is illustrated in Figure 9-1.
FIGURE 9-1: PREFETCH CACHE MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 4. “PrefetchCache” (DS60001119) in the “PIC32Family Reference Manual”, which isavailable from the Microchip web site(www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
CTRL
RDATA
PrefetchPrefetch
Hit Logic
CacheLine
AddressEncode
Cache Line
FSM
CTRL RDATA
Tag Logic
Bus Control
Cache Control
Prefetch Control
Hit LRU
Miss LRU
BM
X/C
PU
BM
X/C
PU
CTRL
PFM
2009-2013 Microchip Technology Inc. DS60001156H-page 147
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-17 Unimplemented: Write ‘0’; ignore read
bit 16 CHECOH: Cache Coherency Setting on a PFM Program Cycle bit
1 = Invalidate all data and instruction lines0 = Invalidate all data lnes and instruction lines that are not locked
bit 15-10 Unimplemented: Write ‘0’; ignore read
bit 9-8 DCSZ<1:0>: Data Cache Size in Lines bits
Changing these bits causes all lines to be reinitialized to the “invalid” state.
11 = Enable data caching with a size of 4 lines10 = Enable data caching with a size of 2 lines 01 = Enable data caching with a size of 1 line00 = Disable data caching
bit 7-6 Unimplemented: Write ‘0’; ignore read
bit 5-4 PREFEN<1:0>: Predictive Prefetch Enable bits
11 = Enable predictive prefetch for both cacheable and non-cacheable regions10 = Enable predictive prefetch only for non-cacheable regions01 = Enable predictive prefetch only for cacheable regions00 = Disable predictive prefetch
bit 3 Unimplemented: Write ‘0’; ignore read
bit 2-0 PFMWS<2:0>: PFM Access Time Defined in Terms of SYSLK Wait States bits
111 = Seven Wait states110 = Six Wait states 101 = Five Wait states100 = Four Wait states011 = Three Wait states010 = Two Wait states 001 = One Wait state000 = Zero Wait state
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REGISTER 9-2: CHEACC: CACHE ACCESS REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
CHEWEN — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — CHEIDX<3:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 CHEWEN: Cache Access Enable bits
These bits apply to registers CHETAG, CHEMSK, CHEW0, CHEW1, CHEW2, and CHEW3.
1 = The cache line selected by CHEIDX<3:0> is writeable0 = The cache line selected by CHEIDX<3:0> is not writeable
bit 30-4 Unimplemented: Write ‘0’; ignore read
bit 3-0 CHEIDX<3:0>: Cache Line Index bits
The value selects the cache line for reading or writing.
2009-2013 Microchip Technology Inc. DS60001156H-page 149
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 LTAGBOOT: Line Tag Address Boot bit
1 = The line is in the 0x1D000000 (physical) area of memory0 = The line is in the 0x1FC00000 (physical) area of memory
bit 30-24 Unimplemented: Write ‘0’; ignore read
bit 23-4 LTAG<19:0>: Line Tag Address bits
LTAG<19:0> bits are compared against physical address to determine a hit. Because its address range andposition of PFM in kernel space and user space, the LTAG PFM address is identical for virtual addresses,(system) physical addresses, and PFM physical addresses.
bit 3 LVALID: Line Valid bit
1 = The line is valid and is compared to the physical address for hit detection0 = The line is not valid and is not compared to the physical address for hit detection
bit 2 LLOCK: Line Lock bit
1 = The line is locked and will not be replaced0 = The line is not locked and can be replaced
bit 1 LTYPE: Line Type bit
1 = The line caches instruction words0 = The line caches data words
bit 0 Unimplemented: Write ‘0’; ignore read
DS60001156H-page 150 2009-2013 Microchip Technology Inc.
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CHEHIT<31:0>: Cache Hit Count bits
Incremented each time the processor issues an instruction fetch or load that hits the prefetch cache from acacheable region. Non-cacheable accesses do not modify this value.
REGISTER 9-11: CHEMIS: CACHE MISS STATISTICS REGISTER
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CHEMIS<31:0>: Cache Miss Count bits
Incremented each time the processor issues an instruction fetch from a cacheable region that misses theprefetch cache. Non-cacheable accesses do not modify this value.
DS60001156H-page 154 2009-2013 Microchip Technology Inc.
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CHEPFABT<31:0>: Prefab Abort Count bits
Incremented each time an automatic prefetch cache is aborted due to a non-sequential instruction fetch, loador store.
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NOTES:
DS60001156H-page 156 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
10.0 DIRECT MEMORY ACCESS (DMA) CONTROLLER
The Direct Memory Access (DMA) controller is a busmaster module useful for data transfers betweendifferent devices without CPU intervention. The sourceand destination of a DMA transfer can be any of thememory mapped modules existent in the PIC32 (suchas SPI, UART, PMP, etc.) or memory itself.
Following are some of the key features of the DMAcontroller module:
• Four identical channels, each featuring:- Auto-increment source and destination address
registers- Source and destination pointers- Memory to memory and memory to
peripheral transfers
• Automatic word-size detection:- Transfer granularity, down to byte level- Bytes need not be word-aligned at source and
- Manual (software) or automatic (interrupt) DMA requests
- One-Shot or Auto-Repeat Block Transfer modes- Channel-to-channel chaining
• Flexible DMA requests:- A DMA request can be selected from any of the
peripheral interrupt sources- Each channel can select any (appropriate)
observable interrupt as its DMA request source- A DMA transfer abort can be selected from any of
the peripheral interrupt sources- Pattern (data) match transfer termination
• Multiple DMA channel status interrupts:- DMA channel block transfer complete- Source empty or half empty- Destination full or half full- DMA transfer aborted due to an external event- Invalid DMA address generated
• DMA debug support features:- Most recent address accessed by a DMA channel- Most recent DMA channel to transfer data
• CRC Generation module:- CRC module can be assigned to any of the
available channels- CRC module is highly configurable
FIGURE 10-1: DMA BLOCK DIAGRAM
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 31. “DirectMemory Access (DMA) Controller”(DS60001117) in the “PIC32 FamilyReference Manual”, which is availablefrom the Microchip web site(www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
Address Decoder Channel 0 Control
Channel 1 Control
Channel ‘n’ ControlGlobal Control(DMACON)
Bus Interface
Channel PriorityArbitration
SEL
SEL
Y
I0
I1
I2
In
System IRQINT Controller
Device Bus + Bus Arbitration
Peripheral Bus
2009-2013 Microchip Technology Inc. DS60001156H-page 157
REGISTER 10-1: DMACON: DMA CONTROLLER CONTROL REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0
ON(1) — — SUSPEND DMABUSY — — —
7:0U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: DMA On bit(1)
1 = DMA module is enabled0 = DMA module is disabled
bit 14-13 Unimplemented: Read as ‘0’
bit 12 SUSPEND: DMA Suspend bit
1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus0 = DMA operates normally
bit 11 DMABUSY: DMA Module Busy bit
1 = DMA module is active0 = DMA module is disabled and not actively transferring data
bit 10-0 Unimplemented: Read as ‘0’
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
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REGISTER 10-2: DMASTAT: DMA STATUS REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0
— — — — RDWR DMACH<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-4 Unimplemented: Read as ‘0’
bit 3 RDWR: Read/Write Status bit
1 = Last DMA bus access was a read0 = Last DMA bus access was a write
bit 2-0 DMACH<2:0>: DMA Channel bits
These bits contain the value of the most recent active DMA channel.
REGISTER 10-3: DMAADDR: DMA ADDRESS REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DMAADDR<31:24>
23:16R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DMAADDR<23:16>
15:8R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DMAADDR<15:8>
7:0R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DMAADDR<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 DMAADDR<31:0>: DMA Module Address bits
These bits contain the address of the most recent DMA access.
2009-2013 Microchip Technology Inc. DS60001156H-page 159
PIC32MX5XX/6XX/7XX
REGISTER 10-4: DCRCCON: DMA CRC CONTROL REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0
— — BYTO<1:0> WBO(1) — — BITO
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — PLEN<4:0>
7:0R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
CRCEN CRCAPP(1) CRCTYP — — CRCCH<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29-28 BYTO<1:0>: CRC Byte Order Selection bits11 = Endian byte swap on half-word boundaries (source half-word order with reverse source byte order
per half-word)10 = Swap half-words on word boundaries (reverse source half-word order with source byte order
per half-word)01 = Endian byte swap on word boundaries (reverse source byte order)00 = No swapping (source byte order)
bit 27 WBO: CRC Write Byte Order Selection bit(1)
1 = Source data is written to the destination re-ordered as defined by BYTO<1:0>0 = Source data is written to the destination unaltered
bit 26-25 Unimplemented: Read as ‘0’
bit 24 BITO: CRC Bit Order Selection bit
When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
1 = The IP header checksum is calculated Least Significant bit (LSb) first (reflected)0 = The IP header checksum is calculated Most Significant bit (MSb) first (not reflected)
When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):
1 = The LFSR CRC is calculated Least Significant bit first (reflected)0 = The LFSR CRC is calculated Most Significant bit first (not reflected)
bit 23-13 Unimplemented: Read as ‘0’
bit 12-8 PLEN<4:0>: Polynomial Length bits(1)
When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
These bits are unused.
When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):
Denotes the length of the polynomial – 1.
bit 7 CRCEN: CRC Enable bit
1 = CRC module is enabled and channel transfers are routed through the CRC module0 = CRC module is disabled and channel transfers proceed normally
Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.
DS60001156H-page 160 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
bit 6 CRCAPP: CRC Append Mode bit(1)
1 = The DMA transfers data from the source into the CRC but not to the destination. When a block transfercompletes the DMA writes the calculated CRC value to the location given by CHxDSA
0 = The DMA transfers data from the source through the CRC obeying WBO as it writes the data to thedestination
bit 5 CRCTYP: CRC Type Selection bit
1 = The CRC module will calculate an IP header checksum0 = The CRC module will calculate a LFSR CRC
bit 4-3 Unimplemented: Read as ‘0’
bit 2-0 CRCCH<2:0>: CRC Channel Select bits
111 = CRC is assigned to Channel 7110 = CRC is assigned to Channel 6101 = CRC is assigned to Channel 5100 = CRC is assigned to Channel 4011 = CRC is assigned to Channel 3010 = CRC is assigned to Channel 2001 = CRC is assigned to Channel 1000 = CRC is assigned to Channel 0
REGISTER 10-4: DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED)
Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.
2009-2013 Microchip Technology Inc. DS60001156H-page 161
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 DCRCDATA<31:0>: CRC Data Register bits
Writing to this register will seed the CRC generator. Reading from this register will return the current value ofthe CRC. Bits greater than PLEN will return ‘0’ on any read.
When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always ‘0’. Data writtento this register is converted and read back in 1’s complement form (current IP header checksum value).
When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):Bits greater than PLEN will return ‘0’ on any read.
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 DCRCXOR<31:0>: CRC XOR Register bits
When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):This register is unused.
When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):1 = Enable the XOR input to the Shift register0 = Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in
the register
DS60001156H-page 162 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 10-7: DCHxCON: DMA CHANNEL ‘x’ CONTROL REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
CHBUSY — — — — — — CHCHNS(1)
7:0R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R/W-0
CHEN(2) CHAED CHCHN CHAEN — CHEDET CHPRI<1:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 CHBUSY: Channel Busy bit
1 = Channel is active or has been enabled0 = Channel is inactive or has been disabled
bit 14-9 Unimplemented: Read as ‘0’
bit 8 CHCHNS: Chain Channel Selection bit(1)
1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
bit 7 CHEN: Channel Enable bit(2)
1 = Channel is enabled0 = Channel is disabled
bit 6 CHAED: Channel Allow Events If Disabled bit
1 = Channel start/abort events will be registered, even if the channel is disabled0 = Channel start/abort events will be ignored if the channel is disabled
bit CHCHN: Channel Chain Enable bit
1 = Allow channel to be chained0 = Do not allow channel to be chained
bit 4 CHAEN: Channel Automatic Enable bit
1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete0 = Channel is disabled on block transfer complete
bit 3 Unimplemented: Read as ‘0’
bit 2 CHEDET: Channel Event Detected bit
1 = An event has been detected0 = No events have been detected
bit 1-0 CHPRI<1:0>: Channel Priority bits
11 = Channel has priority 3 (highest)10 = Channel has priority 201 = Channel has priority 100 = Channel has priority 0
Note 1: The chain selection bit takes effect when chaining is enabled (CHCHN = 1).
2: When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if available on the device variant) to see when the channel is suspended, as it may take some clock cycles to complete a current transaction before the channel is suspended.
2009-2013 Microchip Technology Inc. DS60001156H-page 163
PIC32MX5XX/6XX/7XX
REGISTER 10-8: DCHxECON: DMA CHANNEL ‘x’ EVENT CONTROL REGISTER
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-16 CHAIRQ<7:0>: Channel Transfer Abort IRQ bits(1)
11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag•••
00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag
bit 15-8 CHSIRQ<7:0>: Channel Transfer Start IRQ bits(1)
11111111 = Interrupt 255 will initiate a DMA transfer•••
00000001 = Interrupt 1 will initiate a DMA transfer00000000 = Interrupt 0 will initiate a DMA transfer
bit 7 CFORCE: DMA Forced Transfer bit
1 = A DMA transfer is forced to begin when this bit is written to a ‘1’0 = This bit always reads ‘0’
bit 6 CABORT: DMA Abort Transfer bit
1 = A DMA transfer is aborted when this bit is written to a ‘1’0 = This bit always reads ‘0’
bit 5 PATEN: Channel Pattern Match Abort Enable bit
1 = Abort transfer and clear CHEN on pattern match0 = Pattern match is disabled
bit 4 SIRQEN: Channel Start IRQ Enable bit
1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs0 = Interrupt number CHSIRQ is ignored and does not start a transfer
bit 3 AIRQEN: Channel Abort IRQ Enable bit
1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer
bit 2-0 Unimplemented: Read as ‘0’
Note 1: See Table 7-1: “Interrupt IRQ, Vector and Bit Location” for the list of available interrupt IRQ sources.
DS60001156H-page 164 2009-2013 Microchip Technology Inc.
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REGISTER 10-9: DCHxINT: DMA CHANNEL ‘x’ INTERRUPT CONTROL REGISTER
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHCSIZ<15:0>: Channel Cell-Size bits
1111111111111111 = 65,535 bytes transferred on an event•••
0000000000000010 = 2 bytes transferred on an event0000000000000001 = 1 byte transferred on an event0000000000000000 = 65,536 bytes transferred on an event
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0 CHPDAT<7:0>: Channel Data Register bits
Pattern Terminate mode:Data to be matched must be stored in this register to allow terminate on match.
All other modes:Unused.
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NOTES:
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11.0 USB ON-THE-GO (OTG)
The Universal Serial Bus (USB) module containsanalog and digital components to provide a USB 2.0full-speed and low-speed embedded Host, full-speedDevice or OTG implementation with a minimum ofexternal components. This module in Host mode isintended for use as an embedded host and thereforedoes not implement a UHCI or OHCI controller.
The USB module consists of the clock generator, theUSB voltage comparators, the transceiver, the SerialInterface Engine (SIE), a dedicated USB DMA control-ler, pull-up and pull-down resistors, and the registerinterface. A block diagram of the PIC32 USB OTGmodule is presented in Figure 11-1.
The clock generator provides the 48 MHz clockrequired for USB full-speed and low-speed communi-cation. The voltage comparators monitor the voltage onthe VBUS pin to determine the state of the bus. Thetransceiver provides the analog translation betweenthe USB bus and the digital logic. The SIE is a statemachine that transfers data to and from the endpointbuffers and generates the hardware protocol for datatransfers. The USB DMA controller transfers databetween the data buffers in RAM and the SIE. The inte-grated pull-up and pull-down resistors eliminate theneed for external signaling components. The registerinterface allows the CPU to configure andcommunicate with the module.
The USB module includes the following features:
• USB Full-speed support for host and device
• Low-speed host support
• USB OTG support
• Integrated signaling resistors
• Integrated analog comparators for VBUS monitoring
• Integrated USB transceiver
• Transaction handshaking performed by hardware
• Endpoint buffering anywhere in system RAM
• Integrated DMA to access system RAM and Flash
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 27. “USB On-The-Go (OTG)” (DS60001126) in the“PIC32 Family Reference Manual”, whichis available from the Microchip web site(www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
Note: The implementation and use of the USBspecifications, as well as other third partyspecifications or technologies, mayrequire licensing; including, but not limitedto, USB Implementers Forum, Inc. (alsoreferred to as USB-IF). The user is fullyresponsible for investigating andsatisfying any applicable licensingobligations.
2009-2013 Microchip Technology Inc. DS60001156H-page 173
FIGURE 11-1: PIC32MX5XX/6XX/7XX FAMILY USB INTERFACE DIAGRAM
OSC1
OSC2
Primary Oscillator
8 MHz Typical
FRCOscillator
TUN<5:0>(4)
PLL
48 MHz USB Clock(7)
Div x
UPLLEN(6)
(PB Out)(1)
UFRCEN(3)
(POSC)
UPLLIDIV(6)
UFIN(5)
Div 2
VUSB3V3
D+(2)
D-(2)
ID(8)
Bus
TransceiverSIE
VBUSON(8)
Comparators
USBSRP Charge
SRP Discharge
Registersand
ControlInterface
Transceiver Power 3.3V
To Clock Generator for Core and Peripherals
Sleep or Idle
Sleep
USBEN
USB Suspend
CPU Clock Not POSC
USB Module
Voltage
SystemRAM
USB Suspend
Full-Speed Pull-up
Host Pull-down
Low-Speed Pull-up
Host Pull-down
ID Pull-up
DMA
Note 1: PB clock is only available on this pin for select EC modes.2: Pins can be used as digital inputs when USB is not enabled.3: This bit field is contained in the OSCCON register.4: This bit field is contained in the OSCTRM register.5: USB PLL UFIN requirements: 4 MHz.6: This bit field is contained in the DEVCFG2 register.7: A 48 MHz clock is required for proper USB operation.8: Pins can be used as GPIO when the USB module is disabled.
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11.1 Control Registers
REGISTER 11-1: U1OTGIR: USB OTG INTERRUPT STATUS REGISTER
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REGISTER 11-3: U1OTGSTAT: USB OTG STATUS REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0R-0 U-0 R-0 U-0 R-0 R-0 U-0 R-0
ID — LSTATE — SESVD SESEND — VBUSVD
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7 ID: ID Pin State Indicator bit
1 = No cable is attached or a “type B” cable has been inserted into the USB receptacle0 = A “type A” OTG cable has been inserted into the USB receptacle
bit 6 Unimplemented: Read as ‘0’
bit 5 LSTATE: Line State Stable Indicator bit
1 = USB line state (SE0 (U1CON<6> and JSTATE (U1CON<7>) has been stable for the previous 1 ms0 = USB line state (SE0 (U1CON<6> and JSTATE (U1CON<7>) has not been stable for the previous 1 ms
bit 4 Unimplemented: Read as ‘0’
bit 3 SESVD: Session Valid Indicator bit
1 = VBUS voltage is above Session Valid on the A or B device0 = VBUS voltage is below Session Valid on the A or B device
bit 2 SESEND: B-Device Session End Indicator bit
1 = VBUS voltage is below Session Valid on the B device0 = VBUS voltage is above Session Valid on the B device
bit 1 Unimplemented: Read as ‘0’
bit 0 VBUSVD: A-Device VBUS Valid Indicator bit
1 = VBUS voltage is above Session Valid on the A device0 = VBUS voltage is below Session Valid on the A device
2009-2013 Microchip Technology Inc. DS60001156H-page 177
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7 DPPULUP: D+ Pull-Up Enable bit
1 = D+ data line pull-up resistor is enabled0 = D+ data line pull-up resistor is disabled
bit 6 DMPULUP: D- Pull-Up Enable bit
1 = D- data line pull-up resistor is enabled0 = D- data line pull-up resistor is disabled
bit 5 DPPULDWN: D+ Pull-Down Enable bit
1 = D+ data line pull-down resistor is enabled0 = D+ data line pull-down resistor is disabled
bit 4 DMPULDWN: D- Pull-Down Enable bit
1 = D- data line pull-down resistor is enabled0 = D- data line pull-down resistor is disabled
bit 3 VBUSON: VBUS Power-on bit
1 = VBUS line is powered0 = VBUS line is not powered
bit 2 OTGEN: OTG Functionality Enable bit
1 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under software control0 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under USB hardware control
bit 1 VBUSCHG: VBUS Charge Enable bit
1 = VBUS line is charged through a pull-up resistor0 = VBUS line is not charged through a resistor
bit 0 VBUSDIS: VBUS Discharge Enable bit
1 = VBUS line is discharged through a pull-down resistor0 = VBUS line is not discharged through a resistor
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PIC32MX5XX/6XX/7XX
REGISTER 11-5: U1PWRC: USB POWER CONTROL REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0R-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
UACTPND — — USLPGRD USBBUSY — USUSPEND USBPWR
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7 UACTPND: USB Activity Pending bit
1 = USB bus activity has been detected; but an interrupt is pending, it has not been generated yet0 = An interrupt is not pending
bit 6-5 Unimplemented: Read as ‘0’
bit 4 USLPGRD: USB Sleep Entry Guard bit
1 = Sleep entry is blocked if USB bus activity is detected or if a notification is pending0 = USB module does not block Sleep entry
bit 3 USBBUSY: USB Module Busy bit
1 = USB module is active or disabled, but not ready to be enabled0 = USB module is not active and is ready to be enabled
Note: When USBPWR = 0 and USBBUSY = 1, status from all other registers is invalid and writes to allUSB module registers produce undefined results.
bit 2 Unimplemented: Read as ‘0’
bit 1 USUSPEND: USB Suspend Mode bit
1 = USB module is placed in Suspend mode(The 48 MHz USB clock will be gated off. The transceiver is placed in a low-power state.)
0 = USB module operates normally
bit 0 USBPWR: USB Operation Enable bit
1 = USB module is turned on0 = USB module is disabled
(Outputs held inactive, device pins not used by USB, analog features are shut down to reduce powerconsumption.)
2009-2013 Microchip Technology Inc. DS60001156H-page 179
Legend: WC = Write ‘1’ to clear HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7 STALLIF: STALL Handshake Interrupt bit1 = In Host mode a STALL handshake was received during the handshake phase of the transaction. In
Device mode, a STALL handshake was transmitted during the handshake phase of the transaction.0 = STALL handshake has not been sent
bit 6 ATTACHIF: Peripheral Attach Interrupt bit(1)
1 = Peripheral attachment was detected by the USB module0 = Peripheral attachment was not detected
bit 5 RESUMEIF: Resume Interrupt bit(2)
1 = K-State is observed on the D+ or D- pin for 2.5 µs0 = K-State is not observed
bit 4 IDLEIF: Idle Detect Interrupt bit1 = Idle condition detected (constant Idle state of 3 ms or more)0 = No Idle condition detected
bit 3 TRNIF: Token Processing Complete Interrupt bit(3)
1 = Processing of current token is complete; a read of the U1STAT register will provide endpoint information0 = Processing of current token not complete
bit 2 SOFIF: SOF Token Interrupt bit1 = SOF token received by the peripheral or the SOF threshold reached by the host0 = SOF token was not received nor threshold reached
bit 1 UERRIF: USB Error Condition Interrupt bit(4)
1 = Unmasked error condition has occurred0 = Unmasked error condition has not occurred
bit 0 URSTIF: USB Reset Interrupt bit (Device mode)(5)
1 = Valid USB Reset has occurred0 = No USB Reset has occurredDETACHIF: USB Detach Interrupt bit (Host mode)(6)
1 = Peripheral detachment was detected by the USB module0 = Peripheral detachment was not detected
Note 1: This bit is only valid if the HOSTEN bit is set (see Register 11-11), there is no activity on the USB for 2.5 µs, and the current bus state is not SE0.
2: When not in Suspend mode, this interrupt should be disabled.
3: Clearing this bit will cause the STAT FIFO to advance.
4: Only error conditions enabled through the U1EIE register will set this bit.
5: Device mode.
6: Host mode.
DS60001156H-page 180 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 11-7: U1IE: USB INTERRUPT ENABLE REGISTER
Legend: WC = Write ‘1’ to clear HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7 BTSEF: Bit Stuff Error Flag bit1 = Packet rejected due to bit stuff error0 = Packet accepted
bit 6 BMXEF: Bus Matrix Error Flag bit1 = Invalid base address of the BDT, or the address of an individual buffer pointed to by a BDT entry 0 = No address error
bit 5 DMAEF: DMA Error Flag bit(1)
1 = USB DMA error condition detected0 = No DMA error
bit 4 BTOEF: Bus Turnaround Time-Out Error Flag bit(2)
1 = Bus turnaround time-out has occurred0 = No bus turnaround time-out
bit 3 DFN8EF: Data Field Size Error Flag bit1 = Data field received is not an integral number of bytes0 = Data field received is an integral number of bytes
bit 2 CRC16EF: CRC16 Failure Flag bit1 = Data packet rejected due to CRC16 error0 = Data packet accepted
bit 1 CRC5EF: CRC5 Host Error Flag bit(4)
1 = Token packet rejected due to CRC5 error0 = Token packet acceptedEOFEF: EOF Error Flag bit(3,5)
bit 0 PIDEF: PID Check Failure Flag bit1 = PID check failed0 = PID check passed
Note 1: This type of error occurs when the module’s request for the DMA bus is not granted in time to service the module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer size is not sufficient to store the received data packet causing it to be truncated.
2: This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP) has elapsed.
3: This type of error occurs when the module is transmitting or receiving data and the SOF counter has reached zero.
4: Device mode.
5: Host mode.
DS60001156H-page 182 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 11-9: U1EIE: USB ERROR INTERRUPT ENABLE REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EECRC5EE(1)
PIDEEEOFEE(2)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: For an interrupt to propagate USBIF, the UERRIE bit (U1IE<1>) must be set.
2009-2013 Microchip Technology Inc. DS60001156H-page 183
PIC32MX5XX/6XX/7XX
REGISTER 11-10: U1STAT: USB STATUS REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0R-x R-x R-x R-x R-x R-x U-0 U-0
ENDPT<3:0> DIR PPBI — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-4 ENDPT<3:0>: Encoded Number of Last Endpoint Activity bits(Represents the number of the BDT, updated by the last USB transfer.)
1111 = Endpoint 151110 = Endpoint 14
•
•
•
0001 = Endpoint 10000 = Endpoint 0
bit 3 DIR: Last Buffer Descriptor Direction Indicator bit
1 = Last transaction was a transmit transfer (TX)0 = Last transaction was a receive transfer (RX)
bit 2 PPBI: Ping-Pong Buffer Descriptor Pointer Indicator bit
1 = The last transaction was to the Odd buffer descriptor bank0 = The last transaction was to the Even buffer descriptor bank
bit 1-0 Unimplemented: Read as ‘0’
Note: The U1STAT register is a window into a 4-byte FIFO maintained by the USB module. U1STAT value is onlyvalid when U1IR<TRNIF> is active. Clearing the U1IR<TRNIF> bit advances the FIFO. Data in register isinvalid when U1IR<TRNIF> = 0.
DS60001156H-page 184 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 11-11: U1CON: USB CONTROL REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
R-x R-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
JSTATE SE0PKTDIS(4)
USBRST HOSTEN(2) RESUME(3) PPBRSTUSBEN(4)
TOKBUSY(1,5) SOFEN(5)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7 JSTATE: Live Differential Receiver JSTATE flag bit1 = JSTATE was detected on the USB0 = JSTATE was not detected
bit 6 SE0: Live Single-Ended Zero flag bit1 = Single-ended zero was detected on the USB0 = Single-ended zero was not detected
bit 5 PKTDIS: Packet Transfer Disable bit(4)
1 = Token and packet processing disabled (set upon SETUP token received)0 = Token and packet processing enabled
TOKBUSY: Token Busy Indicator bit(1,5)
1 = Token being executed by the USB module0 = No token being executed
bit 4 USBRST: Module Reset bit(5)
1 = USB reset generated0 = USB reset terminated
bit 3 HOSTEN: Host Mode Enable bit(2)
1 = USB host capability enabled0 = USB host capability disabled
Note 1: Software is required to check this bit before issuing another token command to the U1TOK register (see Register 11-15).
2: All host control logic is reset any time that the value of this bit is toggled.
3: Software must set RESUME for 10 ms in Device mode, or for 25 ms in Host mode, and then clear it to enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to the RESUME signaling when this bit is cleared.
4: Device mode.
5: Host mode.
2009-2013 Microchip Technology Inc. DS60001156H-page 185
PIC32MX5XX/6XX/7XX
bit 1 PPBRST: Ping-Pong Buffers Reset bit1 = Reset all Even/Odd buffer pointers to the Even buffer descriptor banks0 = Even/Odd buffer pointers are not reset
bit 0 USBEN: USB Module Enable bit(4)
1 = USB module and supporting circuitry enabled0 = USB module and supporting circuitry disabled
SOFEN: SOF Enable bit(5)
1 = SOF token sent every 1 ms0 = SOF token disabled
REGISTER 11-11: U1CON: USB CONTROL REGISTER (CONTINUED)
Note 1: Software is required to check this bit before issuing another token command to the U1TOK register (see Register 11-15).
2: All host control logic is reset any time that the value of this bit is toggled.
3: Software must set RESUME for 10 ms in Device mode, or for 25 ms in Host mode, and then clear it to enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to the RESUME signaling when this bit is cleared.
4: Device mode.
5: Host mode.
DS60001156H-page 186 2009-2013 Microchip Technology Inc.
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-4 PID<3:0>: Token Type Indicator bits(1)
1101 = SETUP (TX) token type transaction1001 = IN (RX) token type transaction0001 = OUT (TX) token type transactionNote: All other values not listed, are Reserved and must not be used.
bit 3-0 EP<3:0>: Token Command Endpoint Address bits
The four bit value must specify a valid endpoint.
DS60001156H-page 188 2009-2013 Microchip Technology Inc.
bit 4 EPCONDIS: Bidirectional Endpoint Control bit
If EPTXEN = 1 and EPRXEN = 1:
1 = Disable Endpoint ‘n’ from control transfers; only TX and RX transfers are allowed0 = Enable Endpoint ‘n’ for control (SETUP) transfers; TX and RX transfers are also allowed
1 = Endpoint ’n’ was stalled0 = Endpoint ’n’ was not stalled
bit 0 EPHSHK: Endpoint Handshake Enable bit
1 = Endpoint Handshake enabled0 = Endpoint Handshake disabled (typically used for isochronous endpoints)
DS60001156H-page 192 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
12.0 I/O PORTS General purpose I/O pins are the simplest of peripher-als. They allow the PIC32 MCU to monitor and controlother devices. To add flexibility and functionality, somepins are multiplexed with alternate function(s). Thesefunctions depend on which peripheral features are onthe device. In general, when a peripheral is functioning,that pin may not be used as a general purpose I/O pin.
Following are some of the key features of this module:
when change in pin state is detected• Operation during Sleep and Idle modes• Fast bit manipulation using CLR, SET and INV
registersFigure 12-1 illustrates a block diagram of a typicalmultiplexed I/O port.
FIGURE 12-1: BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 12. “I/O Ports”(DS60001120) in the “PIC32 FamilyReference Manual”, which is availablefrom the Microchip web site(www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
Peripheral Output Data
Peripheral Module
Peripheral Output Enable
PIO Module
Peripheral Module Enable
WR LAT
I/O Pin
WR PORT
Data Bus
RD LAT
RD PORT
RD TRIS
WR TRIS
0
1
RD ODC
SYSCLK
QD
CKEN Q
QD
CKEN Q
QD
CKEN Q
Q D
CKQ
Q D
CKQ
0
1
SYSCLK
WR ODC
ODC
TRIS
LAT
Sleep
1
0
1
0
Output Multiplexers
I/O Cell
SynchronizationRPeripheral Input
Legend: R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details.
Note: This block diagram is a general representation of a shared port/peripheral structure is only for illustration purposes. The actual structurefor any specific port/peripheral combination may be different than it is shown here.
Peripheral Input Buffer
2009-2013 Microchip Technology Inc. DS60001156H-page 193
All port pins have three registers (TRIS, LAT andPORT) that are directly associated with their operation.
TRIS is a Data Direction or Tri-State Control registerthat determines whether a digital pin is an input or anoutput. Setting a TRISx register bit = 1, configures thecorresponding I/O pin as an input; setting a TRISxregister bit = 0, configures the corresponding I/O pin asan output. All port I/O pins are defined as inputs after adevice Reset. Certain I/O pins are shared with analogperipherals and default to analog inputs after a deviceReset.
PORT is a register used to read the current state of thesignal applied to the port I/O pins. Writing to a PORTxregister performs a write to the port’s latch, LATxregister, latching the data to the port’s I/O pins.
LAT is a register used to write data to the port I/O pins.The LATx Latch register holds the data written to eitherthe LATx or PORTx registers. Reading the LATx Latchregister reads the last value written to thecorresponding PORT or Latch register.
Not all port I/O pins are implemented on some devices,therefore, the corresponding PORTx, LATx and TRISxregister bits will read as zeros.
12.1.1 CLR, SET AND INV REGISTERS
Every I/O module register has a corresponding Clear(CLR), Set (SET) and Invert (INV) register designed toprovide fast atomic bit manipulations. As the name ofthe register implies, a value written to a SET, CLR orINV register effectively performs the implied operation,but only on the corresponding base register and onlybits specified as ‘1’ are modified. Bits specified as ‘0’are not modified.
Reading SET, CLR and INV registers returns undefinedvalues. To see the affects of a write operation to a SET,CLR or INV register, the base register must be read.
12.1.2 DIGITAL INPUTS
Pins are configured as digital inputs by setting thecorresponding TRIS register bits = 1. When configuredas inputs, they are either TTL buffers or SchmittTriggers. Several digital pins share functionality withanalog inputs and default to the analog inputs at POR.Setting the corresponding bit in the AD1PCFGregister = 1 enables the pin as a digital pin.
The maximum input voltage allowed on the input pinsis the same as the maximum VIH specification. Refer toSection 31.0 “Electrical Characteristics” for VIH
specification details.
12.1.3 ANALOG INPUTS
Certain pins can be configured as analog inputs usedby the ADC and comparator modules. Setting thecorresponding bits in the AD1PCFG register = 0enables the pin as an analog input pin and must havethe corresponding TRIS bit set = 1 (input). If the TRISbit is cleared = 0 (output), the digital output level (VOH
or VOL) will be converted. Any time a port I/O pin isconfigured as analog, its digital input is disabled andthe corresponding PORTx register bit will read ‘0’. TheAD1PCFG register has a default value of 0x0000;therefore, all pins that share ANx functions are analog(not digital) by default.
12.1.4 DIGITAL OUTPUTS
Pins are configured as digital outputs by setting thecorresponding TRIS register bits = 0. When configuredas digital outputs, these pins are CMOS drivers or canbe configured as open-drain outputs by setting thecorresponding bits in the Open-Drain Configuration(ODCx) register.
The open-drain feature allows generation of outputshigher than VDD (e.g., 5V) on any desired 5V tolerantpins by using external pull-up resistors. The maximumopen-drain voltage allowed is the same as themaximum VIH specification.
See the “Pin Diagrams” section for the available pinsand their functionality.
12.1.5 ANALOG OUTPUTS
Certain pins can be configured as analog outputs, suchas the CVREF output voltage used by the comparatormodule. Configuring the comparator reference moduleto provide this output will present the analog outputvoltage on the pin, independent of the TRIS registersetting for the corresponding pin.
12.1.6 INPUT CHANGE NOTIFICATION
The input change notification function of the I/O ports(CNx) allows devices to generate interrupt requests inresponse to change-of-state on selected pin.
Each CNx pin also has a weak pull-up, which acts as acurrent source connected to the pin. The pull-ups areenabled by setting the corresponding bit in the CNPUEregister.
Note: Using a PORTxINV register to toggle a bitis recommended because the operation isperformed in hardware atomically, usingfewer instructions, as compared to thetraditional read-modify-write method, asfollows:
PORTC ^ = 0x0001;
Note: Analog levels on any pin that is defined asa digital input (including the ANx pins)may cause the input buffer to consumecurrent that exceeds the devicespecifications.
DS60001156H-page 194 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
12.2 Control Register
REGISTER 12-1: CNCON: CHANGE NOTICE CONTROL REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
ON — SIDL — — — — —
7:0U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: Change Notice (CN) Control ON bit
1 = CN is enabled0 = CN is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Control bit
1 = Idle mode halts CN operation0 = Idle mode does not affect CN operation
bit 12-0 Unimplemented: Read as ‘0’
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PIC32MX5XX/6XX/7XX
NOTES:
DS60001156H-page 196 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
13.0 TIMER1 This family of PIC32 devices features one synchronous/asynchronous 16-bit timer that can operate as a free-run-ning interval timer for various timing applications andcounting external events. This timer can also be usedwith the low-power Secondary Oscillator (SOSC) forReal-Time Clock (RTC) applications. The followingmodes are supported:
• Synchronous Internal Timer
• Synchronous Internal Gated Timer
• Synchronous External Timer
• Asynchronous External Timer
13.1 Additional Supported Features
• Selectable clock prescaler
• Timer operation during Idle and Sleep mode
• Fast bit manipulation using CLR, SET and INV registers
• Asynchronous mode can be used with the SOSC to function as a Real-Time Clock (RTC)
A simplified block diagram of the Timer1 module isillustrated in Figure 13-1.
FIGURE 13-1: TIMER1 BLOCK DIAGRAM
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 14. “Timers”(DS60001105) in the “PIC32 FamilyReference Manual”, which is availablefrom the Microchip web site(www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
ON (T1CON<15>)
Sync
SOSCI
SOSCO/T1CK
PR1
T1IF
Equal16-bit Comparator
TMR1Reset
SOSCEN(1)
Event Flag
1
0
TSYNC (T1CON<2>)
TGATE (T1CON<7>)
TGATE (T1CON<7>)
PBCLK
1
0
TCS (T1CON<1>)
GateSync
TCKPS<1:0>
Prescaler
2
1, 8, 64, 256
x 1
1 0
0 0
Q
Q D
(T1CON<5:4>)
Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit inConfiguration Word, DEVCFG1.
2009-2013 Microchip Technology Inc. DS60001156H-page 197
REGISTER 13-1: T1CON: TYPE A TIMER CONTROL REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8R/W-0 U-0 R/W-0 R/W-0 R-0 U-0 U-0 U-0
ON(1) — SIDL TWDIS TWIP — — —
7:0R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0
TGATE — TCKPS<1:0> — TSYNC TCS —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: Timer On bit(1)
1 = Timer is enabled0 = Timer is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Discontinue operation when device enters Idle mode0 = Continue operation when device is in Idle mode
bit 12 TWDIS: Asynchronous Timer Write Disable bit
1 = Writes to TMR1 are ignored until pending write operation completes0 = Back-to-back writes are enabled (Legacy Asynchronous Timer functionality)
bit 11 TWIP: Asynchronous Timer Write in Progress bit
In Asynchronous Timer mode:1 = Asynchronous write to TMR1 register in progress0 = Asynchronous write to TMR1 register complete
In Synchronous Timer mode:This bit is read as ‘0’.
bit 10-8 Unimplemented: Read as ‘0’
bit 7 TGATE: Timer Gated Time Accumulation Enable bit
When TCS = 1:This bit is ignored.
When TCS = 0:1 = Gated time accumulation is enabled0 = Gated time accumulation is disabled
bit 6 Unimplemented: Read as ‘0’
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
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bit 5-4 TCKPS<1:0>: Timer Input Clock Prescale Select bits
REGISTER 13-1: T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED)
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
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NOTES:
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14.0 TIMER2/3, TIMER4/5
This family of PIC32 devices features four synchronous16-bit timers (default) that can operate as a free-running interval timer for various timing applicationsand counting external events. The following modes aresupported:
• Synchronous Internal 16-bit Timer
• Synchronous Internal 16-bit Gated Timer
• Synchronous External 16-bit Timer
Two 32-bit synchronous timers are available bycombining Timer2 with Timer3 and Timer4 with Timer5.The 32-bit timers can operate in three modes:
• Synchronous Internal 32-bit Timer
• Synchronous Internal 32-bit Gated Timer
• Synchronous External 32-bit Timer
14.1 Additional Supported Features
• Selectable clock prescaler
• Timers operational during CPU idle
• Time base for Input Capture and Output Compare modules (only Timer2 and Timer3)
• ADC event trigger (only Timer3)
• Fast bit manipulation using CLR, SET and INV registers
FIGURE 14-1: TIMER2/3 AND TIMER4/5 BLOCK DIAGRAM (16-BIT)
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 14. “Timers”(DS60001105) of the “PIC32 FamilyReference Manual”, which is availablefrom the Microchip web site(www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
Note: In this chapter, references to registers,TxCON, TMRx and PRx, use ‘x’ torepresent Timer2 through Timer5 in 16-bitmodes. In 32-bit modes, ‘x’ representsTimer2 or Timer4; ‘y’ represents Timer3 orTimer5.
Sync
PRx
TxIF
EqualComparator x 16
TMRx
Reset
Event Flag
Q
Q D
TGATE (TxCON<7>)
1
0
Gate
TxCK(2)
Sync
ON (TxCON<15>)
TGATE (TxCON<7>)
TCS (TxCON<1>)
TCKPS (TxCON<6:4>)
Prescaler
3
1, 2, 4, 8, 16,32, 64, 256
x 1
1 0
0 0PBCLK
Trigger(1)ADC Event
Note 1: ADC event trigger is only available on Timer3.
2: TxCK pins are not available on 64-pin devices.
2009-2013 Microchip Technology Inc. DS60001156H-page 201
FIGURE 14-2: TIMER2/3 AND TIMER4/5 BLOCK DIAGRAM (32-BIT)
TMRy TMRx
TyIF Event
Equal 32-bit Comparator
PRy PRx
Reset
LS Half WordMS Half Word
Flag
Note 1: In this diagram, the use of ‘x’ in registers, TxCON, TMRx, PRx and TxCK, refers to either Timer2 or Timer4; the useof ‘y’ in registers, TyCON, TMRy, PRy, TyIF, refers to either Timer3 or Timer5.
2: TxCK pins are not available on 64-pin devices.
3: ADC event trigger is only available on the Timer2/3 pair.
TGATE (TxCON<7>)
0
1
PBCLK
Gate
TxCK(2)
Sync
Sync
ADC EventTrigger(3)
ON (TxCON<15>)
TGATE (TxCON<7>)
TCS (TxCON<1>)
TCKPS (TxCON<6:4>)
Prescaler
3
1, 2, 4, 8, 16,32, 64, 256
1 0
0 0
Q
Q D
x 1
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14.2 Control Register
REGISTER 14-1: TXCON: TYPE B TIMER CONTROL REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
ON(1,3) — SIDL(4) — — — — —
7:0R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0
TGATE(3) TCKPS<2:0>(3) T32(2) — TCS(3) —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: Timer On bit(1,3)
1 = Module is enabled0 = Module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit(4)
1 = Discontinue operation when device enters Idle mode0 = Continue operation when device is in Idle mode
bit 12-8 Unimplemented: Read as ‘0’
bit 7 TGATE: Timer Gated Time Accumulation Enable bit(3)
When TCS = 1:This bit is ignored and is read as ‘0’.
When TCS = 0:1 = Gated time accumulation is enabled0 = Gated time accumulation is disabled
bit 6-4 TCKPS<2:0>: Timer Input Clock Prescale Select bits(3)
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: This bit is only available on even numbered timers (Timer2 and Timer4).
3: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, and Tim-er5). All timer functions are set through the even numbered timers.
4: While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer in Idle mode.
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bit 3 T32: 32-Bit Timer Mode Select bit(2)
1 = Odd numbered and even numbered timers form a 32-bit timer0 = Odd numbered and even numbered timers form a separate 16-bit timer
REGISTER 14-1: TXCON: TYPE B TIMER CONTROL REGISTER (CONTINUED)
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: This bit is only available on even numbered timers (Timer2 and Timer4).
3: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, and Tim-er5). All timer functions are set through the even numbered timers.
4: While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer in Idle mode.
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15.0 INPUT CAPTURE
The Input Capture module is useful in applicationsrequiring frequency (period) and pulse measurement.
The Input Capture module captures the 16-bit or 32-bitvalue of the selected Time Base registers when anevent occurs at the ICx pin. The following events causecapture events:
• Simple capture event modes:
- Capture timer value on every falling edge of input at ICx pin
- Capture timer value on every rising edge of input at ICx pin
• Capture timer value on every edge (rising and falling)
• Capture timer value on every edge (rising and falling), specified edge first.
• Prescaler capture event modes:
- Capture timer value on every 4th rising edge of input at ICx pin
- Capture timer value on every 16th rising edge of input at ICx pin
Each input capture channel can select between one oftwo 16-bit timers (Timer2 or Timer3) for the time base,or two 16-bit timers (Timer2 and Timer3) together toform a 32-bit timer. The selected timer can use eitheran internal or external clock.
Other operational features include:
• Device wake-up from capture pin during Sleep and Idle modes
• Interrupt on input capture event
• 4-word FIFO buffer for capture valuesInterrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled
• Input Capture module can also be used to provide additional sources of external interrupts
FIGURE 15-1: INPUT CAPTURE BLOCK DIAGRAM
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 15. “InputCapture” (DS60001122) of the “PIC32Family Reference Manual”, which isavailable from the Microchip web site(www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
Prescaler1, 4, 16
Edge Detect
FIFO Control
Interrupt Event
Generation
ICxBUF<31:16>
Interrupt
Timer3 Timer2
ICxCONICI<1:0>
ICx Input
0 1
ICxBUF<15:0>
Data Space Interface
Peripheral Data Bus
C32
ICTMR
ICM<2:0>FEDGE ICBNE
ICOV
ICM<2:0>
2009-2013 Microchip Technology Inc. DS60001156H-page 205
bit 7 ICTMR: Timer Select bit (Does not affect timer selection when C32 (ICxCON<8>) is ‘1’)
1 = Timer2 is the counter source for capture 0 = Timer3 is the counter source for capture
bit 6-5 ICI<1:0>: Interrupt Control bits
11 = Interrupt on every fourth capture event10 = Interrupt on every third capture event01 = Interrupt on every second capture event00 = Interrupt on every capture event
bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only)
bit 3 ICBNE: Input Capture Buffer Not Empty Status bit (read-only)
1 = Input capture buffer is not empty; at least one more capture value can be read0 = Input capture buffer is empty
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
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bit 2-0 ICM<2:0>: Input Capture Mode Select bits
111 = Interrupt-Only mode (only supported while in Sleep mode or Idle mode)110 = Simple Capture Event mode – every edge, specified edge first and every edge thereafter101 = Prescaled Capture Event mode – every sixteenth rising edge100 = Prescaled Capture Event mode – every fourth rising edge011 = Simple Capture Event mode – every rising edge010 = Simple Capture Event mode – every falling edge001 = Edge Detect mode – every edge (rising and falling)000 = Input Capture module is disabled
REGISTER 15-1: ICXCON: INPUT CAPTURE ‘X’ CONTROL REGISTER (CONTINUED)
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
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NOTES:
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16.0 OUTPUT COMPARE The Output Compare module is used to generate asingle pulse or a series of pulses in response toselected time base events. For all modes of operation,the Output Compare module compares the valuesstored in the OCxR and/or the OCxRS registers to thevalue in the selected timer. When a match occurs, theOutput Compare module generates an event based onthe selected mode of operation.
Some of the key features of the Output Comparemodule are:
• Multiple Output Compare modules in a device
• Programmable interrupt generation on compare event
• Single and Dual Compare modes
• Single and continuous output pulse generation
• Pulse-Width Modulation (PWM) mode
• Hardware-based PWM Fault detection and automatic output disable
• Programmable selection of 16-bit or 32-bit time bases
• Can operate from either of two available 16-bit time bases or a single 32-bit time base
FIGURE 16-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 16. “OutputCompare” (DS60001111) in the “PIC32Family Reference Manual”, which isavailable from the Microchip web site(www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
OCxR(1)
Comparator
OutputLogic
QSR
OCM<2:0>
Output Enable
OCx(1)
Set Flag bitOCxIF(1)
OCxRS(1)
Mode Select
3
Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels,1 through 5.
2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel.3: Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base.
0 1 OCTSEL 0 1
16 16
OCFA or OCFB(2)
TMR Register Inputsfrom Time Bases(3)
Period Match Signalsfrom Time Bases(3)
LogicOutput Enable
2009-2013 Microchip Technology Inc. DS60001156H-page 209
REGISTER 16-1: OCxCON: OUTPUT COMPARE ‘x’ CONTROL REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
ON(1) — SIDL — — — — —
7:0U-0 U-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
— — OC32 OCFLT(2) OCTSEL OCM<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: Output Compare Module On bit(1)
1 = Output Compare module is enabled0 = Output Compare module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Discontinue operation when CPU enters Idle mode0 = Continue operation when CPU is in Idle mode
bit 12-6 Unimplemented: Read as ‘0’
bit 5 OC32: 32-bit Compare Mode bit
1 = OCxR<31:0> and/or OCxRS<31:0> are used for comparisions to the 32-bit timer source0 = OCxR<15:0> and OCxRS<15:0> are used for comparisons to the 16-bit timer source
bit 4 OCFLT: PWM Fault Condition Status bit(2)
1 = PWM Fault condition has occurred (only cleared in hardware)0 = PWM Fault condition has not occurred
bit 3 OCTSEL: Output Compare Timer Select bit1 = Timer3 is the clock source for this Output Compare module0 = Timer2 is the clock source for this Output Compare module
bit 2-0 OCM<2:0>: Output Compare Mode Select bits111 = PWM mode on OCx; Fault pin enabled110 = PWM mode on OCx; Fault pin disabled101 = Initialize OCx pin low; generate continuous output pulses on OCx pin100 = Initialize OCx pin low; generate single output pulse on OCx pin011 = Compare event toggles OCx pin010 = Initialize OCx pin high; compare event forces OCx pin low001 = Initialize OCx pin low; compare event forces OCx pin high000 = Output compare peripheral is disabled but continues to draw current
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: This bit is only used when OCM<2:0> = 111. It is read as ‘0’ in all other modes.
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17.0 SERIAL PERIPHERAL INTERFACE (SPI)
The SPI module is a synchronous serial interface thatis useful for communicating with external peripheralsand other microcontroller devices. These peripheraldevices may be Serial EEPROMs, Shift registers, dis-play drivers, Analog-to-Digital Converters, etc. ThePIC32 SPI module is compatible with Motorola® SPIand SIOP interfaces.
Some of the key features of this module include:
• Master mode and Slave mode support
• Four different clock formats
• Enhanced Framed SPI protocol support
• User-configurable 8-bit, 16-bit and 32-bit data width
• Separate SPI FIFO buffers for receive and transmit
- FIFO buffers act as 4/8/16-level deep FIFOs based on 32/16/8-bit data width
• Programmable interrupt event on every 8-bit, 16-bit and 32-bit data transfer
• Operation during Sleep and Idle modes
• Fast bit manipulation using CLR, SET and INV registers
FIGURE 17-1: SPI MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 23. “SerialPeripheral Interface (SPI)”(DS60001106) in the “PIC32 FamilyReference Manual”, which is availablefrom the Microchip web site(www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
InternalData Bus
SDIx
SDOx
SSx/FSYNC
SCKx
SPIxSR
bit 0
ShiftControl
EdgeSelect
Enable Master Clock
Baud Rate
Slave Select
Sync Control
ClockControl
Transmit
Receive
and Frame
Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register.
FIFOs Share Address SPIxBUF
SPIxBUF
Generator PBCLK
WriteRead
SPIxTXB FIFOSPIxRXB FIFO
2009-2013 Microchip Technology Inc. DS60001156H-page 211
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 FRMEN: Framed SPI Support bit1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output)0 = Framed SPI support is disabled
bit 30 FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (only Framed SPI mode)1 = Frame sync pulse input (Slave mode)0 = Frame sync pulse output (Master mode)
bit 29 FRMPOL: Frame Sync Polarity bit (only Framed SPI mode)1 = Frame pulse is active-high0 = Frame pulse is active-low
bit 28 MSSEN: Master Mode Slave Select Enable bit1 = Slave select SPI support enabled. The SS pin is automatically driven during transmission in
Master mode. Polarity is determined by the FRMPOL bit.0 = Slave select SPI support is disabled.
bit 27 FRMSYPW: Frame Sync Pulse Width bit1 = Frame sync pulse is one character wide0 = Frame sync pulse is one clock wide
bit 26-24 FRMCNT<2:0>: Frame Sync Pulse Counter bits. Controls the number of data characters transmitted perpulse. This bit is only valid in Framed Sync mode.111 = Reserved110 = Reserved101 = Generate a frame sync pulse on every 32 data characters100 = Generate a frame sync pulse on every 16 data characters011 = Generate a frame sync pulse on every 8 data characters010 = Generate a frame sync pulse on every 4 data characters001 = Generate a frame sync pulse on every 2 data characters000 = Generate a frame sync pulse on every data character
bit 23-18 Unimplemented: Read as ‘0’
bit 17 SPIFE: Frame Sync Pulse Edge Select bit (only Framed SPI mode)1 = Frame synchronization pulse coincides with the first bit clock0 = Frame synchronization pulse precedes the first bit clock
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: This bit can only be written when the ON bit = 0.
3: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI mode (FRMEN = 1).
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bit 16 ENHBUF: Enhanced Buffer Enable bit(2)
1 = Enhanced Buffer mode is enabled0 = Enhanced Buffer mode is disabled
bit 15 ON: SPI Peripheral On bit(1)
1 = SPI Peripheral is enabled0 = SPI Peripheral is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit1 = Discontinue operation when CPU enters in Idle mode0 = Continue operation in Idle mode
bit 12 DISSDO: Disable SDOx pin bit1 = SDOx pin is not used by the module (pin is controlled by associated PORT register)0 = SDOx pin is controlled by the module
bit 11-10 MODE<32,16>: 32/16-Bit Communication Select bitsMODE32 MODE16 Communication
1 x 32-bit0 1 16-bit0 0 8-bit
bit 9 SMP: SPI Data Input Sample Phase bitMaster mode (MSTEN = 1):1 = Input data sampled at end of data output time0 = Input data sampled at middle of data output time
Slave mode (MSTEN = 0):SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0.
bit 8 CKE: SPI Clock Edge Select bit(3)
1 = Serial output data changes on transition from active clock state to Idle clock state (see CKP bit)0 = Serial output data changes on transition from Idle clock state to active clock state (see CKP bit)
bit 7 SSEN: Slave Select Enable (Slave mode) bit1 = SSx pin used for Slave mode0 = SSx pin not used for Slave mode (pin is controlled by port function)
bit 6 CKP: Clock Polarity Select bit1 = Idle state for clock is a high level; active state is a low level0 = Idle state for clock is a low level; active state is a high level
bit 3-2 STXISEL<1:0>: SPI Transmit Buffer Empty Interrupt Mode bits11 = Interrupt is generated when the buffer is not full (has one or more empty elements)10 = Interrupt is generated when the buffer is empty by one-half or more01 = Interrupt is generated when the buffer is completely empty00 = Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are
complete
bit 1-0 SRXISEL<1:0>: SPI Receive Buffer Full Interrupt Mode bits11 = Interrupt is generated when the buffer is full10 = Interrupt is generated when the buffer is full by one-half or more01 = Interrupt is generated when the buffer is not empty00 = Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty)
REGISTER 17-1: SPIxCON: SPI CONTROL REGISTER (CONTINUED)
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: This bit can only be written when the ON bit = 0.
3: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI mode (FRMEN = 1).
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REGISTER 17-2: SPIxSTAT: SPI STATUS REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
— — — RXBUFELM<4:0>
23:16U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
— — — TXBUFELM<4:0>
15:8U-0 U-0 U-0 U-0 R-0 U-0 U-0 R-0
— — — — SPIBUSY — — SPITUR
7:0R-0 R/W-0 R-0 U-0 R-1 U-0 R-0 R-0
SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF
Legend: C = Clearable bit HS = Set in hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 RXBUFELM<4:0>: Receive Buffer Element Count bits (only valid when ENHBUF = 1)
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TXBUFELM<4:0>: Transmit Buffer Element Count bits (only valid when ENHBUF = 1)
bit 15-12 Unimplemented: Read as ‘0’
bit 11 SPIBUSY: SPI Activity Status bit
1 = SPI peripheral is currently busy with some transactions0 = SPI peripheral is currently idle
bit 10-9 Unimplemented: Read as ‘0’
bit 8 SPITUR: Transmit Under Run bit
1 = Transmit buffer has encountered an underrun condition
0 = Transmit buffer has no underrun condition
This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling/re-enablingthe module.
bit 7 SRMT: Shift Register Empty bit (only valid when ENHBUF = 1)
1 = When SPI module shift register is empty
0 = When SPI module shift register is not empty
bit 6 SPIROV: Receive Overflow Flag bit1 = A new data is completely received and discarded. The user software has not read the previous data in
the SPIxBUF register.0 = No overflow has occurred
This bit is set in hardware; can only be cleared (= 0) in software.
bit 5 SPIRBE: RX FIFO Empty bit (only valid when ENHBUF = 1)1 = RX FIFO is empty (CRPTR = SWPTR)0 = RX FIFO is not empty (CRPTR SWPTR)
bit 4 Unimplemented: Read as ‘0’
bit 3 SPITBE: SPI Transmit Buffer Empty Status bit
1 = Transmit buffer, SPIxTXB is empty0 = Transmit buffer, SPIxTXB is not empty
Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR.
Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB.
bit 2 Unimplemented: Read as ‘0’
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bit 1 SPITBF: SPI Transmit Buffer Full Status bit
1 = Transmit not yet started, SPITXB is full0 = Transmit buffer is not full
Standard Buffer Mode:
Automatically set in hardware when the core writes to the SPIBUF location, loading SPITXB.Automatically cleared in hardware when the SPI module transfers data from SPITXB to SPISR.
Enhanced Buffer Mode:
Set when CWPTR + 1 = SRPTR; cleared otherwise
bit 0 SPIRBF: SPI Receive Buffer Full Status bit
1 = Receive buffer, SPIxRXB is full0 = Receive buffer, SPIxRXB is not full
Standard Buffer Mode:
Automatically set in hardware when the SPI module transfers data from SPIxSR to SPIxRXB.Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB.
Enhanced Buffer Mode:
Set when SWPTR + 1 = CRPTR; cleared otherwise
REGISTER 17-2: SPIxSTAT: SPI STATUS REGISTER
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NOTES:
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18.0 INTER-INTEGRATED CIRCUIT™ (I2C™)
The I2C module provides complete hardware supportfor both Slave and Multi-Master modes of the I2C serialcommunication standard. Figure 18-1 illustrates theI2C module block diagram.
Each I2C module has a 2-pin interface: the SCLx pin isclock and the SDAx pin is data.
Each I2C module offers the following key features:
• I2C interface supporting both master and slave operation
• I2C Slave mode supports 7-bit and 10-bit addressing
• I2C Master mode supports 7-bit and 10-bit addressing
• I2C port allows bidirectional transfers between master and slaves
• Serial clock synchronization for the I2C port can be used as a handshake mechanism to suspend and resume serial transfer (SCLREL control)
• I2C supports multi-master operation; detects bus collision and arbitrates accordingly
• Provides support for address bit masking
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 24. “Inter-Integrated Circuit™ (I2C™)”(DS60001116) in the “PIC32 FamilyReference Manual”, which is availablefrom the Microchip web site(www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
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18.1 Control Registers
REGISTER 18-1: I2CXCON: I2C™ CONTROL REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0
ON(1) — SIDL SCLREL STRICT A10M DISSLW SMEN
7:0R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC
GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN
Legend: HC = Cleared by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: I2C Enable bit(1)
1 = Enables the I2C module and configures the SDA and SCL pins as serial port pins0 = Disables the I2C module; all I2C pins are controlled by PORT functions
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode0 = Continue module operation when device enters Idle mode
bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave)
If STREN = 1:Bit is R/W (software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Cleared by hardware at the beginning of a slave transmission and at the end of slave reception.
If STREN = 0:Bit is R/S (software can only write ‘1’ to release clock). Cleared by hardware at the beginning of slavetransmission.
bit 11 STRICT: Strict I2C Reserved Address Rule Enable bit
1 = Strict reserved addressing is enforced. Device does not respond to reserved address space or generateaddresses in reserved address space.
0 = Strict I2C reserved address rule is not enabled
bit 10 A10M: 10-bit Slave Address bit
1 = I2CxADD is a 10-bit slave address0 = I2CxADD is a 7-bit slave address
bit 9 DISSLW: Disable Slew Rate Control bit
1 = Slew rate control disabled0 = Slew rate control enabled
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
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bit 7 GCEN: General Call Enable bit (when operating as I2C slave)
1 = Enable interrupt when a general call address is received in the I2CxRSR(module is enabled for reception)
0 = General call address disabled
bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with SCLREL bit.1 = Enable software or receive clock stretching0 = Disable software or receive clock stretching
bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that is transmitted when the software initiates an acknowledge sequence.1 = Send NACK during an acknowledge0 = Send ACK during an acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master receive)
1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Hardware clear at end of master Acknowledge sequence.
0 = Acknowledge sequence not in progress
bit 3 RCEN: Receive Enable bit (when operating as I2C master)
1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte.0 = Receive sequence not in progress
bit 2 PEN: Stop Condition Enable bit (when operating as I2C master)
1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.0 = Stop condition not in progress
bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master RepeatedStart sequence.
0 = Repeated Start condition is not in progress
bit 0 SEN: Start Condition Enable bit (when operating as I2C master)
1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.0 = Start condition is not in progress
REGISTER 18-1: I2CXCON: I2C™ CONTROL REGISTER (CONTINUED)
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
DS60001156H-page 220 2009-2013 Microchip Technology Inc.
The UART module is one of the serial I/O modulesavailable in PIC32MX5XX/6XX/7XX family devices.The UART is a full-duplex, asynchronous communica-tion channel that communicates with peripheraldevices and personal computers through protocols,such as RS-232, RS-485, LIN 1.2 and IrDA®. Themodule also supports the hardware flow control option,with UxCTS and UxRTS pins, and also includes anIrDA encoder and decoder.
The primary features of the UART module are:
• Full-duplex, 8-bit or 9-bit data transmission
• Even, Odd or No Parity options (for 8-bit data)
• One or two Stop bits
• Hardware auto-baud feature
• Hardware flow control option
• Fully integrated Baud Rate Generator (BRG) with 16-bit prescaler
• Baud rates ranging from 76 bps to 20 Mbps at 80 MHz
• 8-level deep First-In-First-Out (FIFO) transmit data buffer
• 8-level deep FIFO receive data buffer
• Parity, framing and buffer overrun error detection
• Support for interrupt-only on address detect (ninth bit = 1)
• Separate transmit and receive interrupts
• Loopback mode for diagnostic support
• LIN 1.2 Protocol support
• IrDA encoder and decoder with 16x baud clock output for external IrDA encoder/decoder support
Figure 19-1 illustrates a simplified block diagram of theUART module.
FIGURE 19-1: UART SIMPLIFIED BLOCK DIAGRAM
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 21. “UniversalAsynchronous Receiver Transmitter(UART)” (DS60001107) in the “PIC32Family Reference Manual”, which isavailable from the Microchip web site(www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
Baud Rate Generator
UxRX
Hardware Flow Control
UARTx Receiver
UARTx Transmitter UxTX
UxCTS
UxRTS
BCLKxIrDA®
Note: Not all pins are available for all UART modules. Refer to the device-specific pin diagram for more information(see “Pin Diagrams”).
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19.1 Control Registers
REGISTER 19-1: UxMODE: UARTx MODE REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
ON(1) — SIDL IREN RTSMD — UEN<1:0>
7:0R/W-0 R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL
Legend: HC = Cleared by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: UARTx Enable bit(1)
1 = UARTx is enabled. UARTx pins are controlled by UARTx as defined by UEN<1:0> and UTXEN control bits.
0 = UARTx is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx and LATxregisters; UARTx power consumption is minimal.
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Discontinue operation when device enters Idle mode0 = Continue operation when device enters Idle mode
bit 12 IREN: IrDA Encoder and Decoder Enable bit
1 = IrDA is enabled0 = IrDA is disabled
bit 11 RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin is in Simplex mode0 = UxRTS pin is in Flow Control mode
bit 10 Unimplemented: Read as ‘0’
bit 9-8 UEN<1:0>: UARTx Enable bits
11 = UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bitsin the PORTx register
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits
in the PORTx register00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by
corresponding bits in the PORTx register
bit 7 WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit1 = Wake-up is enabled0 = Wake-up is disabled
bit 6 LPBACK: UARTx Loopback Mode Select bit1 = Loopback mode is enabled0 = Loopback mode is disabled
Note 1: When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
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bit 5 ABAUD: Auto-Baud Enable bit1 = Enable baud rate measurement on the next character – requires reception of Sync character (0x55);
cleared by hardware upon completion0 = Baud rate measurement disabled or completed
bit 4 RXINV: Receive Polarity Inversion bit1 = UxRX Idle state is ‘0’0 = UxRX Idle state is ‘1’
bit 3 BRGH: High Baud Rate Enable bit1 = High-Speed mode – 4x baud clock enabled 0 = Standard Speed mode – 16x baud clock enabled
bit 2-1 PDSEL<1:0>: Parity and Data Selection bits11 = 9-bit data, no parity10 = 8-bit data, odd parity01 = 8-bit data, even parity00 = 8-bit data, no parity
bit 0 STSEL: Stop Selection bit1 = 2 Stop bits0 = 1 Stop bit
Note 1: When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
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REGISTER 19-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
15:8R/W-0 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0 R-0 R-1
UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT
7:0R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/W-0, HS R-0
URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA
Legend: HS = Set by hardware HC = Cleared by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-25 Unimplemented: Read as ‘0’
bit 24 ADM_EN: Automatic Address Detect Mode Enable bit
1 = Automatic Address Detect mode is enabled0 = Automatic Address Detect mode is disabled
bit 23-16 ADDR<7:0>: Automatic Address Mask bits
When the ADM_EN bit is ‘1’, this value defines the address character to use for automatic addressdetection.
bit 15-14 UTXISEL<1:0>: TX Interrupt Mode Selection bits
11 = Reserved, do not use10 = Interrupt is generated and asserted while the transmit buffer is empty01 = Interrupt is generated and asserted when all characters have been transmitted00 = Interrupt is generated and asserted while the transmit buffer contains at least one empty space
bit 13 UTXINV: Transmit Polarity Inversion bit
If IrDA mode is disabled (i.e., IREN (UxMODE<12>) is ‘0’):1 = UxTX Idle state is ‘0’0 = UxTX Idle state is ‘1’
If IrDA mode is enabled (i.e., IREN (UxMODE<12>) is ‘1’):1 = IrDA encoded UxTX Idle state is ‘1’0 = IrDA encoded UxTX Idle state is ‘0’
bit 12 URXEN: Receiver Enable bit1 = UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1)0 = UARTx receiver is disabled. UxRX pin is ignored by the UARTx module. UxRX pin is controlled by port.
bit 11 UTXBRK: Transmit Break bit1 = Send Break on next transmission. Start bit followed by twelve ‘0’ bits, followed by Stop bit; cleared by
hardware upon completion.0 = Break transmission is disabled or completed
bit 10 UTXEN: Transmit Enable bit1 = UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1)0 = UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset. UxTX pin is
controlled by port.
bit 9 UTXBF: Transmit Buffer Full Status bit (read-only)1 = Transmit buffer is full0 = Transmit buffer is not full, at least one more character can be written
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bit 8 TRMT: Transmit Shift Register is Empty bit (read-only)1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed)0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer
bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bit11 = Reserved10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full (has 6 or more data characters)01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full (has 4 or more data characters)00 = Interrupt flag bit is asserted while receive buffer is not empty (has at least 1 data character)
bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)1 = Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect.0 = Address Detect mode is disabled
bit 4 RIDLE: Receiver Idle bit (read-only)1 = Receiver is idle0 = Data is being received
bit 3 PERR: Parity Error Status bit (read-only)1 = Parity error has been detected for the current character0 = Parity error has not been detected
bit 2 FERR: Framing Error Status bit (read-only)1 = Framing error has been detected for the current character0 = Framing error has not been detected
bit 1 OERR: Receive Buffer Overrun Error Status bit.
This bit is set in hardware and can only be cleared (= 0) in software. Clearing a previously set OERR bitresets the receiver buffer and RSR to an empty state.
1 = Receive buffer has overflowed0 = Receive buffer has not overflowed
bit 0 URXDA: Receive Buffer Data Available bit (read-only)1 = Receive buffer has data, at least one more character can be read0 = Receive buffer is empty
REGISTER 19-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
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20.0 PARALLEL MASTER PORT (PMP)
The PMP is a parallel 8-bit/16-bit input/output modulespecifically designed to communicate with a widevariety of parallel devices, such as communicationsperipherals, LCDs, external memory devices andmicrocontrollers. Because the interface to parallelperipherals varies significantly, the PMP module ishighly configurable. Figure 20-1 shows the PMPmodule pinout and its connections to external devices.
Key features of the PMP module include:
• 8-bit and 16-bit interface
• Up to 16 programmable address lines
• Up to two Chip Select lines
• Programmable strobe options
- Individual read and write strobes, or
- Read/Write strobe with enable strobe
• Address auto-increment/auto-decrement
• Programmable address/data multiplexing
• Programmable polarity on control signals
• Parallel Slave Port support
- Legacy addressable
- Address support
- 4-byte deep auto-incrementing buffer
• Programmable wait states
• Operates during Sleep and Idle modes
• Fast bit manipulation using CLR, SET and INV registers
FIGURE 20-1: PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 13. “ParallelMaster Port (PMP)” (DS60001128) inthe “PIC32 Family Reference Manual”,which is available from the Microchip website (www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
Note: On 64-pin devices, the PMD<15:8> datapins are not available.
PMA<0>
PMA<14>
PMA<15>
PMRD
PMWRPMENB
PMRD/PMWR
PMCS1
PMA<1>
PMA<13:2>
PMALL
PMALH
PMCS2
Flash
Address Bus
Data Bus
Control LinesPIC32MX5XX/6XX/7XX
LCDFIFO
Microcontroller
16/8-bit Data (with or without multiplexed addressing)
Up to 16-bit Address
Parallel
Buffer
PMD<15:8>(1)PMD<7:0>
Master Port
Note 1: On 64-pin devices, data pins, PMD<15:8>, are not available in 16-bit Master modes.
EEPROMSRAM
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REGISTER 20-1: PMCON: PARALLEL PORT CONTROL REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ON(1) — SIDL ADRMUX<1:0> PMPTTL PTWREN PTRDEN
7:0R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0
CSF<1:0>(2) ALP(2) — CS1P(2) — WRSP RDSP
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: Parallel Master Port Enable bit(1)
1 = PMP is enabled0 = PMP is disabled, no off-chip access performed
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode0 = Continue module operation when device enters Idle mode
bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits11 = Lower 8 bits of address are multiplexed on PMD<7:0> pins; upper 8 bits are not used10 = All 16 bits of address are multiplexed on PMD<7:0> pins01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper bits are on PMA<10:8> and
PMA<14>00 = Address and data appear on separate pins
bit 10 PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMWR/PMENB port is enabled0 = PMWR/PMENB port is disabled
bit 8 PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port is enabled0 = PMRD/PMWR port is disabled
bit 7-6 CSF<1:0>: Chip Select Function bits(2)
11 = Reserved10 = PMCS1 functions as Chip Select01 = PMCS1 functions as address bit 1400 = PMCS1 functions as address bit 14
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in theSYSCLK cycle immediately following the instruction that clears the module’s ON control bit.
2: These bits have no effect when their corresponding pins are used as address lines.
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bit 5 ALP: Address Latch Polarity bit(2)
1 = Active-high (PMALL and PMALH)0 = Active-low (PMALL and PMALH)
bit 4 Unimplemented: Read as ‘0’
bit 3 CS1P: Chip Select 0 Polarity bit(2)
1 = Active-high (PMCS1)0 = Active-low (PMCS1)
bit 2 Unimplemented: Read as ‘0’
bit 1 WRSP: Write Strobe Polarity bit
For Slave Modes and Master mode 2 (PMMODE<9:8> = 00,01,10):
REGISTER 20-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in theSYSCLK cycle immediately following the instruction that clears the module’s ON control bit.
2: These bits have no effect when their corresponding pins are used as address lines.
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REGISTER 20-2: PMMODE: PARALLEL PORT MODE REGISTER
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 BUSY: Busy bit (only Master mode)
1 = Port is busy 0 = Port is not busy
bit 14-13 IRQM<1:0>: Interrupt Request Mode bits
11 = Reserved10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)
or on a read or write operation when PMA<1:0> =11 (only Addressable Slave mode)01 = Interrupt generated at the end of the read/write cycle00 = Interrupt is not generated
bit 12-11 INCM<1:0>: Increment Mode bits
11 = Slave mode read and write buffers auto-increment (only PMMODE<1:0> = 00)10 = Decrement ADDR<10:2> and ADDR<14> by 1 every read/write cycle(2)
01 = Increment ADDR<10:2> and ADDR<14> by 1 every read/write cycle(2)
00 = No increment or decrement of address
bit 10 Unimplemented: Read as ‘0’
bit 9-8 MODE<1:0>: Parallel Port Mode Select bits
11 = Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMA<x:0>, and PMD<7:0>)10 = Master mode 2 (PMCS1, PMRD, PMWR, PMA<x:0>, and PMD<7:0>)01 = Enhanced Slave mode, control signals (PMRD, PMWR, PMCS1, PMD<7:0>, and PMA<1:0>)00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1, and PMD<7:0>)
bit 7-6 WAITB<1:0>: Data Setup to Read/Write Strobe Wait States bits(1)
11 = Data wait of 4 TPB; multiplexed address phase of 4 TPB
10 = Data wait of 3 TPB; multiplexed address phase of 3 TPB
01 = Data wait of 2 TPB; multiplexed address phase of 2 TPB
00 = Data wait of 1 TPB; multiplexed address phase of 1 TPB (default)
Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for awrite operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation.
2: Address bit A14 is not subject to auto-increment/decrement if configured as Chip Select CS1.
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bit 5-2 WAITM<3:0>: Data Read/Write Strobe Wait States bits(1)
1111 = Wait of 16 TPB
•
•
•
0001 = Wait of 2 TPB
0000 = Wait of 1 TPB (default)
bit 1-0 WAITE<1:0>: Data Hold After Read/Write Strobe Wait States bits(1)
11 = Wait of 4 TPB
10 = Wait of 3 TPB
01 = Wait of 2 TPB
00 = Wait of 1 TPB (default)
For Read operations:11 = Wait of 3 TPB
10 = Wait of 2 TPB
01 = Wait of 1 TPB
00 = Wait of 0 TPB (default)
REGISTER 20-2: PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED)
Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for awrite operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation.
2: Address bit A14 is not subject to auto-increment/decrement if configured as Chip Select CS1.
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REGISTER 20-3: PMADDR: PARALLEL PORT ADDRESS REGISTER
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 15-14 PTEN14: PMCS1 Strobe Enable bits
1 = PMA14 functions as either PMA14 or PMCS1(1)
0 = PMA14 functions as port I/O
bit 13-11 Unimplemented: Read as ‘0’
bit 10-2 PTEN<10:2>: PMP Address Port Enable bits
1 = PMA<10:2> function as PMP address lines0 = PMA<10:2> function as port I/O
bit 1-0 PTEN<1:0>: PMALH/PMALL Strobe Enable bits
1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL(2)
0 = PMA1 and PMA0 pads function as port I/O
Note 1: The use of this pin as PMA14 or CS1 is selected by the CSF<1:0> bits in the PMCON register.
2: The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode selected by bits ADRMUX<1:0> in the PMCON register.
2009-2013 Microchip Technology Inc. DS60001156H-page 235
PIC32MX5XX/6XX/7XX
REGISTER 20-5: PMSTAT: PARALLEL PORT STATUS REGISTER (ONLY SLAVE MODES)
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8R-0 R/W-0, HSC U-0 U-0 R-0 R-0 R-0 R-0
IBF IBOV — — IB3F IB2F IB1F IB0F
7:0R-1 R/W-0, HSC U-0 U-0 R-1 R-1 R-1 R-1
OBE OBUF — — OB3E OB2E OB1E OB0E
Legend: HSC = Set by Hardware; Cleared by Software
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 IBF: Input Buffer Full Status bit
1 = All writable input buffer registers are full0 = Some or all of the writable input buffer registers are empty
bit 14 IBOV: Input Buffer Overflow Status bit
1 = A write attempt to a full input byte buffer occurred (must be cleared in software)0 = An overflow has not occurred
bit 13-12 Unimplemented: Read as ‘0’
bit 11-8 IBxF: Input Buffer ‘x’ Status Full bits
1 = Input buffer contains data that has not been read (reading buffer will clear this bit)0 = Input buffer does not contain any unread data
bit 7 OBE: Output Buffer Empty Status bit
1 = All readable output buffer registers are empty0 = Some or all of the readable output buffer registers are full
bit 6 OBUF: Output Buffer Underflow Status bit
1 = A read occurred from an empty output byte buffer (must be cleared in software)0 = An underflow has not occurred
bit 5-4 Unimplemented: Read as ‘0’
bit 3-0 OBxE: Output Buffer ‘x’ Status Empty bits
1 = Output buffer is empty (writing data to the buffer will clear this bit)0 = Output buffer contains data that has not been transmitted
DS60001156H-page 236 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
21.0 REAL-TIME CLOCK AND CALENDAR (RTCC)
The PIC32 RTCC module is intended for applicationsin which accurate time must be maintained forextended periods of time with minimal or no CPUintervention. Low-power optimization providesextended battery lifetime while keeping track of time.A simplified block diagram of the RTCC module isillustrated in Figure 21-1.
Key features of the RTCC module include:
• Time: hours, minutes and seconds
• 24-hour format (military time)
• Visibility of one-half second period
• Provides calendar: Weekday, date, month and year
• Alarm intervals are configurable for half of a second, one second, 10 seconds, one minute, 10 minutes, one hour, one day, one week, one month and one year
• Alarm repeat with decrementing counter
• Alarm with indefinite repeat: Chime
• Year range: 2000 to 2099
• Leap year correction
• BCD format for smaller firmware overhead
• Optimized for long-term battery operation
• Fractional second synchronization
• User calibration of the clock crystal frequency with auto-adjust
• Calibration range: 0.66 seconds error per month
• Calibrates up to 260 ppm of crystal error
• Requirements: External 32.768 kHz clock crystal
• Alarm pulse or seconds clock output on RTCC pin
FIGURE 21-1: RTCC BLOCK DIAGRAM
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 29. “Real-TimeClock and Calendar (RTCC)”(DS60001125) in the “PIC32 FamilyReference Manual”, which is availablefrom the Microchip web site(www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
Seconds Pulse
RTCC Prescalers
RTCC Timer
Comparator
Compare Registers
Repeat Counter
YEAR, MTH, DAY
WKDAY
HR, MIN, SEC
MTH, DAY
WKDAY
HR, MIN, SECwith Masks
RTCC Interrupt Logic
AlarmEvent
32.768 kHz Inputfrom Secondary
0.5s
Alarm Pulse
RTCC Interrupt
RTCVAL
ALRMVAL
RTCC Pin
RTCOE
Oscillator (SOSC)
2009-2013 Microchip Technology Inc. DS60001156H-page 237
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25-16 CAL<9:0>: RTC Drift Calibration bits, which contain a signed 10-bit integer value
1111111111 = Minimum negative adjustment, subtracts 1 RTC clock pulse every one minute•••
1000000000 = Minimum negative adjustment, subtracts 512 clock pulses every one minute0111111111 = Maximum positive adjustment, adds 511 RTC clock pulses every one minute•••
0000000001 = Minimum positive adjustment, adds 1 RTC clock pulse every one minute0000000000 = No adjustment
bit 15 ON: RTCC On bit(1,2)
1 = RTCC module is enabled0 = RTCC module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Disables the PBCLK to the RTCC when CPU enters in Idle mode0 = Continue normal operation in Idle mode
bit 12-8 Unimplemented: Read as ‘0’
bit 7 RTSECSEL: RTCC Seconds Clock Output Select bit(3)
1 = RTCC Seconds Clock is selected for the RTCC pin0 = RTCC Alarm Pulse is selected for the RTCC pin
bit 6 RTCCLKON: RTCC Clock Enable Status bit
1 = RTCC Clock is actively running0 = RTCC Clock is not running
bit 5-4 Unimplemented: Read as ‘0’
Note 1: The ON bit is only writable when RTCWREN = 1.
2: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
3: Requires RTCOE = 1 (RTCCON<0>) for the output to be active.
4: The RTCWREN bit can only be set when the write sequence is enabled.
5: This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME<14:8>).
Note: This register is only reset on a Power-on Reset (POR).
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bit 3 RTCWREN: RTC Value Registers Write Enable bit(4)
1 = RTC Value registers can be written to by the user0 = RTC Value registers are locked out from being written to by the user
bit 2 RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = RTC Value registers can change while reading, due to a rollover ripple that results in an invalid dataread. If the register is read twice and results in the same data, the data can be assumed to be valid.
0 = RTC Value registers can be read without concern about a rollover ripple
bit 1 HALFSEC: Half-Second Status bit(5)
1 = Second half period of a second0 = First half period of a second
bit 0 RTCOE: RTCC Output Enable bit
1 = RTCC clock output is enabled (clock presented onto an I/O)0 = RTCC clock output is disabled
REGISTER 21-1: RTCCON: RTC CONTROL REGISTER (CONTINUED)
Note 1: The ON bit is only writable when RTCWREN = 1.
2: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
3: Requires RTCOE = 1 (RTCCON<0>) for the output to be active.
4: The RTCWREN bit can only be set when the write sequence is enabled.
5: This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME<14:8>).
Note: This register is only reset on a Power-on Reset (POR).
2009-2013 Microchip Technology Inc. DS60001156H-page 239
PIC32MX5XX/6XX/7XX
REGISTER 21-2: RTCALRM: RTC ALARM CONTROL REGISTER
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ALRMEN: Alarm Enable bit(1,2)
1 = Alarm is enabled0 = Alarm is disabled
bit 14 CHIME: Chime Enable bit(2)
1 = Chime is enabled – ARPT<7:0> is allowed to rollover from 0x00 to 0xFF0 = Chime is disabled – ARPT<7:0> stops once it reaches 0x00
bit 13 PIV: Alarm Pulse Initial Value bit(3)
When ALRMEN = 0, PIV is writable and determines the initial value of the Alarm Pulse.When ALRMEN = 1, PIV is read-only and returns the state of the Alarm Pulse.
bit 12 ALRMSYNC: Alarm Sync bit(3)
1 = ARPT<7:0> and ALRMEN may change as a result of a half second rollover during a read. The ARPT must be read repeatedly until the same value is read twice. This must be done since multiplebits may be changing, which are then synchronized to the PB clock domain.
0 = ARPT<7:0> and ALRMEN can be read without concerns of rollover because the prescaler is > 32 RTCclocks away from a half-second rollover
bit 11-8 AMASK<3:0>: Alarm Mask Configuration bits(2)
1111 = Reserved•••
1010 = Reserved1001 = Once a year (except when configured for February 29, once every four years)1000 = Once a month0111 = Once a week0110 = Once a day0101 = Every hour0100 = Every 10 minutes0011 = Every minute0010 = Every 10 seconds0001 = Every second0000 = Every half-second
Note 1: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and CHIME = 0.
2: This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC = 1.
3: This assumes a CPU read will execute in less than 32 PBCLKs.
Note: This register is only reset on a Power-on Reset (POR).
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bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits(2)
11111111 = Alarm will trigger 256 times•••
00000000 = Alarm will trigger one timeThe counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1.
REGISTER 21-2: RTCALRM: RTC ALARM CONTROL REGISTER (CONTINUED)
Note 1: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and CHIME = 0.
2: This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC = 1.
3: This assumes a CPU read will execute in less than 32 PBCLKs.
Note: This register is only reset on a Power-on Reset (POR).
2009-2013 Microchip Technology Inc. DS60001156H-page 241
• Up to 1 Msps conversion speed• Up to 16 analog input pins• External voltage reference input pins• One unipolar, differential Sample and Hold (S&H)
circuit
• Automatic Channel Scan mode• Selectable conversion trigger source• 16-word conversion result buffer• Selectable buffer fill modes• Eight conversion result format options • Operation during Sleep and Idle modes
A block diagram of the 10-bit ADC is illustrated inFigure 22-1. The 10-bit ADC has up to 16 analog inputpins, designated AN0-AN15. In addition, there are twoanalog input pins for external voltage referenceconnections. These voltage reference inputs may beshared with other analog input pins and may becommon to other analog module references.
The analog inputs are connected through two multi-plexers (MUXs) to one S&H. The analog input MUXscan be switched between two sets of analog inputsbetween conversions. Unipolar differential conversionsare possible on all channels, other than the pin used asthe reference, using a reference input pin (seeFigure 22-1).
The Analog Input Scan mode sequentially convertsuser-specified channels. A control register specifieswhich analog input channels will be included in thescanning sequence.
The 10-bit ADC is connected to a 16-word result buffer.Each 10-bit result is converted to one of eight 32-bitoutput formats when it is read from the result buffer.
FIGURE 22-1: ADC1 MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 17. “10-bitAnalog-to-Digital Converter (ADC)”(DS60001104) in the “PIC32 FamilyReference Manual”, which is availablefrom the Microchip web site(www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
SAR ADC
S&H
ADC1BUF0
ADC1BUF1
ADC1BUF2
ADC1BUFF
ADC1BUFE
AN0
AN15
AN1
VREFL
CH0SB<4:0>
CH0NA CH0NB
+
-CH0SA<4:0>
ChannelScan
CSCNA
Alternate
VREF+(1) AVDD AVSSVREF-(1)
Note 1: VREF+ and VREF- inputs can be multiplexed with other analog inputs.
Input Selection
VREFH VREFL
VCFG<2:0>
2009-2013 Microchip Technology Inc. DS60001156H-page 247
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: If ASAM = 0, software can write a ‘1’ to start sampling. This bit is automatically set by hardware if ASAM = 1. If SSRC<2:0> = 000, software can write a ‘0’ to end sampling and start conversion. If SSRC<2:0> ‘000’, this bit is automatically cleared by hardware to end sampling and start conversion.
3: This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can write a ‘0’ to clear this bit (a write of ‘1’ is not allowed). Clearing this bit does not affect any operation already in progress. This bit is automatically cleared by hardware at the start of a new conversion.
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PIC32MX5XX/6XX/7XX
bit 7-5 SSRC<2:0>: Conversion Trigger Source Select bits
111 = Internal counter ends sampling and starts conversion (auto convert)110 = Reserved101 = Reserved100 = Reserved011 = CTMU ends sampling and starts conversion010 = Timer 3 period match ends sampling and starts conversion001 = Active transition on INT0 pin ends sampling and starts conversion000 = Clearing the SAMP bit ends sampling and starts conversion
bit 4 CLRASAM: Stop Conversion Sequence bit (when the first ADC interrupt is generated)1 = Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the
ADC interrupt is generated.0 = Normal operation, buffer contents will be overwritten by the next conversion sequence
bit 3 Unimplemented: Read as ‘0’
bit 2 ASAM: ADC Sample Auto-Start bit
1 = Sampling begins immediately after last conversion completes; SAMP bit is automatically set0 = Sampling begins when SAMP bit is set
bit 1 SAMP: ADC Sample Enable bit(2)
1 = The ADC S&H circuit is sampling0 = The ADC S&H circuit is holdingWhen ASAM = 0, writing ‘1’ to this bit starts sampling. When SSRC<2:0> = 000, writing ‘0’ to this bit will end sampling and start conversion.
bit 0 DONE: Analog-to-Digital Conversion Status bit(3)
Clearing this bit will not affect any operation in progress.
1 = Analog-to-digital conversion is done0 = Analog-to-digital conversion is not done or has not started
REGISTER 22-1: AD1CON1: ADC CONTROL REGISTER 1 (CONTINUED)
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: If ASAM = 0, software can write a ‘1’ to start sampling. This bit is automatically set by hardware if ASAM = 1. If SSRC<2:0> = 000, software can write a ‘0’ to end sampling and start conversion. If SSRC<2:0> ‘000’, this bit is automatically cleared by hardware to end sampling and start conversion.
3: This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can write a ‘0’ to clear this bit (a write of ‘1’ is not allowed). Clearing this bit does not affect any operation already in progress. This bit is automatically cleared by hardware at the start of a new conversion.
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REGISTER 22-2: AD1CON2: ADC CONTROL REGISTER 2
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0
VCFG<2:0> OFFCAL — CSCNA — —
7:0R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BUFS — SMPI<3:0> BUFM ALTS
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits
Positive and negative inputs of the S&H circuit are connected to VREFL.0 = Disable Offset Calibration mode
The inputs to the S&H circuit are controlled by AD1CHS or AD1CSSL.
bit 11 Unimplemented: Read as ‘0’
bit 10 CSCNA: Input Scan Select bit1 = Scan inputs0 = Do not scan inputs
bit 9-8 Unimplemented: Read as ‘0’
bit 7 BUFS: Buffer Fill Status bitOnly valid when BUFM = 1.1 = ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x70 = ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF
bit 6 Unimplemented: Read as ‘0’
bit 5-2 SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence•••
0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence0000 = Interrupts at the completion of conversion for each sample/convert sequence
bit 1 BUFM: ADC Result Buffer Mode Select bit1 = Buffer configured as two 8-word buffers, ADC1BUF7-ADC1BUF0, ADC1BUFF-ADCBUF80 = Buffer configured as one 16-word buffer ADC1BUFF-ADC1BUF0
bit 0 ALTS: Alternate Input Sample Mode Select bit1 = Uses Sample A input multiplexer settings for first sample, and then alternates between Sample B and
Sample A input multiplexer settings for all subsequent samples0 = Always use Sample A input multiplexer settings
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PIC32MX5XX/6XX/7XX
REGISTER 22-3: AD1CON3: ADC CONTROL REGISTER 3
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADRC — — SAMC<4:0>(1)
7:0R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W R/W-0
ADCS<7:0>(2)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ADRC: ADC Conversion Clock Source bit
1 = Clock derived from FRC0 = Clock derived from Peripheral Bus Clock (PBCLK)
bit 14-13 Unimplemented: Read as ‘0’
bit 12-8 SAMC<4:0>: Auto-Sample Time bits(1)
11111 = 31 TAD
•
•
•
00001 =1 TAD
00000 =0 TAD (Not allowed)
bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits(2)
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CSSL<15:0>: ADC Input Pin Scan Selection bits(1)
1 = Select ANx for input scan0 = Skip ANx for input scan
Note 1: CSSL = ANx, where ‘x’ = 0-15.
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PIC32MX5XX/6XX/7XX
23.0 CONTROLLER AREA NETWORK (CAN)
The Controller Area Network (CAN) module supportsthe following key features:
• Standards Compliance:
- Full CAN 2.0B compliance
- Programmable bit rate up to 1 Mbps
• Message Reception and Transmission:
- 32 message FIFOs
- Each FIFO can have up to 32 messages for a total of 1024 messages
- FIFO can be a transmit message FIFO or a receive message FIFO
- User-defined priority levels for message FIFOs used for transmission
- 32 acceptance filters for message filtering
- Four acceptance filter mask registers for message filtering
- Automatic response to remote transmit request
- DeviceNet™ addressing support
• Additional Features:
- Loopback, Listen All Messages, and Listen Only modes for self-test, system diagnostics and bus monitoring
- Low-power operating modes
- CAN module is a bus master on the PIC32 system bus
- Use of DMA is not required
- Dedicated time-stamp timer
- Dedicated DMA channels
- Data-only Message Reception mode
Figure 23-1 illustrates the general structure of the CANmodule.
FIGURE 23-1: PIC32 CAN MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 34. “ControllerArea Network (CAN)” (DS60001154) inthe “PIC32 Family Reference Manual”,which is available from the Microchip website (www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
Message Buffer 31
Message Buffer 1
Message Buffer 0
Message Buffer 31
Message Buffer 1
Message Buffer 0
Message Buffer 31
Message Buffer 1
Message Buffer 0
FIFO0 FIFO1 FIFO31
System RAM
Up
to 3
2 M
ess
ag
e B
uffe
rs
CAN Message FIFO (up to 32 FIFOs)
MessageBuffer Size
2 or 4 Words
System Bus
CPU
CAN Module
32 Filters4 Masks
CxTX
CxRX
2009-2013 Microchip Technology Inc. DS60001156H-page 255
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-28 Unimplemented: Read as ‘0’
bit 27 ABAT: Abort All Pending Transmissions bit
1 = Signal all transmit buffers to abort transmission0 = Module will clear this bit when all transmissions aborted
bit 26-24 REQOP<2:0>: Request Operation Mode bits
111 = Set Listen All Messages mode110 = Reserved101 = Reserved100 = Set Configuration mode011 = Set Listen Only mode010 = Set Loopback mode001 = Set Disable mode000 = Set Normal Operation mode
bit 23-21 OPMOD<2:0>: Operation Mode Status bits
111 = Module is in Listen All Messages mode110 = Reserved101 = Reserved100 = Module is in Configuration mode011 = Module is in Listen Only mode010 = Module is in Loopback mode001 = Module is in Disable mode000 = Module is in Normal Operation mode
bit 20 CANCAP: CAN Message Receive Time Stamp Timer Capture Enable bit
1 = CANTMR value is stored on valid message reception and is stored with the message0 = Disable CAN message receive time stamp timer capture and stop CANTMR to conserve power
bit 19-16 Unimplemented: Read as ‘0’
bit 15 ON: CAN On bit(1)
1 = CAN module is enabled0 = CAN module is disabled
bit 14 Unimplemented: Read as ‘0’
Note 1: If the user application clears this bit, it may take a number of cycles before the CAN module completes the current transaction and responds to this request. The user application should poll the CANBUSY bit to verify that the request has been honored.
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bit 13 SIDLE: CAN Stop in Idle bit
1 = CAN Stops operation when system enters Idle mode0 = CAN continues operation when system enters Idle mode
bit 12 Unimplemented: Read as ‘0’
bit 11 CANBUSY: CAN Module is Busy bit
1 = The CAN module is active0 = The CAN module is completely disabled
bit 10-5 Unimplemented: Read as ‘0’
bit 4-0 DNCNT<4:0>: Device Net Filter Bit Number bits
10011-11111 = Invalid Selection (compare up to 18-bits of data with EID)10010 = Compare up to data byte 2 bit 6 with EID17 (CiRXFn<17>)
•
•
•
00001 = Compare up to data byte 0 bit 7 with EID0 (CiRXFn<0>)00000 = Do not compare data bytes
REGISTER 23-1: CiCON: CAN MODULE CONTROL REGISTER (CONTINUED)
Note 1: If the user application clears this bit, it may take a number of cycles before the CAN module completes the current transaction and responds to this request. The user application should poll the CANBUSY bit to verify that the request has been honored.
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REGISTER 23-2: CiCFG: CAN BAUD RATE CONFIGURATION REGISTER
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-23 Unimplemented: Read as ‘0’
bit 22 WAKFIL: CAN Bus Line Filter Enable bit
1 = Use CAN bus line filter for wake-up0 = CAN bus line filter is not used for wake-up
bit 21-19 Unimplemented: Read as ‘0’
bit 18-16 SEG2PH<2:0>: Phase Buffer Segment 2 bits(1,4)
111 = Length is 8 x TQ
•
•
•
000 = Length is 1 x TQ
bit 15 SEG2PHTS: Phase Segment 2 Time Select bit(1)
1 = Freely programmable0 = Maximum of SEG1PH or Information Processing Time, whichever is greater
bit 14 SAM: Sample of the CAN Bus Line bit(2)
1 = Bus line is sampled three times at the sample point0 = Bus line is sampled once at the sample point
bit 13-11 SEG1PH<2:0>: Phase Buffer Segment 1 bits(4)
111 = Length is 8 x TQ
•
•
•
000 = Length is 1 x TQ
Note 1: SEG2PH SEG1PH. If SEG2PHTS is clear, SEG2PH will be set automatically.
2: 3 Time bit sampling is not allowed for BRP < 2.
3: SJW SEG2PH.
4: The Time Quanta per bit must be greater than 7 (that is, TQBIT > 7).
Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>(CiCON<23:21>) = 100).
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bit 10-8 PRSEG<2:0>: Propagation Time Segment bits(4)
111 = Length is 8 x TQ
•
•
•
000 = Length is 1 x TQ
bit 7-6 SJW<1:0>: Synchronization Jump Width bits(3)
11 = Length is 4 x TQ
10 = Length is 3 x TQ
01 = Length is 2 x TQ
00 = Length is 1 x TQ
bit 5-0 BRP<5:0>: Baud Rate Prescaler bits
111111 = TQ = (2 x 64)/FSYS
111110 = TQ = (2 x 63)/FSYS
•
•
•
000001 = TQ = (2 x 2)/FSYS
000000 = TQ = (2 x 1)/FSYS
REGISTER 23-2: CiCFG: CAN BAUD RATE CONFIGURATION REGISTER (CONTINUED)
Note 1: SEG2PH SEG1PH. If SEG2PHTS is clear, SEG2PH will be set automatically.
2: 3 Time bit sampling is not allowed for BRP < 2.
3: SJW SEG2PH.
4: The Time Quanta per bit must be greater than 7 (that is, TQBIT > 7).
Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>(CiCON<23:21>) = 100).
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REGISTER 23-3: CiINT: CAN INTERRUPT REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
IVRIE WAKIE CERRIE SERRIE RBOVIE — — —
23:16U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — MODIE CTMRIE RBIE TBIE
15:8R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
IVRIF WAKIF CERRIF SERRIF(1) RBOVIF — — —
7:0U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — MODIF CTMRIF RBIF TBIF
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 IVRIE: Invalid Message Received Interrupt Enable bit1 = Interrupt request is enabled0 = Interrupt request is not enabled
bit 30 WAKIE: CAN Bus Activity Wake-up Interrupt Enable bit1 = Interrupt request is enabled0 = Interrupt request is not enabled
bit 29 CERRIE: CAN Bus Error Interrupt Enable bit1 = Interrupt request is enabled0 = Interrupt request is not enabled
bit 28 SERRIE: System Error Interrupt Enable bit1 = Interrupt request is enabled0 = Interrupt request is not enabled
bit 27 RBOVIE: Receive Buffer Overflow Interrupt Enable bit1 = Interrupt request is enabled0 = Interrupt request is not enabled
bit 26-20 Unimplemented: Read as ‘0’
bit 19 MODIE: Mode Change Interrupt Enable bit1 = Interrupt request is enabled0 = Interrupt request is not enabled
bit 18 CTMRIE: CAN Timestamp Timer Interrupt Enable bit1 = Interrupt request is enabled0 = Interrupt request is not enabled
bit 17 RBIE: Receive Buffer Interrupt Enable bit1 = Interrupt request is enabled0 = Interrupt request is not enabled
bit 16 TBIE: Transmit Buffer Interrupt Enable bit1 = Interrupt request is enabled0 = Interrupt request is not enabled
bit 15 IVRIF: Invalid Message Received Interrupt Flag bit1 = An invalid messages interrupt has occurred0 = An invalid message interrupt has not occurred
Note 1: This bit can only be cleared by turning the CAN module Off and On by clearing or setting the ON bit (CiCON<15>).
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bit 14 WAKIF: CAN Bus Activity Wake-up Interrupt Flag bit1 = A bus wake-up activity interrupt has occurred0 = A bus wake-up activity interrupt has not occurred
bit 13 CERRIF: CAN Bus Error Interrupt Flag bit1 = A CAN bus error has occurred0 = A CAN bus error has not occurred
bit 12 SERRIF: System Error Interrupt Flag bit
1 = A system error occurred (typically an illegal address was presented to the system bus)0 = A system error has not occurred
bit 11 RBOVIF: Receive Buffer Overflow Interrupt Flag bit
1 = A receive buffer overflow has occurred0 = A receive buffer overflow has not occurred
bit 10-4 Unimplemented: Read as ‘0’
bit 3 MODIF: CAN Mode Change Interrupt Flag bit
1 = A CAN module mode change has occurred (OPMOD<2:0> has changed to reflect REQOP)0 = A CAN module mode change has not occurred
bit 2 CTMRIF: CAN Timer Overflow Interrupt Flag bit
1 = A CAN timer (CANTMR) overflow has occurred0 = A CAN timer (CANTMR) overflow has not occurred
bit 1 RBIF: Receive Buffer Interrupt Flag bit
1 = A receive buffer interrupt is pending0 = A receive buffer interrupt is not pending
bit 0 TBIF: Transmit Buffer Interrupt Flag bit
1 = A transmit buffer interrupt is pending0 = A transmit buffer interrupt is not pending
REGISTER 23-3: CiINT: CAN INTERRUPT REGISTER (CONTINUED)
Note 1: This bit can only be cleared by turning the CAN module Off and On by clearing or setting the ON bit (CiCON<15>).
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REGISTER 23-4: CiVEC: CAN INTERRUPT CODE REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
— — — FILHIT<4:0>
7:0U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0
— ICODE<6:0>(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-13 Unimplemented: Read as ‘0’
bit 12-8 FILHIT<4:0>: Filter Hit Number bit
11111 = Filter 3111110 = Filter 30•••
00001 = Filter 100000 = Filter 0
bit 7 Unimplemented: Read as ‘0’
bit 6-0 ICODE<6:0>: Interrupt Flag Code bits(1)
1111111 = Reserved•••
1001001 = Reserved1001000 = Invalid message received (IVRIF)1000111 = CAN module mode change (MODIF)1000110 = CAN timestamp timer (CTMRIF)1000101 = Bus bandwidth error (SERRIF)1000100 = Address error interrupt (SERRIF)1000011 = Receive FIFO overflow interrupt (RBOVIF)1000010 = Wake-up interrupt (WAKIF)1000001 = Error Interrupt (CERRIF)1000000 = No interrupt0111111 = Reserved•••
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-21 SID<10:0>: Standard Identifier bits
1 = Include the SIDx bit in filter comparison0 = The SIDx bit is a ‘don’t care’ in filter operation
bit 20 Unimplemented: Read as ‘0’
bit 19 MIDE: Identifier Receive Mode bit
1 = Match only message types (standard/extended address) that correspond to the EXID bit in filter0 = Match either standard or extended address message if filters match (that is, if (Filter SID) = (Message
SID) or if (FILTER SID/EID) = (Message SID/EID))
bit 18 Unimplemented: Read as ‘0’
bit 17-0 EID<17:0>: Extended Identifier bits
1 = Include the EIDx bit in filter comparison0 = The EIDx bit is a ‘don’t care’ in filter operation
Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>(CiCON<23:21>) = 100).
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REGISTER 23-10: CiFLTCON0: CAN FILTER CONTROL REGISTER 0
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CiFIFOBA<31:0>: CAN FIFO Base Address bits
These bits define the base address of all message buffers. Individual message buffers are located basedon the size of the previous message buffers. This address is a physical address. Bits <1:0> are read-onlyand read as ‘0’, forcing the messages to be 32-bit word-aligned in device RAM.
Note 1: This bit is unimplemented and will always read ‘0’, which forces word-alignment of messages.
Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>(CiCON<23:21>) = 100).
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REGISTER 23-20: CiFIFOCONn: CAN FIFO CONTROL REGISTER ‘n’ (n = 0 THROUGH 31)
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-21 Unimplemented: Read as ‘0’
bit 20-16 FSIZE<4:0>: FIFO Size bits(1)
11111 = FIFO is 32 messages deep
•
•
•
00010 = FIFO is 3 messages deep00001 = FIFO is 2 messages deep00000 = FIFO is 1 message deep
bit 15 Unimplemented: Read as ‘0’
bit 14 FRESET: FIFO Reset bits
1 = FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user shouldpoll whether this bit is clear before taking any action.
0 = No effect
bit 13 UINC: Increment Head/Tail bit
TXEN = 1: (FIFO configured as a Transmit FIFO)When this bit is set the FIFO head will increment by a single message
TXEN = 0: (FIFO configured as a Receive FIFO)When this bit is set the FIFO tail will increment by a single message
bit 12 DONLY: Store Message Data Only bit(1)
TXEN = 1: (FIFO configured as a Transmit FIFO)This bit is not used and has no effect.
TXEN = 0: (FIFO configured as a Receive FIFO)1 = Only data bytes will be stored in the FIFO0 = Full message is stored, including identifier
bit 11-8 Unimplemented: Read as ‘0’
bit 7 TXEN: TX/RX Buffer Selection bit
1 = FIFO is a Transmit FIFO0 = FIFO is a Receive FIFO
Note 1: These bits can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits (CiCON<23:21>) = 100).
2: This bit is updated when a message completes (or aborts) or when the FIFO is reset.
3: This bit is reset on any read of this register or when the FIFO is reset.
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bit 6 TXABAT: Message Aborted bit(2)
1 = Message was aborted0 = Message completed successfully
bit 5 TXLARB: Message Lost Arbitration bit(3)
1 = Message lost arbitration while being sent0 = Message did not lose arbitration while being sent
bit 4 TXERR: Error Detected During Transmission bit(3)
1 = A bus error occured while the message was being sent0 = A bus error did not occur while the message was being sent
bit 3 TXREQ: Message Send Request
TXEN = 1: (FIFO configured as a Transmit FIFO)Setting this bit to ‘1’ requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent.Clearing the bit to ‘0’ while set (‘1’) will request a message abort.
TXEN = 0: (FIFO configured as a receive FIFO)This bit has no effect.
bit 2 RTREN: Auto RTR Enable bit
1 = When a remote transmit is received, TXREQ will be set0 = When a remote transmit is received, TXREQ will be unaffected
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26 TXNFULLIE: Transmit FIFO Not Full Interrupt Enable bit
1 = Interrupt enabled for FIFO not full0 = Interrupt disabled for FIFO not full
bit 25 TXHALFIE: Transmit FIFO Half Full Interrupt Enable bit
1 = Interrupt enabled for FIFO half full0 = Interrupt disabled for FIFO half full
bit 24 TXEMPTYIE: Transmit FIFO Empty Interrupt Enable bit
1 = Interrupt enabled for FIFO empty0 = Interrupt disabled for FIFO empty
bit 23-20 Unimplemented: Read as ‘0’
bit 19 RXOVFLIE: Overflow Interrupt Enable bit
1 = Interrupt enabled for overflow event0 = Interrupt disabled for overflow event
bit 18 RXFULLIE: Full Interrupt Enable bit
1 = Interrupt enabled for FIFO full0 = Interrupt disabled for FIFO full
bit 17 RXHALFIE: FIFO Half Full Interrupt Enable bit
1 = Interrupt enabled for FIFO half full0 = Interrupt disabled for FIFO half full
bit 16 RXNEMPTYIE: Empty Interrupt Enable bit
1 = Interrupt enabled for FIFO not empty0 = Interrupt disabled for FIFO not empty
bit 15-11 Unimplemented: Read as ‘0’
bit 10 TXNFULLIF: Transmit FIFO Not Full Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a transmit buffer)1 = FIFO is not full0 = FIFO is full
TXEN = 0: (FIFO configured as a receive buffer)Unused, reads ‘0’
Note 1: This bit is read-only and reflects the status of the FIFO.
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bit 9 TXHALFIF: FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a transmit buffer)1 = FIFO is half full0 = FIFO is > half full
TXEN = 0: (FIFO configured as a receive buffer)Unused, reads ‘0’
bit 8 TXEMPTYIF: Transmit FIFO Empty Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a transmit buffer)1 = FIFO is empty0 = FIFO is not empty, at least 1 message queued to be transmitted
TXEN = 0: (FIFO configured as a receive buffer)Unused, reads ‘0’
bit 7-4 Unimplemented: Read as ‘0’
bit 3 RXOVFLIF: Receive FIFO Overflow Interrupt Flag bit
TXEN = 1: (FIFO configured as a transmit buffer)Unused, reads ‘0’
TXEN = 0: (FIFO configured as a receive buffer)1 = Overflow event has occurred0 = No overflow event occured
bit 2 RXFULLIF: Receive FIFO Full Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a transmit buffer)Unused, reads ‘0’
TXEN = 0: (FIFO configured as a receive buffer)1 = FIFO is full0 = FIFO is not full
bit 1 RXHALFIF: Receive FIFO Half Full Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a transmit buffer)Unused, reads ‘0’
TXEN = 0: (FIFO configured as a receive buffer)1 = FIFO is half full0 = FIFO is < half full
bit 0 RXNEMPTYIF: Receive Buffer Not Empty Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a transmit buffer)Unused, reads ‘0’
TXEN = 0: (FIFO configured as a receive buffer)1 = FIFO is not empty, has at least 1 message0 = FIFO is empty
REGISTER 23-21: CiFIFOINTn: CAN FIFO INTERRUPT REGISTER ‘n’ (n = 0 THROUGH 31)
Note 1: This bit is read-only and reflects the status of the FIFO.
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REGISTER 23-22: CiFIFOUAn: CAN FIFO USER ADDRESS REGISTER ‘n’ (n = 0 THROUGH 31)
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24R-x R-x R-x R-x R-x R-x R-x R-x
CiFIFOUAn<31:24>
23:16R-x R-x R-x R-x R-x R-x R-x R-x
CiFIFOUAn<23:16>
15:8R-x R-x R-x R-x R-x R-x R-x R-x
CiFIFOUAn<15:8>
7:0R-x R-x R-x R-x R-x R-x R-0(1) R-0(1)
CiFIFOUAn<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CiFIFOUAn<31:0>: CAN FIFO User Address bits
TXEN = 1: (FIFO configured as a transmit buffer)
A read of this register will return the address where the next message is to be written (FIFO head).
TXEN = 0: (FIFO configured as a receive buffer)
A read of this register will return the address where the next message is to be read (FIFO tail).
Note 1: This bit will always read ‘0’, which forces byte-alignment of messages.
Note: This register is not guaranteed to read correctly in Configuration mode, and should only be accessed whenthe module is not in Configuration mode.
REGISTER 23-23: CiFIFOCIN: CAN MODULE MESSAGE INDEX REGISTER ‘n’ (n = 0 THROUGH 31)
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
— — — CiFIFOCI<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-5 Unimplemented: Read as ‘0’
bit 4-0 CiFIFOCIn<4:0>: CAN Side FIFO Message Index bits
TXEN = 1: (FIFO configured as a transmit buffer)A read of this register will return an index to the message that the FIFO will next attempt to transmit.
TXEN = 0: (FIFO configured as a receive buffer)A read of this register will return an index to the message that the FIFO will use to save the next message.
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24.0 ETHERNET CONTROLLER
The Ethernet controller is a bus master module thatinterfaces with an off-chip Physical Layer (PHY) toimplement a complete Ethernet node in a system.
Key features of the Ethernet Controller include:
• Supports 10/100 Mbps data transfer rates
• Supports full-duplex and half-duplex operation
• Supports RMII and MII PHY interface
• Supports MIIM PHY management interface
• Supports both manual and automatic Flow Control
• RAM descriptor-based DMA operation for both receive and transmit path
• Fully configurable interrupts
• Configurable receive packet filtering
- CRC check
- 64-byte pattern match
- Broadcast, multicast and unicast packets
- Magic Packet™
- 64-bit hash table
- Runt packet
• Supports packet payload checksum calculation
• Supports various hardware statistics counters
Figure 24-1 illustrates a block diagram of the Ethernetcontroller.
FIGURE 24-1: ETHERNET CONTROLLER BLOCK DIAGRAM
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 35. “EthernetController” (DS60001155) in the “PIC32Family Reference Manual”, which isavailable from the Microchip web site(www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
TX BusMaster
System
Bus
RX Bus Master
TX DMA
TX Flow Control
Host IF
RX DMA
RX Filter
Checksum
MAC ExternalPHY
MII/RMIIIF
MIIMIF
MAC Controland
ConfigurationRegisters
TX Function
RX Function
DMA Control
Registers
Fa
st Pe
riph
eral
Bu
s
Ethernet Controller
RX Flow Control
Ethernet DMA
RX BM
TX BMTX
F
IFO
RX
F
IFO
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R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 PTV<15:0>: PAUSE Timer Value bits
PAUSE Timer Value used for Flow Control. This register should only be written when RXEN (ETHCON1<8>) is not set.
These bits are only used for Flow Control operations.
bit 15 ON: Ethernet ON bit
1 = Ethernet module is enabled0 = Ethernet module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Ethernet Stop in Idle Mode bit
1 = Ethernet module transfers are paused during Idle mode0 = Ethernet module transfers continue during Idle mode
bit 12-10 Unimplemented: Read as ‘0’
bit 9 TXRTS: Transmit Request to Send bit
1 = Activate the TX logic and send the packet(s) defined in the TX EDT0 = Stop transmit (when cleared by software) or transmit done (when cleared by hardware)
After the bit is written with a ‘1’, it will clear to a ‘0’ whenever the transmit logic has finished transmittingthe requested packets in the Ethernet Descriptor Table (EDT). If a ‘0’ is written by the CPU, the transmitlogic finishes the current packet’s transmission and then stops any further.
This bit only affects TX operations.
bit 8 RXEN: Receive Enable bit(1)
1 = Enable RX logic, packets are received and stored in the RX buffer as controlled by the filter configuration
0 = Disable RX logic, no packets are received in the RX buffer
This bit only affects RX operations.
Note 1: It is not recommended to clear the RXEN bit and then make changes to any RX related field/register. The Ethernet Controller must be reinitialized (ON cleared to ‘0’), and then the RX changes applied.
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bit 7 AUTOFC: Automatic Flow Control bit
1 = Automatic Flow Control is enabled0 = Automatic Flow Control is disabled
Setting this bit will enable automatic Flow Control. If set, the full and empty watermarks are used toautomatically enable and disable the Flow Control, respectively. When the number of received buffersBUFCNT (ETHSTAT<16:23>) rises to the full watermark, Flow Control is automatically enabled. Whenthe BUFCNT falls to the empty watermark, Flow Control is automatically disabled.
This bit is only used for Flow Control operations and affects both TX and RX operations.
bit 6-5 Unimplemented: Read as ‘0’
bit 4 MANFC: Manual Flow Control bit
1 = Manual Flow Control is enabled0 = Manual Flow Control is disabled
Setting this bit will enable manual Flow Control. If set, the Flow Control logic will send a PAUSE frameusing the PAUSE timer value in the PTV register. It will then resend a PAUSE frame every 128 *PTV<15:0>/2 TX clock cycles until the bit is cleared.
Note: For 10 Mbps operation, TX clock runs at 2.5 MHz. For 100 Mbps operation, TX clock runs at25 MHz.
When this bit is cleared, the Flow Control logic will automatically send a PAUSE frame with a 0x0000PAUSE timer value to disable Flow Control.
This bit is only used for Flow Control operations and affects both TX and RX operations.
bit 3-1 Unimplemented: Read as ‘0’
bit 0 BUFCDEC: Descriptor Buffer Count Decrement bit
The BUFCDEC bit is a write-1 bit that reads as ‘0’. When written with a ‘1’, the Descriptor Buffer Counter,BUFCNT, will decrement by one. If BUFCNT is incremented by the RX logic at the same time that this bitis written, the BUFCNT value will remain unchanged. Writing a ‘0’ will have no effect.
This bit is only used for RX operations.
REGISTER 24-1: ETHCON1: ETHERNET CONTROLLER CONTROL REGISTER 1 (CONTINUED)
Note 1: It is not recommended to clear the RXEN bit and then make changes to any RX related field/register. The Ethernet Controller must be reinitialized (ON cleared to ‘0’), and then the RX changes applied.
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REGISTER 24-2: ETHCON2: ETHERNET CONTROLLER CONTROL REGISTER 2
Bit Range Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — RXBUFSZ<6:4>
7:0R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
RXBUFSZ<3:0> — — — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-11 Unimplemented: Read as ‘0’
bit 10-4 RXBUFSZ<6:0>: RX Data Buffer Size for All RX Descriptors (in 16-byte increments) bits
1111111 = RX data Buffer size for descriptors is 2032 bytes•••
1100000 = RX data Buffer size for descriptors is 1536 bytes•••
0000011 = RX data Buffer size for descriptors is 48 bytes0000010 = RX data Buffer size for descriptors is 32 bytes0000001 = RX data Buffer size for descriptors is 16 bytes0000000 = Reserved
bit 3-0 Unimplemented: Read as ‘0’
Note 1: This register is only used for RX operations.
2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0.
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bit 12 NOTPM: Pattern Match Inversion bit1 = The Pattern Match Checksum must not match for a successful Pattern Match to occur0 = The Pattern Match Checksum must match for a successful Pattern Match to occurThis bit determines whether Pattern Match Checksum must match in order for a successful Pattern Matchto occur.
bit 11-8 PMMODE<3:0>: Pattern Match Mode bits1001 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Packet = Magic Packet)(1,3)
1000 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND (Hash Table Filter match)(1,2)
0111 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND(Destination Address = Broadcast Address)(1)
0110 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND (Destination Address = Broadcast Address)(1)
0101 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND (Destination Address = Unicast Address)(1)
0100 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND (Destination Address = Unicast Address)(1)
0011 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND (Destination Address = Station Address)(1)
0010 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND(Destination Address = Station Address)(1)
0001 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches)(1)
0000 = Pattern Match is disabled; pattern match is always unsuccessful
Note 1: XOR = True when either one or the other conditions are true, but not both.2: This Hash Table Filter match is active regardless of the value of the HTEN bit.3: This Magic Packet Filter match is active regardless of the value of the MPEN bit.
Note 1: This register is only used for RX operations.
2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0.
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bit 7 CRCERREN: CRC Error Collection Enable bit1 = The received packet CRC must be invalid for the packet to be accepted0 = Disable CRC Error Collection filteringThis bit allows the user to collect all packets that have an invalid CRC.
bit 6 CRCOKEN: CRC OK Enable bit1 = The received packet CRC must be valid for the packet to be accepted0 = Disable CRC filteringThis bit allows the user to reject all packets that have an invalid CRC.
bit 5 RUNTERREN: Runt Error Collection Enable bit1 = The received packet must be a runt packet for the packet to be accepted0 = Disable Runt Error Collection filtering
This bit allows the user to collect all packets that are runt packets. For this filter, a runt packet is defined asany packet with a size of less than 64 bytes (when CRCOKEN = 0) or any packet with a size of less than64 bytes that has a valid CRC (when CRCOKEN = 1).
bit 4 RUNTEN: Runt Enable bit1 = The received packet must not be a runt packet for the packet to be accepted0 = Disable Runt filtering
This bit allows the user to reject all runt packets. For this filter, a runt packet is defined as any packet with asize of less than 64 bytes.
Note 1: XOR = True when either one or the other conditions are true, but not both.2: This Hash Table Filter match is active regardless of the value of the HTEN bit.3: This Magic Packet Filter match is active regardless of the value of the MPEN bit.
Note 1: This register is only used for RX operations.
2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0.
2009-2013 Microchip Technology Inc. DS60001156H-page 299
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-16 RXFWM<7:0>: Receive Full Watermark bits
The software controlled RX Buffer Full Watermark Pointer is compared against the RX BUFCNT todetermine the full watermark condition for the FWMARK interrupt and for enabling Flow Control whenautomatic Flow Control is enabled. The Full Watermark Pointer should always be greater than the EmptyWatermark Pointer.
bit 15-8 Unimplemented: Read as ‘0’
bit 7-0 RXEWM<7:0>: Receive Empty Watermark bits
The software controlled RX Buffer Empty Watermark Pointer is compared against the RX BUFCNT todetermine the empty watermark condition for the EWMARK interrupt and for disabling Flow Control whenautomatic Flow Control is enabled. The Empty Watermark Pointer should always be less than the FullWatermark Pointer.
Note: This register is only used for RX operations.
DS60001156H-page 300 2009-2013 Microchip Technology Inc.
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 14 TXBUSE: Transmit BVCI Bus Error Interrupt bit
1 = BVCI Bus Error has occurred0 = BVCI Bus Error has not occurred
This bit is set when the TX DMA encounters a BVCI Bus error during a memory access. It is cleared byeither a Reset or CPU write of a ‘1’ to the CLR register.
bit 13 RXBUSE: Receive BVCI Bus Error Interrupt bit
1 = BVCI Bus Error has occurred0 = BVCI Bus Error has not occurred
This bit is set when the RX DMA encounters a BVCI Bus error during a memory access. It is cleared byeither a Reset or CPU write of a ‘1’ to the CLR register.
bit 12-10 Unimplemented: Read as ‘0’
bit 9 EWMARK: Empty Watermark Interrupt bit
1 = Empty Watermark pointer reached0 = No interrupt pending
This bit is set when the RX Descriptor Buffer Count is less than or equal to the value in theRXEWM bit (ETHRXWM<0:7>) value. It is cleared by BUFCNT bit (ETHSTAT<16:23>)being incremented by hardware. Writing a ‘0’ or a ‘1’ has no effect.
bit 8 FWMARK: Full Watermark Interrupt bit
1 = Full Watermark pointer reached0 = No interrupt pending
This bit is set when the RX Descriptor Buffer Count is greater than or equal to the value in the RXFWMbit (ETHRXWM<16:23>) field. It is cleared by writing the BUFCDEC (ETHCON1<0>) bit to decrementthe BUFCNT counter. Writing a ‘0’ or a ‘1’ has no effect.
bit 7 RXDONE: Receive Done Interrupt bit
1 = RX packet was successfully received0 = No interrupt pending
This bit is set whenever an RX packet is successfully received. It is cleared by either a Reset or CPUwrite of a ‘1’ to the CLR register.
Note: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting orclearing any bits in this register should only be done for debug/test purposes.
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bit 6 PKTPEND: Packet Pending Interrupt bit
1 = RX packet pending in memory0 = RX packet is not pending in memory
This bit is set when the BUFCNT counter has a value other than ‘0’. It is cleared by either a Reset or bywriting the BUFCDEC bit to decrement the BUFCNT counter. Writing a ‘0’ or a ‘1’ has no effect.
bit 5 RXACT: Receive Activity Interrupt bit
1 = RX packet data was successfully received0 = No interrupt pending
This bit is set whenever RX packet data is stored in the RXBM FIFO. It is cleared by either a Reset orCPU write of a ‘1’ to the CLR register.
bit 4 Unimplemented: Read as ‘0’
bit 3 TXDONE: Transmit Done Interrupt bit
1 = TX packet was successfully sent0 = No interrupt pending
This bit is set when the currently transmitted TX packet completes transmission, and the Transmit StatusVector is loaded into the first descriptor used for the packet. It is cleared by either a Reset or CPU writeof a ‘1’ to the CLR register.
bit 2 TXABORT: Transmit Abort Condition Interrupt bit
1 = TX abort condition occurred on the last TX packet0 = No interrupt pending
This bit is set when the MAC aborts the transmission of a TX packet for one of the following reasons:
• Jumbo TX packet abort
• Underrun abort
• Excessive defer abort
• Late collision abort
• Excessive collisions abort
This bit is cleared by either a Reset or CPU write of a ‘1’ to the CLR register.
bit 1 RXBUFNA: Receive Buffer Not Available Interrupt bit
1 = RX Buffer Descriptor Not Available condition has occurred0 = No interrupt pending
This bit is set by a RX Buffer Descriptor Overrun condition. It is cleared by either a Reset or a CPU writeof a ‘1’ to the CLR register.
bit 0 RXOVFLW: Receive FIFO Over Flow Error bit
1 = RX FIFO Overflow Error condition has occurred0 = No interrupt pending
RXOVFLW is set by the RXBM Logic for an RX FIFO Overflow condition. It is cleared by either a Resetor CPU write of a ‘1’ to the CLR register.
Note: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting orclearing any bits in this register should only be done for debug/test purposes.
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REGISTER 24-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-16 BUFCNT<7:0>: Packet Buffer Count bits
Number of packet buffers received in memory. Once a packet has been successfully received, this registeris incremented by hardware based on the number of descriptors used by the packet. Software decrementsthe counter (by writing to the BUFCDEC bit (ETHCON1<0>) for each descriptor used) after a packet hasbeen read out of the buffer. The register does not roll over (0xFF to 0x00) when hardware tries to incrementthe register and the register is already at 0xFF. Conversely, the register does not roll under (0x00 to 0xFF)when software tries to decrement the register and the register is already at 0x0000. When software attemptsto decrement the counter at the same time that the hardware attempts to increment the counter, the countervalue will remain unchanged.
When this register value reaches 0xFF, the RX logic will halt (only if automatic Flow Control is enabled)awaiting software to write the BUFCDEC bit in order to decrement the register below 0xFF.
If automatic Flow Control is disabled, the RXDMA will continue processing and the BUFCNT will saturate ata value of 0xFF.
When this register is non-zero, the PKTPEND status bit will be set and an interrupt may be generated,depending on the value of the ETHIEN bit <PKTPENDIE> register.
When the ETHRXST register is written, the BUFCNT counter is automatically cleared to 0x00.
Note: BUFCNT will not be cleared when ON is set to ‘0’. This enables software to continue to utilize and decrement this count.
bit 15-8 Unimplemented: Read as ‘0’
bit 7 ETHBUSY: Ethernet Module busy bit(1)
1 = Ethernet logic has been turned on (ON (ETHCON1<15>) = 1) or is completing a transaction0 = Ethernet logic is idle
This bit indicates that the module has been turned on or is completing a transaction after being turned off.
bit 6 TXBUSY: Transmit Busy bit(2)
1 = TX logic is receiving data0 = TX logic is idle
This bit indicates that a packet is currently being transmitted. A change in this status bit is not necessarilyreflected by the TXDONE interrupt, as TX packets may be aborted or rejected by the MAC.
Note 1: This bit will be set when the ON bit (ETHCON1<15>) = 1.
2: This bit will be cleared when the ON bit (ETHCON1<15>) = 0.
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bit 5 RXBUSY: Receive Busy bit(2)
1 = RX logic is receiving data0 = RX logic is idle
This bit indicates that a packet is currently being received. A change in this status bit is not necessarilyreflected by the RXDONE interrupt, as RX packets may be aborted or rejected by the RX filter.
bit 4-0 Unimplemented: Read as ‘0’
REGISTER 24-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER (CONTINUED)
Note 1: This bit will be set when the ON bit (ETHCON1<15>) = 1.
2: This bit will be cleared when the ON bit (ETHCON1<15>) = 0.
2009-2013 Microchip Technology Inc. DS60001156H-page 305
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 RXOVFLWCNT<15:0>: Dropped Receive Frames Count bits
Increment counter for frames accepted by the RX filter and subsequently dropped due to internal receiveerror (RXFIFO overrun). This event also sets the RXOVFLW bit (ETHIRQ<0>) interrupt flag.
Note 1: This register is only used for RX operations.
2: This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are ‘0’.
3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should only be done for debug/test purposes.
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REGISTER 24-17: ETHFRMTXOK: ETHERNET CONTROLLER FRAMES TRANSMITTED OK STATISTICS REGISTER
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 FRMTXOKCNT<15:0>: Frame Transmitted OK Count bits
Increment counter for frames successfully transmitted.
Note 1: This register is only used for TX operations.
2: This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are ‘0’.
3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should only be done for debug/test purposes.
2009-2013 Microchip Technology Inc. DS60001156H-page 307
PIC32MX5XX/6XX/7XX
REGISTER 24-18: ETHSCOLFRM: ETHERNET CONTROLLER SINGLE COLLISION FRAMES STATISTICS REGISTER
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 SCOLFRMCNT<15:0>: Single Collision Frame Count bits
Increment count for frames that were successfully transmitted on the second try.
Note 1: This register is only used for TX operations.
2: This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are ‘0’.
3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should only be done for debug/test purposes.
DS60001156H-page 308 2009-2013 Microchip Technology Inc.
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 MCOLFRMCNT<15:0>: Multiple Collision Frame Count bits
Increment count for frames that were successfully transmitted after there was more than one collision.
Note 1: This register is only used for TX operations.
2: This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are ‘0’.
3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should only be done for debug/test purposes.
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REGISTER 24-20: ETHFRMRXOK: ETHERNET CONTROLLER FRAMES RECEIVED OK STATISTICS REGISTER
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 FRMRXOKCNT<15:0>: Frames Received OK Count bits
Increment count for frames received successfully by the RX Filter. This count will not be incremented ifthere is a Frame Check Sequence (FCS) or Alignment error.
Note 1: This register is only used for RX operations.
2: This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are ‘0’.
3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should only be done for debug/test purposes.
DS60001156H-page 310 2009-2013 Microchip Technology Inc.
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 FCSERRCNT<15:0>: FCS Error Count bits
Increment count for frames received with FCS error and the frame length in bits is an integral multiple of8 bits.
Note 1: This register is only used for RX operations.
2: This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are ‘0’.
3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should be only done for debug/test purposes.
2009-2013 Microchip Technology Inc. DS60001156H-page 311
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 ALGNERRCNT<15:0>: Alignment Error Count bits
Increment count for frames with alignment errors. Note that an alignment error is a frame that has an FCSerror and the frame length in bits is not an integral multiple of 8 bits (a.k.a., dribble nibble)
Note 1: This register is only used for RX operations.
2: This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are ‘0’.
3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should be only done for debug/test purposes.
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PIC32MX5XX/6XX/7XX
REGISTER 24-23: EMAC1CFG1: ETHERNET CONTROLLER MAC CONFIGURATION 1 REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8R/W-1 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
SOFTRESET
SIMRESET
— —RESETRMCS
RESETRFUN
RESETTMCS
RESETTFUN
7:0U-0 U-0 U-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1
— — — LOOPBACKTX
PAUSERX
PAUSEPASSALL
RXENABLE
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 SOFTRESET: Soft Reset bit
Setting this bit will put the MACMII in reset. Its default value is ‘1’.
bit 14 SIMRESET: Simulation Reset bit
Setting this bit will cause a reset to the random number generator within the Transmit Function.
bit 13-12 Unimplemented: Read as ‘0’
bit 11 RESETRMCS: Reset MCS/RX bit
Setting this bit will put the MAC Control Sub-layer/Receive domain logic in reset.
bit 10 RESETRFUN: Reset RX Function bit
Setting this bit will put the MAC Receive function logic in reset.
bit 9 RESETTMCS: Reset MCS/TX bit
Setting this bit will put the MAC Control Sub-layer/TX domain logic in reset.
bit 8 RESETTFUN: Reset TX Function bit
Setting this bit will put the MAC Transmit function logic in reset.
bit 7-5 Unimplemented: Read as ‘0’
bit 4 LOOPBACK: MAC Loopback mode bit
1 = MAC Transmit interface is loop backed to the MAC Receive interface0 = MAC normal operation
bit 3 TXPAUSE: MAC TX Flow Control bit
1 = PAUSE Flow Control frames are allowed to be transmitted0 = PAUSE Flow Control frames are blocked
bit 2 RXPAUSE: MAC RX Flow Control bit
1 = The MAC acts upon received PAUSE Flow Control frames0 = Received PAUSE Flow Control frames are ignored
bit 1 PASSALL: MAC Pass all Receive Frames bit
1 = The MAC will accept all frames regardless of type (Normal vs. Control)0 = The received Control frames are ignored
bit 0 RXENABLE: MAC Receive Enable bit
1 = Enable the MAC receiving of frames0 = Disable the MAC receiving of frames
Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
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REGISTER 24-24: EMAC1CFG2: ETHERNET CONTROLLER MAC CONFIGURATION 2 REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit25/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0
—EXCESS
DFRBPNOBK
OFFNOBKOFF
— — LONGPRE PUREPRE
7:0
R/W-1 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0
AUTOPAD(1,2)
VLANPAD(1,2)
PADENABLE(1,3)
CRCENABLE
DELAYCRC HUGEFRM LENGTHCK FULLDPLX
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 14 EXCESSDER: Excess Defer bit
1 = The MAC will defer to carrier indefinitely as per the Standard0 = The MAC will abort when the excessive deferral limit is reached
bit 13 BPNOBKOFF: Backpressure/No Backoff bit
1 = The MAC after incidentally causing a collision during backpressure will immediately retransmit withoutbackoff reducing the chance of further collisions and ensuring transmit packets get sent
0 = The MAC will not remove the backoff
bit 12 NOBKOFF: No Backoff bit
1 = Following a collision, the MAC will immediately retransmit rather than using the Binary Exponential Back-off algorithm as specified in the Standard
0 = Following a collision, the MAC will use the Binary Exponential Backoff algorithm
bit 11-10 Unimplemented: Read as ‘0’
bit 9 LONGPRE: Long Preamble Enforcement bit
1 = The MAC only allows receive packets which contain preamble fields less than 12 bytes in length0 = The MAC allows any length preamble as per the Standard
bit 8 PUREPRE: Pure Preamble Enforcement bit
1 = The MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet witherrors in its preamble is discarded
0 = The MAC does not perform any preamble checking
bit 7 AUTOPAD: Automatic Detect Pad Enable bit(1,2)
1 = The MAC will automatically detect the type of frame, either tagged or untagged, by comparing the twooctets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly
0 = The MAC does not perform automatic detection
Note 1: Table 24-5 provides a description of the pad function based on the configuration of this register.
2: This bit is ignored if the PADENABLE bit is cleared.
3: This bit is used in conjunction with the AUTOPAD and VLANPAD bits.
Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware
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TABLE 24-5: PAD OPERATION
bit 6 VLANPAD: VLAN Pad Enable bit(1,2)
1 = The MAC will pad all short frames to 64 bytes and append a valid CRC0 = The MAC does not perform padding of short frames
bit 5 PADENABLE: Pad/CRC Enable bit(1,3)
1 = The MAC will pad all short frames0 = The frames presented to the MAC have a valid length
bit 4 CRCENABLE: CRC Enable1 bit
1 = The MAC will append a CRC to every frame whether padding was required or not. Must be set if thePADENABLE bit is set.
0 = The frames presented to the MAC have a valid CRC
bit 3 DELAYCRC: Delayed CRC bit
This bit determines the number of bytes, if any, of proprietary header information that exist on the front of theIEEE 802.3 frames.
1 = Four bytes of header (ignored by the CRC function)0 = No proprietary header
bit 2 HUGEFRM: Huge Frame enable bit
1 = Frames of any length are transmitted and received0 = Huge frames are not allowed for receive or transmit
bit 1 LENGTHCK: Frame Length checking bit
1 = Both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type fieldrepresents a length then the check is performed. Mismatches are reported on the transmit/receivestatistics vector.
0 = Length/Type field check is not performed
bit 0 FULLDPLX: Full-Duplex Operation bit
1 = The MAC operates in Full-Duplex mode0 = The MAC operates in Half-Duplex mode
REGISTER 24-24: EMAC1CFG2: ETHERNET CONTROLLER MAC CONFIGURATION 2 REGISTER
Note 1: Table 24-5 provides a description of the pad function based on the configuration of this register.
2: This bit is ignored if the PADENABLE bit is cleared.
3: This bit is used in conjunction with the AUTOPAD and VLANPAD bits.
Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware
Type AUTOPAD VLANPAD PADENABLE Action
Any x x 0 No pad, check CRC
Any 0 0 1 Pad to 60 Bytes, append CRC
Any x 1 1 Pad to 64 Bytes, append CRC
Any 1 0 1 If untagged: Pad to 60 Bytes, append CRCIf VLAN tagged: Pad to 64 Bytes, append CRC
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REGISTER 24-25: EMAC1IPGT: ETHERNET CONTROLLER MAC BACK-TO-BACK INTERPACKET GAP REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0U-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0
— B2BIPKTGP<6:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-7 Unimplemented: Read as ‘0’
bit 6-0 B2BIPKTGP<6:0>: Back-to-Back Interpacket Gap bits
This is a programmable field representing the nibble time offset of the minimum possible period betweenthe end of any transmitted packet, to the beginning of the next. In Full-Duplex mode, the register valueshould be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be thedesired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which rep-resents the minimum IPG of 0.96 µs (in 100 Mbps) or 9.6 µs (in 10 Mbps). In Half-Duplex mode, the rec-ommended setting is 0x12 (18d), which also represents the minimum IPG of 0.96 µs (in 100 Mbps) or 9.6µs (in 10 Mbps).
Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
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REGISTER 24-26: EMAC1IPGR: ETHERNET CONTROLLER MAC NON-BACK-TO-BACK INTERPACKET GAP REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0
— NB2BIPKTGP1<6:0>
7:0U-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0
— NB2BIPKTGP2<6:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 14-8 NB2BIPKTGP1<6:0>: Non-Back-to-Back Interpacket Gap Part 1 bits
This is a programmable field representing the optional carrierSense window referenced in section4.2.3.2.1 “Deference” of the IEEE 80.23 Specification. If the carrier is detected during the timing of IPGR1,the MAC defers to the carrier. If, however, the carrier comes after IPGR1, the MAC continues timing IPGR2and transmits, knowingly causing a collision, thus ensuring fair access to the medium. Its range of valuesis 0x0 to IPGR2. Its recommend value is 0xC (12d).
bit 7 Unimplemented: Read as ‘0’
bit 6-0 NB2BIPKTGP2<6:0>: Non-Back-to-Back Interpacket Gap Part 2 bits
This is a programmable field representing the non-back-to-back Inter-Packet-Gap. Its recommended valueis 0x12 (18d), which represents the minimum IPG of 0.96 µs (in 100 Mbps) or 9.6 µs (in 10 Mbps).
Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
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REGISTER 24-27: EMAC1CLRT: ETHERNET CONTROLLER MAC COLLISION WINDOW/RETRY LIMIT REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8U-0 U-0 R/W-1 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1
— — CWINDOW<5:0>
7:0U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1
— — — — RETX<3:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-14 Unimplemented: Read as ‘0’
bit 13-8 CWINDOW<5:0>: Collision Window bits
This is a programmable field representing the slot time or collision window during which collisions occur inproperly configured networks. Since the collision window starts at the beginning of transmission, the pre-amble and SFD is included. Its default of 0x37 (55d) corresponds to the count of frame bytes at the end ofthe window.
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 RETX<3:0>: Retransmission Maximum bits
This is a programmable field specifying the number of retransmission attempts following a collision beforeaborting the packet due to excessive collisions. The Standard specifies the maximum number of attempts(attemptLimit) to be 0xF (15d). Its default is ‘0xF’.
Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
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REGISTER 24-28: EMAC1MAXF: ETHERNET CONTROLLER MAC MAXIMUM FRAME LENGTH REGISTER
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 MACMAXF<15:0>: Maximum Frame Length bits(1)
These bits reset to 0x05EE, which represents a maximum receive frame of 1518 octets. An untaggedmaximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. Ifa shorter/longer maximum length restriction is desired, program this 16-bit field.
Note 1: If a proprietary header is allowed, this bit should be adjusted accordingly. For example, if 4-byte headers are prepended to frames, MACMAXF could be set to 1527 octets. This would allow the maximum VLAN tagged frame plus the 4-byte header.
Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
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REGISTER 24-29: EMAC1SUPP: ETHERNET CONTROLLER MAC PHY SUPPORT REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0
— — — — RESETRMII(1) — — SPEEDRMII(1)
7:0U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-12 Unimplemented: Read as ‘0’
bit 11 RESETRMII: Reset RMII Logic bit(1)
1 = Reset the MAC RMII module0 = Normal operation.
bit 10-9 Unimplemented: Read as ‘0’
bit 8 SPEEDRMII: RMII Speed bit(1)
This bit configures the Reduced MII logic for the current operating speed.
1 = RMII is running at 100 Mbps0 = RMII is running at 10 Mbps
bit 7-0 Unimplemented: Read as ‘0’
Note 1: This bit is only used for the RMII module.
Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
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REGISTER 24-30: EMAC1TEST: ETHERNET CONTROLLER MAC TEST REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — TESTBP TESTPAUSE(1) SHRTQNTA(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-3 Unimplemented: Read as ‘0’
bit 2 TESTBP: Test Backpressure bit
1 = The MAC will assert backpressure on the link. Backpressure causes preamble to be transmitted, raisingcarrier sense. A transmit packet from the system will be sent during backpressure.
0 = Normal operation
bit 1 TESTPAUSE: Test PAUSE bit(1)
1 = The MAC Control sub-layer will inhibit transmissions, just as if a PAUSE Receive Control frame with anon-zero pause time parameter was received
0 = Normal operation
bit 0 SHRTQNTA: Shortcut PAUSE Quanta bit(1)
1 = The MAC reduces the effective PAUSE Quanta from 64 byte-times to 1 byte-time0 = Normal operation
Note 1: This bit is only for testing purposes.
Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
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TABLE 24-6: MIIM CLOCK SELECTION
REGISTER 24-31: EMAC1MCFG: ETHERNET CONTROLLER MAC MII MANAGEMENT CONFIGURATION REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
RESETMGMT — — — — — — —
7:0U-0 U-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CLKSEL<3:0>(1) NOPRE SCANINC
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 RESETMGMT: Test Reset MII Management bit
1 = Reset the MII Management module0 = Normal Operation
bit 14-6 Unimplemented: Read as ‘0’
bit 5-2 CLKSEL<3:0>: MII Management Clock Select 1 bits(1)
These bits are used by the clock divide logic in creating the MII Management Clock (MDC), which the IEEE802.3 Specification defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz.
bit 1 NOPRE: Suppress Preamble bit
1 = The MII Management will perform read/write cycles without the 32-bit preamble field. Some PHYssupport suppressed preamble
0 = Normal read/write cycles are performed
bit 0 SCANINC: Scan Increment bit
1 = The MII Management module will perform read cycles across a range of PHYs. The read cycles will startfrom address 1 through the value set in EMAC1MADR<PHYADDR>
0 = Continuous reads of the same PHY
Note 1: Table 24-6 provides a description of the clock divider encoding.
Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
MIIM Clock Select EMAC1MCFG<5:2>
SYSCLK divided by 4 000x
SYSCLK divided by 6 0010
SYSCLK divided by 8 0011
SYSCLK divided by 10 0100
SYSCLK divided by 14 0101
SYSCLK divided by 20 0110
SYSCLK divided by 28 0111
SYSCLK divided by 40 1000
Undefined Any other combination
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REGISTER 24-32: EMAC1MCMD: ETHERNET CONTROLLER MAC MII MANAGEMENT COMMAND REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — SCAN READ
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-2 Unimplemented: Read as ‘0’
bit 1 SCAN: MII Management Scan Mode bit
1 = The MII Management module will perform read cycles continuously (for example, useful for monitoringthe Link Fail)
0 = Normal Operation
bit 0 READ: MII Management Read Command bit1 = The MII Management module will perform a single read cycle. The read data is returned in the
EMAC1MRDD register0 = The MII Management module will perform a write cycle. The write data is taken from the EMAC1MWTD
register
Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
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REGISTER 24-33: EMAC1MADR: ETHERNET CONTROLLER MAC MII MANAGEMENT ADDRESS REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1
— — — PHYADDR<4:0>
7:0U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — REGADDR<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-13 Unimplemented: Read as ’0’
bit 12-8 PHYADDR<4:0>: MII Management PHY Address bits
This field represents the 5-bit PHY Address field of Management cycles. Up to 31 PHYs can be addressed(0 is reserved).
bit 7-5 Unimplemented: Read as ’0’
bit 4-0 REGADDR<4:0>: MII Management Register Address bits
This field represents the 5-bit Register Address field of Management cycles. Up to 32 registers can beaccessed.
Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
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REGISTER 24-34: EMAC1MWTD: ETHERNET CONTROLLER MAC MII MANAGEMENT WRITE DATA REGISTER
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ’0’
bit 15-0 MWTD<15:0>: MII Management Write Data bits
When written, a MII Management write cycle is performed using the 16-bit data and the pre-configured PHYand Register addresses from the EMAC1MADR register.
Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
REGISTER 24-35: EMAC1MRDD: ETHERNET CONTROLLER MAC MII MANAGEMENT READ DATA REGISTER
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 MRDD<15:0>: MII Management Read Data bits
Following a MII Management Read Cycle, the 16-bit data can be read from this location.
Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
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REGISTER 24-36: EMAC1MIND: ETHERNET CONTROLLER MAC MII MANAGEMENT INDICATORS REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — LINKFAIL NOTVALID SCAN MIIMBUSY
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-4 Unimplemented: Read as ‘0’
bit 3 LINKFAIL: Link Fail bit
When ‘1’ is returned - indicates link fail has occurred. This bit reflects the value last read from the PHY statusregister.
bit 2 NOTVALID: MII Management Read Data Not Valid bit
When ‘1’ is returned - indicates an MII management read cycle has not completed and the Read Data is notyet valid.
bit 1 SCAN: MII Management Scanning bit
When ‘1’ is returned - indicates a scan operation (continuous MII Management Read cycles) is in progress.
bit 0 MIIMBUSY: MII Management Busy bit
When ‘1’ is returned - indicates MII Management module is currently performing an MII Management Reador Write cycle.
Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
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REGISTER 24-37: EMAC1SA0: ETHERNET CONTROLLER MAC STATION ADDRESS 0 REGISTER
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-8 STNADDR6<7:0>: Station Address Octet 6 bits
These bits hold the sixth transmitted octet of the station address.
bit 7-0 STNADDR5<7:0>: Station Address Octet 5 bits
These bits hold the fifth transmitted octet of the station address.
Note 1: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
2: This register is loaded at reset from the factory preprogrammed station address.
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REGISTER 24-38: EMAC1SA1: ETHERNET CONTROLLER MAC STATION ADDRESS 1 REGISTER
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-8 STNADDR4<7:0>: Station Address Octet 4 bits
These bits hold the fourth transmitted octet of the station address.
bit 7-0 STNADDR3<7:0>: Station Address Octet 3 bits
These bits hold the third transmitted octet of the station address.
Note 1: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
2: This register is loaded at reset from the factory preprogrammed station address.
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REGISTER 24-39: EMAC1SA2: ETHERNET CONTROLLER MAC STATION ADDRESS 2 REGISTER
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Reserved: Maintain as ‘0’; ignore read
bit 15-8 STNADDR2<7:0>: Station Address Octet 2 bits
These bits hold the second transmitted octet of the station address.
bit 7-0 STNADDR1<7:0>: Station Address Octet 1 bits
These bits hold the most significant (first transmitted) octet of the station address.
Note 1: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
2: This register is loaded at reset from the factory preprogrammed station address.
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NOTES:
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25.0 COMPARATOR The Comparator module contains two comparators thatcan be configured in a variety of ways.
Key features of the Comparator module include:
• Selectable inputs available include:
- Analog inputs multiplexed with I/O pins
- On-chip internal absolute voltage reference (IVREF)
- Comparator voltage reference (CVREF)
• Outputs can be inverted
• Selectable interrupt generation
A block diagram of the Comparator module isillustrated in Figure 25-1.
FIGURE 25-1: COMPARATOR MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in thisdata sheet, refer to Section 19.“Comparator” (DS60001110) in the“PIC32 Family Reference Manual”, whichis available from the Microchip web site(www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
C1
CVREF(2)C1IN+(1)
C1IN+
C1IN-
C1OUT
COUT (CM1CON<8>)CREF
CCH<1:0>
CPOL
COE
ON
C2IN+
IVREF(2)
C1OUT (CMSTAT<0>)
C2
CVREF(2)C2IN+
C2IN+
C2IN-
C2OUT
COUT (CM2CON<8>)CREF
CPOL
COE
ON
C1IN+
IVREF(2)
C2OUT (CMSTAT<1>)
Comparator 2
Comparator 1
CCH<1:0>
Note 1: On devices with a USB module, and when the module is enabled, this pin is controlled by the USB module,and therefore, is not available as a comparator input.
2: Internally connected. See Section 26.0 “Comparator Voltage Reference (CVREF)”.
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REGISTER 25-1: CMxCON: COMPARATOR ‘x’ CONTROL REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R-0
ON(1) COE CPOL(2) — — — — COUT
7:0R/W-1 R/W-1 U-0 R/W-0 U-0 U-0 R/W-1 R/W-1
EVPOL<1:0> — CREF — — CCH<1:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: Comparator ON bit(1)
Clearing this bit does not affect the other bits in this register.
1 = Module is enabled. Setting this bit does not affect the other bits in this register0 = Module is disabled and does not consume current.
bit 14 COE: Comparator Output Enable bit
1 = Comparator output is driven on the output CxOUT pin0 = Comparator output is not driven on the output CxOUT pin
bit 13 CPOL: Comparator Output Inversion bit(2)
1 = Output is inverted0 = Output is not inverted
bit 12-9 Unimplemented: Read as ‘0’
bit 8 COUT: Comparator Output bit
1 = Output of the Comparator is a ‘1’0 = Output of the Comparator is a ‘0’
bit 7-6 EVPOL<1:0>: Interrupt Event Polarity Select bits
11 = Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output10 = Comparator interrupt is generated on a high-to-low transition of the comparator output01 = Comparator interrupt is generated on a low-to-high transition of the comparator output00 = Comparator interrupt generation is disabled
bit 5 Unimplemented: Read as ‘0’
bit 4 CREF: Comparator Positive Input Configure bit
1 = Comparator non-inverting input is connected to the internal CVREF
0 = Comparator non-inverting input is connected to the CXIN+ pin
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 CCH<1:0>: Comparator Negative Input Select bits for Comparator
11 = Comparator inverting input is connected to the IVREF
10 = Comparator inverting input is connected to the C2IN+ pin for C1 and C1IN+ pin for C201 = Comparator inverting input is connected to the C1IN+ pin for C1 and C2IN+ pin for C200 = Comparator inverting input is connected to the C1IN- pin for C1 and C2IN- pin for C2
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: Setting this bit will invert the signal to the comparator interrupt generator as well. This will result in an interrupt being generated on the opposite edge from the one selected by EVPOL<1:0>.
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REGISTER 25-2: CMSTAT: COMPARATOR STATUS REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
— — SIDL — — — — —
7:0U-0 U-0 U-0 U-0 U-0 U-0 R-0 R-0
— — — — — — C2OUT C1OUT
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Control bit
1 = All Comparator modules are disabled while in Idle mode0 = All Comparator modules continue to operate while in Idle mode
bit 12-2 Unimplemented: Read as ‘0’
bit 1 C2OUT: Comparator Output bit
1 = Output of Comparator 2 is a ‘1’0 = Output of Comparator 2 is a ‘0’
bit 0 C1OUT: Comparator Output bit
1 = Output of Comparator 1 is a ‘1’0 = Output of Comparator 1 is a ‘0’
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NOTES:
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26.0 COMPARATOR VOLTAGE REFERENCE (CVREF)
The CVREF module is a 16-tap, resistor ladder networkthat provides a selectable reference voltage. Althoughits primary purpose is to provide a reference for theanalog comparators, it also may be used independentlyof them.
A block diagram of the module is illustrated inFigure 26-1. The resistor ladder is segmented toprovide two ranges of voltage reference values and hasa power-down function to conserve power when thereference is not being used. The module’s supply refer-ence can be provided from either device VDD/VSS or anexternal voltage reference. The CVREF output is avail-able for the comparators and typically available for pinoutput.
Key features of the CVREF module include:
• High and low range selection• Sixteen output levels available for each range• Internally connected to comparators to conserve
device pins• Output can be connected to a pin
FIGURE 26-1: COMPARATOR VOLTAGE REFERENCE MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 20. “ComparatorVoltage Reference (CVREF)”(DS60001109) in the “PIC32 FamilyReference Manual”, which is availablefrom the Microchip web site(www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
16-t
o-1
MU
X
CVR<3:0>8R
RCVREN
CVRSS = 0AVDD
VREF+CVRSS = 1
8R
CVRSS = 0
VREF-CVRSS = 1
R
R
R
R
R
R
16 Steps
CVRR
CVREFOUT
AVSS
CVROE (CVRCON<6>)
CVREF
VREFSEL(1)
IVREF
1.2V
0.6V
BGSEL<1:0>(1)
CVRSRC
Note 1: This bit is not available on PIC32MX575/675/695/775/795 devices. On these devices CVREF is generated by theRegister network and IVREF is connected to 0.6V.
2009-2013 Microchip Technology Inc. DS60001156H-page 335
bit 3-0 CVR<3:0>: CVREF Value Selection 0 CVR<3:0> 15 bits
When CVRR = 1:CVREF = (CVR<3:0>/24) (CVRSRC)
When CVRR = 0:CVREF = 1/4 (CVRSRC) + (CVR<3:0>/32) (CVRSRC)
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in theSYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: These bits are not available on PIC32MX575/675/775/795 devices. On these devices, the reset value forCVRON is ‘0000’.
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27.0 POWER-SAVING FEATURES
This section describes power-saving features for thePIC32MX5XX/6XX/7XX family of devices. Thesedevices offer a total of nine methods and modes,organized into two categories, that allow the user tobalance power consumption with device performance.In all of the methods and modes described in thissection, power-saving is controlled by software.
27.1 Power-Saving with CPU Running
When the CPU is running, power consumption can becontrolled by reducing the CPU clock frequency,lowering the Peripheral Bus Clock (PBCLK) and byindividually disabling modules. These methods aregrouped into the following categories:
• FRC Run mode: the CPU is clocked from the FRC clock source with or without postscalers.
• LPRC Run mode: the CPU is clocked from the LPRC clock source.
• SOSC Run mode: the CPU is clocked from the SOSC clock source.
In addition, the Peripheral Bus Scaling mode is availablewhere peripherals are clocked at the programmablefraction of the CPU clock (SYSCLK).
27.2 CPU Halted Methods
The device supports two power-saving modes, Sleepand Idle, both of which Halt the clock to the CPU. Thesemodes operate with all clock sources, as listed below:
• POSC Idle mode: the system clock is derived from the POSC. The system clock source continues to operate. Peripherals continue to operate, but can optionally be individually disabled.
• FRC Idle mode: the system clock is derived from the FRC with or without postscalers. Peripherals continue to operate, but can optionally be individually disabled.
• SOSC Idle mode: the system clock is derived from the SOSC. Peripherals continue to operate, but can optionally be individually disabled.
• LPRC Idle mode: the system clock is derived from the LPRC. Peripherals continue to operate, but can optionally be individually disabled. This is the lowest power mode for the device with a clock running.
• Sleep mode: the CPU, the system clock source and any peripherals that operate from the system clock source are Halted. Some peripherals can operate in Sleep using specific clock sources. This is the lowest power mode for the device.
27.3 Power-Saving Operation
Peripherals and the CPU can be halted or disabled tofurther reduce power consumption.
27.3.1 SLEEP MODE
Sleep mode has the lowest power consumption of thedevice power-saving operating modes. The CPU andmost peripherals are halted. Select peripherals cancontinue to operate in Sleep mode and can be used towake the device from Sleep. See the individualperipheral module sections for descriptions ofbehavior in Sleep.
Sleep mode includes the following characteristics:
• The CPU is halted
• The system clock source is typically shutdown. See Section 27.3.3 “Peripheral Bus Scaling Method” for specific information.
• There can be a wake-up delay based on the oscillator selection
• The Fail-Safe Clock Monitor (FSCM) does not operate during Sleep mode
• The BOR circuit, if enabled, remains operative during Sleep mode
• The WDT, if enabled, is not automatically cleared prior to entering Sleep mode
• Some peripherals can continue to operate at limited functionality in Sleep mode. These peripherals include I/O pins that detect a change in the input signal, WDT, ADC, UART and peripherals that use an external clock input or the internal LPRC oscillator (e.g., RTCC, Timer1 and Input Capture).
• I/O pins continue to sink or source current in the same manner as they do when the device is not in Sleep
• Modules can be individually disabled by software prior to entering Sleep in order to further reduce consumption
Note 1: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 10. “Power-Saving Features” (DS60001130) in the“PIC32 Family Reference Manual”, whichis available from the Microchip web site(www.microchip.com/PIC32).
2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 4.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.
2009-2013 Microchip Technology Inc. DS60001156H-page 337
The processor will exit, or ‘wake-up’, from Sleep on oneof the following events:
• On any interrupt from an enabled source that is operating in Sleep. The interrupt priority must be greater than the current CPU priority.
• On any form of device Reset
• On a WDT time-out
If the interrupt priority is lower than or equal to thecurrent priority, the CPU will remain Halted, but thePBCLK will start running and the device will enter intoIdle mode.
27.3.2 IDLE MODE
In Idle mode, the CPU is Halted but the System Clock(SYSCLK) source is still enabled. This allows peripher-als to continue operation when the CPU is Halted.Peripherals can be individually configured to Halt whenentering Idle by setting their respective SIDL bit.Latency, when exiting Idle mode, is very low due to theCPU oscillator source remaining active.
The device enters Idle mode when the SLPEN bit(OSCCON<4>) is clear and a WAIT instruction isexecuted.
The processor will wake or exit from Idle mode on thefollowing events:
• On any interrupt event for which the interrupt source is enabled. The priority of the interrupt event must be greater than the current priority of the CPU. If the priority of the interrupt event is lower than or equal to current priority of the CPU, the CPU will remain Halted and the device will remain in Idle mode.
• On any form of device Reset
• On a WDT time-out interrupt
27.3.3 PERIPHERAL BUS SCALING METHOD
Most of the peripherals on the device are clocked usingthe PBCLK. The Peripheral Bus (PB) can be scaled rel-ative to the SYSCLK to minimize the dynamic powerconsumed by the peripherals. The PBCLK divisor is con-trolled by PBDIV<1:0> (OSCCON<20:19>), allowingSYSCLK to PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. Allperipherals using PBCLK are affected when the divisoris changed. Peripherals such as USB, interrupt control-ler, DMA, bus matrix and prefetch cache are clockeddirectly from SYSCLK. As a result, they are not affectedby PBCLK divisor changes.
Changing the PBCLK divisor affects:
• The CPU to peripheral access latency. The CPU has to wait for next PBCLK edge for a read to complete. In 1:8 mode, this results in a latency of one to seven SYSCLKs.
• The power consumption of the peripherals. Power consumption is directly proportional to the fre-quency at which the peripherals are clocked. The greater the divisor, the lower the power consumed by the peripherals.
To minimize dynamic power, the PB divisor should bechosen to run the peripherals at the lowest frequencythat provides acceptable system performance. Whenselecting a PBCLK divider, peripheral clock require-ments, such as baud rate accuracy, should be takeninto account. For example, the UART peripheral maynot be able to achieve all baud rate values at somePBCLK divider depending on the SYSCLK value.
Note 1: Changing the PBCLK divider ratiorequires recalculation of peripheral tim-ing. For example, assume the UART isconfigured for 9600 baud with a PB clockratio of 1:1 and a POSC of 8 MHz. Whenthe PB clock divisor of 1:2 is used, theinput frequency to the baud clock is cut inhalf; therefore, the baud rate is reducedto 1/2 its former value. Due to numerictruncation in calculations (such as thebaud rate divisor), the actual baud ratemay be a tiny percentage different thanexpected. For this reason, any timing cal-culation required for a peripheral shouldbe performed with the new PB clock fre-quency instead of scaling the previousvalue based on a change in the PB divisorratio.
2: Oscillator start-up and PLL lock delaysare applied when switching to a clocksource that was disabled and that uses acrystal and/or the PLL. For example,assume the clock source is switched fromPOSC to LPRC just prior to entering Sleepin order to save power. No oscillator start-up delay would be applied when exitingIdle. However, when switching back toPOSC, the appropriate PLL and/oroscillator start-up/lock delays would beapplied.
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28.0 SPECIAL FEATURES
PIC32MX5XX/6XX/7XX devices include severalfeatures intended to maximize application flexibility andreliability and minimize cost through elimination ofexternal components. Key features include:
• Flexible device configuration
• Watchdog Timer (WDT)
• Joint Test Action Group (JTAG) interface
• In-Circuit Serial Programming™ (ICSP™)
28.1 Configuration Bits
The Configuration bits can be programmed using thefollowing registers to select various deviceconfigurations.
• DEVCFG0: Device Configuration Word 0
• DEVCFG1: Device Configuration Word 1
• DEVCFG2: Device Configuration Word 2
• DEVCFG3: Device Configuration Word 3
• DEVID: Device and Revision ID Register
Note: This data sheet summarizes the featuresof the PIC32MX5XX/6XX/7XX family ofdevices. However, it is not intended to bea comprehensive reference source. Tocomplement the information in this datasheet, refer to Section 8. “WatchdogTimer and Power-up Timer”(DS60001114), Section 24.“Configuration” (DS60001124) andSection 33. “Programming andDiagnostics” (DS60001129) in the“PIC32 Family Reference Manual”, whichare available from the Microchip web site(www.microchip.com/PIC32).
2009-2013 Microchip Technology Inc. DS60001156H-page 339
REGISTER 28-1: DEVCFG0: DEVICE CONFIGURATION WORD 0
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24r-0 r-1 r-1 R/P r-1 r-1 r-1 R/P
— — — CP — — — BWP
23:16r-1 r-1 r-1 r-1 R/P R/P R/P R/P
— — — — PWP<7:4>
15:8R/P R/P R/P R/P r-1 r-1 r-1 r-1
PWP<3:0> — — — —
7:0r-1 r-1 r-1 r-1 R/P r-1 R/P R/P
— — — — ICESEL — DEBUG<1:0>
Legend: r = Reserved bit P = Programmable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 Reserved: Write ‘0’
bit 30-29 Reserved: Write ‘1’
bit 28 CP: Code-Protect bit
Prevents boot and program Flash memory from being read or modified by an external programming device.1 = Protection is disabled0 = Protection is enabled
bit 27-25 Reserved: Write ‘1’
bit 24 BWP: Boot Flash Write-Protect bit
Prevents boot Flash memory from being modified during code execution.1 = Boot Flash is writable0 = Boot Flash is not writable
bit 23-20 Reserved: Write ‘1’
bit 19-12 PWP<7:0>: Program Flash Write-Protect bits
Prevents selected program Flash memory pages from being modified during code execution. The PWP bitsrepresent the 1’s complement of the number of write-protected program Flash memory pages. 11111111 = Disabled11111110 = 0xBD00_0FFF11111101 = 0xBD00_1FFF11111100 = 0xBD00_2FFF11111011 = 0xBD00_3FFF11111010 = 0xBD00_4FFF11111001 = 0xBD00_5FFF11111000 = 0xBD00_6FFF11110111 = 0xBD00_7FFF11110110 = 0xBD00_8FFF11110101 = 0xBD00_9FFF11110100 = 0xBD00_AFFF11110011 = 0xBD00_BFFF11110010 = 0xBD00_CFFF11110001 = 0xBD00_DFFF11110000 = 0xBD00_EFFF11101111 = 0xBD00_FFFF•••
01111111 = 0xBD07_FFFF
bit 11-4 Reserved: Write ‘1’
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PIC32MX5XX/6XX/7XX
bit 3 ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bit
1 = PGEC2/PGED2 pair is used0 = PGEC1/PGED1 pair is used
bit 2 Reserved: Write ‘1’
bit 1-0 DEBUG<1:0>: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled)
11 = Debugger is disabled10 = Debugger is enabled01 = Reserved (same as ‘11’ setting)00 = Reserved (same as ‘11’ setting)
REGISTER 28-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED)
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REGISTER 28-2: DEVCFG1: DEVICE CONFIGURATION WORD 1
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
23:16R/P r-1 r-1 R/P R/P R/P R/P R/P
FWDTEN — — WDTPS<4:0>
15:8R/P R/P R/P R/P r-1 R/P R/P R/P
FCKSM<1:0> FPBDIV<1:0> — OSCIOFNC POSCMOD<1:0>
7:0R/P r-1 R/P r-1 r-1 R/P R/P R/P
IESO — FSOSCEN — — FNOSC<2:0>
Legend: r = Reserved bit P = Programmable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-24 Reserved: Write ‘1’
bit 23 FWDTEN: Watchdog Timer Enable bit
1 = The WDT is enabled and cannot be disabled by software0 = The WDT is not enabled; it can be enabled in software
bit 22-21 Reserved: Write ‘1’
bit 20-16 WDTPS<4:0>: Watchdog Timer Postscale Select bits
bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
Note 1: Do not disable the POSC (POSCMOD = 11) when using this oscillator source.
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bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits11 = PBCLK is SYSCLK divided by 810 = PBCLK is SYSCLK divided by 401 = PBCLK is SYSCLK divided by 200 = PBCLK is SYSCLK divided by 1
bit 11 Reserved: Write ‘1’
bit 10 OSCIOFNC: CLKO Enable Configuration bit
1 = CLKO output is disabled0 = CLKO output signal is active on the OSCO pin; the Primary Oscillator must be disabled or configured
for External Clock mode (EC) for the CLKO to be active (POSCMOD<1:0> = 11 or 00)
bit 9-8 POSCMOD<1:0>: Primary Oscillator Configuration bits
111 = Assign Interrupt Priority 7 to a shadow register set110 = Assign Interrupt Priority 6 to a shadow register set•••
001 = Assign Interrupt Priority 1 to a shadow register set000 = All interrupt priorities are assigned to a shadow register set
bit 15-0 USERID<15:0>: User ID bitsThis is a 16-bit value that is user-defined and is readable via ICSP™ and JTAG.
Note 1: This bit is Reserved and reads ‘1’ on PIC32MX664/675/695 devices.
2: This bit is Reserved and reads ‘1’ on PIC32MX534/564/575 devices.
DS60001156H-page 346 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 28-5: DEVID: DEVICE AND REVISION ID REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24R R R R R R R R
VER<3:0>(1) DEVID<27:24>(1)
23:16R R R R R R R R
DEVID<23:16>(1)
15:8R R R R R R R R
DEVID<15:8>(1)
7:0R R R R R R R R
DEVID<7:0>(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-28 VER<3:0>: Revision Identifier bits(1)
bit 27-0 DEVID<27:0>: Device ID bits(1)
Note 1: See the “PIC32 Flash Programming Specification” (DS60001145) for a list of Revision and Device ID values.
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PIC32MX5XX/6XX/7XX
28.2 Watchdog Timer (WDT)
This section describes the operation of the WDT andPower-up Timer of the PIC32MX5XX/6XX/7XX.
The WDT, when enabled, operates from the internalLow-Power Oscillator (LPRC) clock source and can beused to detect system software malfunctions by reset-ting the device if the WDT is not cleared periodically insoftware. Various WDT time-out periods can beselected using the WDT postscaler. The WDT can alsobe used to wake the device from Sleep or Idle mode.
Key features of the WDT module include:
• Configuration or software controlled
• User-configurable time-out period
• Can wake the device from Sleep or Idle
FIGURE 28-1: WATCHDOG TIMER AND POWER-UP TIMER BLOCK DIAGRAM
Wake
WDTCLR = 1
WDT Enable
LPRC
Power Save
25-bit Counter
PWRT EnableWDT Enable
LPRC
WDT Counter Reset
Control
Oscillator
25Device Reset
NMI (Wake-up)
PWRT
PWRT Enable
FWDTPS<4:0> (DEVCFG1<20:16>)
Clock
Decoder
1
1:64 Output
0
1WDT EnableReset Event
DS60001156H-page 348 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 28-6: WDTCON: WATCHDOG TIMER CONTROL REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
ON(1,2) — — — — — — —
7:0U-0 R-y R-y R-y R-y R-y R/W-0 R/W-0
— SWDTPS<4:0> WDTWINEN WDTCLR
Legend: y = Values set from Configuration bits on POR
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: Watchdog Timer Enable bit(1,2)
1 = Enables the WDT if it is not enabled by the device configuration0 = Disable the WDT if it was enabled in software
bit 14-7 Unimplemented: Read as ‘0’
bit 6-2 SWDTPS<4:0>: Shadow Copy of Watchdog Timer Postscaler Value from Device Configuration bits
On reset, these bits are set to the values of the WDTPS <4:0> Configuration bits.
bit 0 WDTCLR: Watchdog Timer Reset bit1 = Writing a ‘1’ will clear the WDT0 = Software cannot force this bit to a ‘0’
Note 1: A read of this bit results in a ‘1’ if the Watchdog Timer is enabled by the device configuration or software.
2: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2009-2013 Microchip Technology Inc. DS60001156H-page 349
PIC32MX5XX/6XX/7XX
28.3 On-Chip Voltage Regulator
All PIC32MX5XX/6XX/7XX devices’ core and digitallogic are designed to operate at a nominal 1.8V. Tosimplify system designs, most devices in the PIC32MX-5XX/6XX/7XX family incorporate an on-chip regulatorproviding the required core logic voltage from VDD.
A low-ESR capacitor (such as tantalum) must beconnected to the VCAP pin (see Figure 28-2). Thishelps to maintain the stability of the regulator. Therecommended value for the filter capacitor is providedin Section 31.1 “DC Characteristics”.
28.3.1 ON-CHIP REGULATOR AND POR
It takes a fixed delay for the on-chip regulator to generatean output. During this time, designated as TPU, codeexecution is disabled. TPU is applied every time thedevice resumes operation after any power-down,including Sleep mode.
28.3.2 ON-CHIP REGULATOR AND BOR
PIC32MX5XX/6XX/7XX devices also have a simplebrown-out capability. If the voltage supplied to theregulator is inadequate to maintain a regulated level,the regulator Reset circuitry will generate a Brown-outReset (BOR). This event is captured by the BOR flagbit (RCON<1>). The brown-out voltage levels arespecified in Section 31.1 “DC Characteristics”.
FIGURE 28-2: CONNECTIONS FOR THE ON-CHIP REGULATOR
28.4 Programming and Diagnostics
PIC32MX5XX/6XX/7XX devices provide a completerange of programming and diagnostic features that canincrease the flexibility of any application using them.These features allow system designers to include:
• Simplified field programmability using two-wire In-Circuit Serial Programming™ (ICSP™) interfaces
• Debugging using ICSP
• Programming and debugging capabilities using the EJTAG extension of JTAG
• JTAG boundary scan testing for device and board diagnostics
PIC32 devices incorporate two programming and diag-nostic modules, and a trace controller, that provide arange of functions to the application developer.
FIGURE 28-3: BLOCK DIAGRAM OF PROGRAMMING, DEBUGGING AND TRACE PORTS
Note: It is important that the low-ESR capacitoris placed as close as possible to the VCAP
pin.
VDD
VCAP
VSS
PIC32
CEFC(2)
3.3V(1)
Note 1: These are typical operating voltages. Refer to Section 31.1 “DC Characteristics” for the full operating ranges of VDD.
2: It is important that the low-ESR capacitor is placed as close as possible to the VCAP pin.
(10 F typical)
TDI
TDO
TCK
TMS
JTAGController
ICSP™Controller
Core
JTAGEN DEBUG<1:0>
Instruction TraceController
DEBUG<1:0>
ICESEL
PGEC1
PGED1
PGEC2
PGED2
TRCLK
TRD0
TRD1
TRD2
TRD3
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REGISTER 28-7: DDPCON: DEBUG DATA PORT CONTROL REGISTER
Bit Range
Bit31/23/15/7
Bit30/22/14/6
Bit29/21/13/5
Bit28/20/12/4
Bit27/19/11/3
Bit26/18/10/2
Bit25/17/9/1
Bit24/16/8/0
31:24U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0U-0 U-0 U-0 U-0 R/W-1 R/W-0 U-0 R/W-0
— — — — JTAGEN TROEN — TDOEN
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-4 Unimplemented: Read as ‘0’
bit 3 JTAGEN: JTAG Port Enable bit
1 = Enable the JTAG port0 = Disable the JTAG port
bit 2 TROEN: Trace Output Enable bit
1 = Enable the trace port0 = Disable the trace port
bit 1 Unimplemented: Read as ‘0’
bit 0 TDOEN: TDO Enable for 2-Wire JTAG
1 = 2-wire JTAG protocol uses TDO0 = 2-wire JTAG protocol does not use TDO
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NOTES:
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29.0 INSTRUCTION SET
The PIC32MX5XX/6XX/7XX family instruction setcomplies with the MIPS32 Release 2 instruction setarchitecture. The PIC32 device family does not supportthe following features:
• Core Extend instructions
• Coprocessor 1 instructions
• Coprocessor 2 instructions
Note: Refer to “MIPS32® Architecture forProgrammers Volume II: The MIPS32®
Instruction Set” at www.mips.com formore information.
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• Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits
30.1 MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of softwaredevelopment previously unseen in the 8/16/32-bitmicrocontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of contents
• High-level source code debugging
• Mouse over variable inspection
• Drag and drop variables from source to watch windows
• Extensive on-line help
• Integration of select third party tools, such as IAR C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information)
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in asingle development paradigm, from the cost-effectivesimulators, through low-cost in-circuit debuggers, tofull-featured emulators. This eliminates the learningcurve when upgrading to tools with increased flexibilityand power.
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30.2 MPLAB C Compilers for Various Device Families
The MPLAB C Compiler code development systemsare complete ANSI C compilers for Microchip’s PIC18,PIC24 and PIC32 families of microcontrollers and thedsPIC30 and dsPIC33 families of digital signal control-lers. These compilers provide powerful integrationcapabilities, superior code optimization and ease ofuse.
For easy source level debugging, the compilers providesymbol information that is optimized to the MPLAB IDEdebugger.
30.3 HI-TECH C for Various Device Families
The HI-TECH C Compiler code development systemsare complete ANSI C compilers for Microchip’s PICfamily of microcontrollers and the dsPIC family of digitalsignal controllers. These compilers provide powerfulintegration capabilities, omniscient code generationand ease of use.
For easy source level debugging, the compilers providesymbol information that is optimized to the MPLAB IDEdebugger.
The compilers include a macro assembler, linker, pre-processor, and one-step driver, and can run on multipleplatforms.
30.4 MPASM Assembler
The MPASM Assembler is a full-featured, universalmacro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable objectfiles for the MPLINK Object Linker, Intel® standard HEXfiles, MAP files to detail memory usage and symbolreference, absolute LST files that contain source linesand generated machine code and COFF files fordebugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• User-defined macros to streamline assembly code
• Conditional assembly for multi-purpose source files
• Directives that allow complete control over the assembly process
30.5 MPLINK Object Linker/MPLIB Object Librarian
The MPLINK Object Linker combines relocatableobjects created by the MPASM Assembler and theMPLAB C18 C Compiler. It can link relocatable objectsfrom precompiled libraries, using directives from alinker script.
The MPLIB Object Librarian manages the creation andmodification of library files of precompiled code. Whena routine from a library is called from a source file, onlythe modules that contain that routine will be linked inwith the application. This allows large libraries to beused efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many smaller files
• Enhanced code maintainability by grouping related modules together
• Flexible creation of libraries with easy module listing, replacement, deletion and extraction
30.6 MPLAB Assembler, Linker and Librarian for Various Device Families
MPLAB Assembler produces relocatable machinecode from symbolic assembly language for PIC24,PIC32 and dsPIC devices. MPLAB C Compiler usesthe assembler to produce its object file. The assemblergenerates relocatable object files that can then bearchived or linked with other relocatable object files andarchives to create an executable file. Notable featuresof the assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich directive set
• Flexible macro language
• MPLAB IDE compatibility
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30.7 MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows codedevelopment in a PC-hosted environment by simulat-ing the PIC MCUs and dsPIC® DSCs on an instructionlevel. On any given instruction, the data areas can beexamined or modified and stimuli can be applied froma comprehensive stimulus controller. Registers can belogged to files for further run-time analysis. The tracebuffer and logic analyzer display extend the power ofthe simulator to record and track program execution,actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supportssymbolic debugging using the MPLAB C Compilers,and the MPASM and MPLAB Assemblers. The soft-ware simulator offers the flexibility to develop anddebug code outside of the hardware laboratory envi-ronment, making it an excellent, economical softwaredevelopment tool.
30.8 MPLAB REAL ICE In-Circuit Emulator System
MPLAB REAL ICE In-Circuit Emulator System isMicrochip’s next generation high-speed emulator forMicrochip Flash DSC and MCU devices. It debugs andprograms PIC® Flash MCUs and dsPIC® Flash DSCswith the easy-to-use, powerful graphical user interface ofthe MPLAB Integrated Development Environment (IDE),included with each kit.
The emulator is connected to the design engineer’s PCusing a high-speed USB 2.0 interface and is connectedto the target with either a connector compatible with in-circuit debugger systems (RJ11) or with the new high-speed, noise tolerant, Low-Voltage Differential Signal(LVDS) interconnection (CAT5).
The emulator is field upgradable through future firmwaredownloads in MPLAB IDE. In upcoming releases ofMPLAB IDE, new devices will be supported, and newfeatures will be added. MPLAB REAL ICE offerssignificant advantages over competitive emulatorsincluding low-cost, full-speed emulation, run-timevariable watches, trace analysis, complex breakpoints, aruggedized probe interface and long (up to three meters)interconnection cables.
30.9 MPLAB ICD 3 In-Circuit Debugger System
MPLAB ICD 3 In-Circuit Debugger System is Micro-chip's most cost effective high-speed hardwaredebugger/programmer for Microchip Flash Digital Sig-nal Controller (DSC) and microcontroller (MCU)devices. It debugs and programs PIC® Flash microcon-trollers and dsPIC® DSCs with the powerful, yet easy-to-use graphical user interface of MPLAB IntegratedDevelopment Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is con-nected to the design engineer's PC using a high-speedUSB 2.0 interface and is connected to the target with aconnector compatible with the MPLAB ICD 2 or MPLABREAL ICE systems (RJ-11). MPLAB ICD 3 supports allMPLAB ICD 2 headers.
30.10 PICkit 3 In-Circuit Debugger/Programmer and PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and program-ming of PIC® and dsPIC® Flash microcontrollers at amost affordable price point using the powerful graphicaluser interface of the MPLAB Integrated DevelopmentEnvironment (IDE). The MPLAB PICkit 3 is connectedto the design engineer's PC using a full-speed USBinterface and can be connected to the target via anMicrochip debug (RJ-11) connector (compatible withMPLAB ICD 3 and MPLAB REAL ICE). The connectoruses two device I/O pins and the reset line to imple-ment in-circuit debugging and In-Circuit Serial Pro-gramming™.
The PICkit 3 Debug Express include the PICkit 3, demoboard and microcontroller, hookup cables and CDROMwith user’s guide, lessons, tutorial, compiler andMPLAB IDE software.
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30.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express
The PICkit™ 2 Development Programmer/Debugger isa low-cost development tool with an easy to use inter-face for programming and debugging Microchip’s Flashfamilies of microcontrollers. The full featuredWindows® programming interface supports baseline(PIC10F, PIC12F5xx, PIC16F5xx), midrange(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bitmicrocontrollers, and many Microchip Serial EEPROMproducts. With Microchip’s powerful MPLAB IntegratedDevelopment Environment (IDE) the PICkit™ 2enables in-circuit debugging on most PIC® microcon-trollers. In-Circuit-Debugging runs, halts and singlesteps the program while the PIC microcontroller isembedded in the application. When halted at a break-point, the file registers can be examined and modified.
The PICkit 2 Debug Express include the PICkit 2, demoboard and microcontroller, hookup cables and CDROMwith user’s guide, lessons, tutorial, compiler andMPLAB IDE software.
30.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,CE compliant device programmer with programmablevoltage verification at VDDMIN and VDDMAX formaximum reliability. It features a large LCD display(128 x 64) for menus and error messages and a modu-lar, detachable socket assembly to support variouspackage types. The ICSP™ cable assembly is includedas a standard item. In Stand-Alone mode, the MPLABPM3 Device Programmer can read, verify and programPIC devices without a PC connection. It can also setcode protection in this mode. The MPLAB PM3connects to the host PC via an RS-232 or USB cable.The MPLAB PM3 has high-speed communications andoptimized algorithms for quick programming of largememory devices and incorporates an MMC card for filestorage and data applications.
30.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
A wide variety of demonstration, development andevaluation boards for various PIC MCUs and dsPICDSCs allows quick application development on fully func-tional systems. Most boards include prototyping areas foradding custom circuitry and provide application firmwareand source code for examination and modification.
The boards support a variety of features, including LEDs,temperature sensors, switches, speakers, RS-232interfaces, LCD displays, potentiometers and additionalEEPROM memory.
The demonstration and development boards can beused in teaching environments, for prototyping customcircuits and for learning about various microcontrollerapplications.
In addition to the PICDEM™ and dsPICDEM™ demon-stration/development board series of circuits, Microchiphas a line of evaluation kits and demonstration softwarefor analog filter design, KEELOQ® security ICs, CAN,IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow ratesensing, plus many more.
Also available are starter kits that contain everythingneeded to experience the specified device. This usuallyincludes a single application and debug capability, allon one board.
Check the Microchip web page (www.microchip.com)for the complete list of demonstration, developmentand evaluation kits.
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This section provides an overview of the PIC32MX5XX/6XX/7XX electrical characteristics. Additional information will beprovided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC32MX5XX/6XX/7XX devices are listed below. Exposure to these maximum ratingconditions for extended periods may affect device reliability. Functional operation of the device at these or any otherconditions, above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings(See Note 1)
Ambient temperature under bias............................................................................................................ .-40°C to +105°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3)......................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD 2.3V (Note 3) ........................................ -0.3V to +5.5V
Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3)........................................ -0.3V to +3.6V
Voltage on VBUS with respect to VSS ....................................................................................................... -0.3V to +5.5V
Maximum current out of VSS pin(s) .......................................................................................................................300 mA
Maximum current into VDD pin(s) (Note 2)............................................................................................................300 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (Note 2)....................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to thedevice. This is a stress rating only and functional operation of the device at those or any other conditions,above those indicated in the operation listings of this specification, is not implied. Exposure to maximumrating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 31-2).
3: See the “Pin Diagrams” section for the 5V tolerant pins.
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31.1 DC Characteristics
TABLE 31-1: OPERATING MIPS VS. VOLTAGE
CharacteristicVDD Range(in Volts)(1)
Temp. Range(in °C)
Max. Frequency
PIC32MX5XX/6XX/7XX
DC5 2.3-3.6V -40°C to +85°C 80 MHz
DC5b 2.3-3.6V -40°C to +105°C 80 MHz
Note 1: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to parameter BO10 in Table 31-10 for BOR values.
TABLE 31-2: THERMAL OPERATING CONDITIONS
Rating Symbol Min. Typical Max. Unit
Industrial Temperature Devices
Operating Junction Temperature Range TJ -40 — +125 °C
Operating Ambient Temperature Range TA -40 — +85 °C
V-Temp Temperature Devices
Operating Junction Temperature Range TJ -40 — +140 °C
Operating Ambient Temperature Range TA -40 — +105 °C
Power Dissipation:Internal Chip Power Dissipation:
PINT = VDD x (IDD – S IOH) PD PINT + PI/O WI/O Pin Power Dissipation:
I/O = S (({VDD – VOH} x IOH) + S (VOL x IOL))
Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W
Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
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TABLE 31-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Param. No.
Symbol Characteristics Min. Typical Max. Units Conditions
Operating Voltage
DC10 VDD Supply Voltage 2.3 — 3.6 V —
DC12 VDR RAM Data Retention Voltage(1) 1.75 — — V —
DC16 VPOR VDD Start Voltage to Ensure Internal Power-on Reset Signal
1.75 — 2.1 V —
DC17 SVDD VDD Rise Rate to Ensure Internal Power-on Reset Signal
0.00005 — 0.115 V/s —
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to parameter BO10 in Table 31-10 for BOR values.
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TABLE 31-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Param. No.
Typical(3) Max. Units Conditions
Operating Current (IDD)(1,2) for PIC32MX575/675/695/775/795 Family Devices
DC20 6 9
mACode executing from Flash
-40ºC, +25ºC, +85ºC — 4 MHz
DC20b 7 10 +105ºC
DC20a 4 — Code executing from SRAM —
DC21 37 40mA
Code executing from Flash— —
25 MHz (Note 4)DC21a 25 — Code executing from SRAM
DC22 64 70mA
Code executing from Flash— —
60 MHz (Note 4)DC22a 61 — Code executing from SRAM
DC23 85 98
mACode executing from Flash
-40ºC, +25ºC, +85ºC — 80 MHz
DC23b 90 120 +105ºC
DC23a 85 — Code executing from SRAM —
DC25a 125 150 µA — +25°C 3.3VLPRC (31 kHz)
(Note 4)
Note 1: A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors, such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate, oscillator type, as well as temperature, can have an impact on the current consumption.
2: The test conditions for IDD measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU, program Flash, and SRAM data memory are operational, program Flash memory Wait states = 111, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• CPU executing while(1) statement from Flash
• RTCC and JTAG are disabled
3: Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated. Parameters are for design guidance only and are not tested.
4: This parameter is characterized, but not tested in manufacturing.
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Operating Current (IDD)(1,2) for PIC32MX534/564/664/764 Family Devices
DC20c 6 9
mACode executing from Flash
-40ºC, +25ºC, +85ºC — 4 MHz
DC20d 7 10 +105ºC
DC20e 2 — Code executing from SRAM —
DC21b 19 32mA
Code executing from Flash— —
25 MHz (Note 4)DC21c 14 — Code executing from SRAM
DC22b 31 50mA
Code executing from Flash— —
60 MHz (Note 4)DC22c 29 — Code executing from SRAM
DC23c 39 65
mACode executing from Flash
-40ºC, +25ºC, +85ºC — 80 MHz
DC23d 49 70 +105ºC
DC23e 39 — Code executing from SRAM —
DC25b 100 150 µA — +25°C 3.3VLPRC (31 kHz)
(Note 4)
TABLE 31-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED)
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Param. No.
Typical(3) Max. Units Conditions
Note 1: A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors, such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate, oscillator type, as well as temperature, can have an impact on the current consumption.
2: The test conditions for IDD measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU, program Flash, and SRAM data memory are operational, program Flash memory Wait states = 111, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• CPU executing while(1) statement from Flash
• RTCC and JTAG are disabled
3: Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated. Parameters are for design guidance only and are not tested.
4: This parameter is characterized, but not tested in manufacturing.
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TABLE 31-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Parameter No.
Typical(2) Max. Units Conditions
Idle Current (IIDLE)(1) for PIC32MX575/675/695/775/795 Family Devices
Note 1: The test conditions for IPD current measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Sleep mode, program Flash memory Wait states = 111, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• RTCC and JTAG are disabled
2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
3: The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current.
4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.5: Data is characterized at +70°C and not tested. Parameter is for design guidance only.6: This parameter is characterized, but not tested in manufacturing.
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Power-Down Current (IPD)(1) for PIC32MX534/564/664/764 Family Devices
DC40g 12 40
A
-40°C
2.3V Base Power-Down Current (Note 6)DC40h 20 120 +25°C
DC40i 210 600 +85°C
DC40o 400 1000 +105°C
DC40j 20 120 +25°C 3.3V Base Power-Down Current
DC40k 15 80 -40°C
3.6V Base Power-Down Current
DC40l 20 120 +25°C
DC40m 113 350(5) +70°C
DC40n 220 650 +85°C
DC40p 500 1000 +105°C
Module Differential Current for PIC32MX534/564/664/764 Family Devices
TABLE 31-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED)
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Param. No.
Typical(2) Max. Units Conditions
Note 1: The test conditions for IPD current measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Sleep mode, program Flash memory Wait states = 111, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• RTCC and JTAG are disabled
2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
3: The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current.
4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.5: Data is characterized at +70°C and not tested. Parameter is for design guidance only.6: This parameter is characterized, but not tested in manufacturing.
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TABLE 31-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial-40°C TA +105°C for V-Temp
Param. No.
Symbol Characteristics Min. Typical(1) Max. Units Conditions
VIL Input Low VoltageDI10 I/O Pins:
with TTL Buffer VSS — 0.15 VDD Vwith Schmitt Trigger Buffer VSS — 0.2 VDD V
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
4: This parameter is characterized, but not tested in manufacturing.
5: See the “Pin Diagrams” section for the 5V-tolerant pins.
6: The VIH specification is only in relation to externally applied inputs and not with respect to the user-select-able pull-ups. Externally applied high impedance or open drain input signals utilizing the PIC32 internal pull-ups are guaranteed to be recognized as a logic “high” internally to the PIC32 device, provided that the external load does not exceed the maximum value of ICNPU.
7: VIL source < (VSS - 0.3). Characterized but not tested.
9: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any “positive” input injection current.
10: Injection currents > | 0 | can affect the ADC results by approximately 4 to 6 counts (i.e., VIH Source > (VDD + 0.3) or VIL source < (VSS - 0.3)).
11: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro-vided the “absolute instantaneous” sum of the input injection currents from all pins do not exceed the speci-fied limit. If Note 7, IICL = (((Vss - 0.3) - VIL source) / Rs). If Note 8, IICH = ((IICH source - (VDD + 0.3)) / RS). RS = Resistance between input source voltage and device pin. If (VSS - 0.3) VSOURCE (VDD + 0.3), injec-tion current = 0.
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IIL Input Leakage Current(3)
DI50 I/O Ports — — +1 A VSS VPIN VDD,Pin at high-impedance
DI51 Analog Input Pins — — +1 A VSS VPIN VDD,Pin at high-impedance
DI55 MCLR(2) — — +1 A VSS VPIN VDD
DI56 OSC1 — — +1 A VSS VPIN VDD, XT and HS modes
DI60a IICLInput Low Injection Current
0 — -5(7,10) mA
This parameter applies to all pins, with the exception of RB10. Maximum IICH current for this exception is 0 mA.
DI60b IICHInput High Injection Current
0 — +5(8,9,10) mA
This parameter applies to all pins, with the exception of all 5V toler-ant pins, SOSCI, and RB10. Maximum IICH current for these exceptions is 0 mA.
DI60c IICT Total Input Injection Current (sum of all I/O and control pins)
-20(11) — +20(11) mA Absolute instantaneous sum of all ± input injection currents from all I/O pins( | IICL + | IICH | ) IICT
TABLE 31-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial-40°C TA +105°C for V-Temp
Param. No.
Symbol Characteristics Min. Typical(1) Max. Units Conditions
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
4: This parameter is characterized, but not tested in manufacturing.
5: See the “Pin Diagrams” section for the 5V-tolerant pins.
6: The VIH specification is only in relation to externally applied inputs and not with respect to the user-select-able pull-ups. Externally applied high impedance or open drain input signals utilizing the PIC32 internal pull-ups are guaranteed to be recognized as a logic “high” internally to the PIC32 device, provided that the external load does not exceed the maximum value of ICNPU.
7: VIL source < (VSS - 0.3). Characterized but not tested.
9: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any “positive” input injection current.
10: Injection currents > | 0 | can affect the ADC results by approximately 4 to 6 counts (i.e., VIH Source > (VDD + 0.3) or VIL source < (VSS - 0.3)).
11: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro-vided the “absolute instantaneous” sum of the input injection currents from all pins do not exceed the speci-fied limit. If Note 7, IICL = (((Vss - 0.3) - VIL source) / Rs). If Note 8, IICH = ((IICH source - (VDD + 0.3)) / RS). RS = Resistance between input source voltage and device pin. If (VSS - 0.3) VSOURCE (VDD + 0.3), injec-tion current = 0.
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TABLE 31-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
Param. Symbol Characteristic Min. Typ. Max. Units Conditions
DO10 VOL
Output Low VoltageI/O Pins:4x Sink Driver Pins - All I/O output pins not defined as 8x Sink Driver pins
Output High VoltageI/O Pins:4x Source Driver Pins - All I/O output pins not defined as 8x Source Driver pins
2.4 — — V IOH -10 mA, VDD = 3.3V
Output High VoltageI/O Pins:8x Source Driver Pins - RC15
2.4 — — V IOH -15 mA, VDD = 3.3V
DO20A VOH1
Output High VoltageI/O Pins:4x Source Driver Pins - All I/O output pins not defined as 8x Sink Driver pins
1.5(1) — —
V
IOH -14 mA, VDD = 3.3V
2.0(1) — — IOH -12 mA, VDD = 3.3V
3.0(1) — — IOH -7 mA, VDD = 3.3V
Output High VoltageI/O Pins:8x Source Driver Pins - RC15
1.5(1) — —
V
IOH -22 mA, VDD = 3.3V
2.0(1) — — IOH -18 mA, VDD = 3.3V
3.0(1) — — IOH -10 mA, VDD = 3.3V
Note 1: Parameters are characterized, but not tested.2: This driver pin only applies to devices with less than 64 pins.3: This driver pin only applies to devices with 64 pins.
TABLE 31-10: ELECTRICAL CHARACTERISTICS: BOR
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Param.No.
Symbol Characteristics Min.(1) Typical Max. Units Conditions
BO10 VBOR BOR Event on VDD transition high-to-low (Note 2)
2.0 — 2.3 V —
Note 1: Parameters are for design guidance only and are not tested in manufacturing.
2: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN.
DS60001156H-page 370 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-12: PROGRAM FLASH MEMORY WAIT STATE CHARACTERISTICS
TABLE 31-11: DC CHARACTERISTICS: PROGRAM MEMORY
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Param.No.
Symbol Characteristics Min. Typical(1) Max. Units Conditions
Program Flash Memory(3)
D130 EP Cell Endurance 1000 — — E/W —
D130a EP Cell Endurance 20,000 — — E/W See Note 4
D131 VPR VDD for Read 2.3 — 3.6 V —
D132 VPEW VDD for Erase or Write 3.0 — 3.6 V —
D132a VPEW VDD for Erase or Write 2.3 — 3.6 V See Note 4
D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications are violated
D135 IDDP Supply Current during Programming
— 10 — mA —
TWW Word Write Cycle Time 20 — 40 s —
D136 TRW Row Write Cycle Time(2) 3 4.5 — ms —
D137 TPE Page Erase Cycle Time 20 — — ms —
TCE Chip Erase Cycle Time 80 — — ms —
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
2: The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus loads are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default Arbitration mode is mode 1 (CPU has lowest priority).
3: Refer to “PIC32 Flash Programming Specification” (DS60001145) for operating conditions during programming and erase cycles.
4: This parameter only applies to PIC32MX534/564/664/764 devices.
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Required Flash Wait States SYSCLK Units Comments
0 Wait State 0 to 30 MHz —
1 Wait State 31 to 60
2 Wait States 61 to 80
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TABLE 31-13: COMPARATOR SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions (see Note 3): 2.3V to 3.6V(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Param.No.
Symbol Characteristics Min. Typical Max. Units Comments
— — 10 s Comparator module is configured before setting the comparator ON bit (Note 2)
D305 IVREF Internal Voltage Reference 0.57 0.6 0.63 V For devices without BGSEL<1:0>
1.14 1.2 1.26 V BGSEL<1:0> = 00
0.57 0.6 0.63 V BGSEL<1:0> = 01
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD.
2: These parameters are characterized but not tested.
3: The Comparator module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized.
DS60001156H-page 372 2009-2013 Microchip Technology Inc.
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TABLE 31-14: VOLTAGE REFERENCE SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Param.No.
Symbol Characteristics Min. Typical Max. Units Comments
D310 VRES Resolution VDD/24 — VDD/32 LSb —
D311 VRAA Absolute Accuracy — — 1/2 LSb —
D312 TSET Settling Time(1) — — 10 s —
D313 VIREF Internal Voltage Reference — 0.6 — V —
Note 1: Settling time measured while CVRR = 1 and CVR<3:0> transitions from ‘0000’ to ‘1111’. This parameter is characterized, but not tested in manufacturing.
TABLE 31-15: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Param.No.
Symbol Characteristics Min. Typical Max. Units Comments
D321 CEFC External Filter Capacitor Value 8 10 — F Capacitor must be low series resistance (1 ohm)
D322 TPWRT Power-up Timer Period — 64 — ms —
2009-2013 Microchip Technology Inc. DS60001156H-page 373
PIC32MX5XX/6XX/7XX
31.2 AC Characteristics and Timing Parameters
The information contained in this section definesPIC32MX5XX/6XX/7XX AC characteristics and timingparameters.
FIGURE 31-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
FIGURE 31-2: EXTERNAL CLOCK TIMING
VDD/2
CL
RL
Pin
Pin
VSS
VSS
CL
RL = 464CL = 50 pF for all pins
50 pF for OSC2 pin (EC mode)
Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2
TABLE 31-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Param. No.
Symbol Characteristics Min. Typical(1) Max. Units Conditions
DO56 CIO All I/O pins and OSC2 — — 50 pF EC mode
DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
OSC1
OS20 OS30
OS30
OS31
OS31
DS60001156H-page 374 2009-2013 Microchip Technology Inc.
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TABLE 31-17: EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Param.No.
Symbol Characteristics Min. Typical(1) Max. Units Conditions
OS10 FOSC External CLKI Frequency(External clocks only allowed in EC and ECPLL modes)
OS20 TOSC TOSC = 1/FOSC = TCY(2) — — — — See parameter OS10 for FOSC value
OS30 TOSL,TOSH
External Clock In (OSC1)High or Low Time
0.45 x TOSC — — ns EC (Note 4)
OS31 TOSR,TOSF
External Clock In (OSC1)Rise or Fall Time
— — 0.05 x TOSC ns EC (Note 4)
OS40 TOST Oscillator Start-up Timer Period(Only applies to HS, HSPLL, XT, XTPLL and SOSC Clock Oscillator modes)
— 1024 — TOSC (Note 4)
OS41 TFSCM Primary Clock Fail Safe Time-out Period
— 2 — ms (Note 4)
OS42 GM External Oscillator Transconductance
— 12 — mA/V VDD = 3.3V,TA = +25°C(Note 4)
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are characterized but are not tested.
2: Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin.
3: PLL input requirements: 4 MHZ FPLLIN 5 MHZ (use PLL prescaler to reduce FOSC). This parameter is characterized, but is only tested at 10 MHz at manufacturing.
4: This parameter is characterized, but not tested in manufacturing.
2009-2013 Microchip Technology Inc. DS60001156H-page 375
Standard Operating Conditions: 2.3V to 3.6V(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Param.No.
Symbol Characteristics(1) Min. Typical Max. Units Conditions
OS50 FPLLI PLL Voltage Controlled Oscillator (VCO) Input Frequency Range
3.92 — 5 MHz ECPLL, HSPLL, XTPLL, FRCPLL modes
OS51 FSYS On-Chip VCO System Frequency
60 — 120 MHz —
OS52 TLOCK PLL Start-up Time (Lock Time) — — 2 ms —
OS53 DCLK CLKO Stability(2)
(Period Jitter or Cumulative)-0.25 — +0.25 % Measured over 100 ms
period
Note 1: These parameters are characterized, but not tested in manufacturing.
2: This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective jitter for individual time-bases on communication clocks, use the following formula:
For example, if SYSCLK = 80 MHz and SPI bit rate = 20 MHz, the effective jitter is as follows:
Standard Operating Conditions: 2.3V to 3.6V(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Param.No.
Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions
SY00 TPU Power-up PeriodInternal Voltage Regulator Enabled
— 400 600 s -40°C to +85°C
SY02 TSYSDLY System Delay Period:Time Required to Reload Device Configuration Fuses plus SYSCLK Delay before First instruction is Fetched.
— 1 µs + 8 SYSCLK
cycles
— — -40°C to +85°C
SY20 TMCLR MCLR Pulse Width (low) — 2 — s -40°C to +85°C
SY30 TBOR BOR Pulse Width (low) — 1 — s -40°C to +85°C
Note 1: These parameters are characterized, but not tested in manufacturing.2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested.
Standard Operating Conditions: 2.3V to 3.6V(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Param.No.
Symbol Characteristics(1) Min. Typ.(2) Max. Units Conditions
SP70 TSCL SCKx Input Low Time(3) TSCK/2 — — ns —SP71 TSCH SCKx Input High Time(3) TSCK/2 — — ns —SP72 TSCF SCKx Input Fall Time — — — ns See parameter DO32SP73 TSCR SCKx Input Rise Time — — — ns See parameter DO31SP30 TDOF SDOx Data Output Fall Time(4) — — — ns See parameter DO32SP31 TDOR SDOx Data Output Rise Time(4) — — — ns See parameter DO31SP35 TSCH2DOV,
TSCL2DOVSDOx Data Output Valid afterSCKx Edge
— — 15 ns VDD > 2.7V— — 20 ns VDD < 2.7V
SP40 TDIV2SCH, TDIV2SCL
Setup Time of SDIx Data Inputto SCKx Edge
10 — — ns —
SP41 TSCH2DIL, TSCL2DIL
Hold Time of SDIx Data Inputto SCKx Edge
10 — — ns —
SP50 TSSL2SCH, TSSL2SCL
SSx to SCKx or SCKx Input 175 — — ns —
SP51 TSSH2DOZ SSx to SDOx Output High-Impedance(3)
5 — 25 ns —
SP52 TSCH2SSHTSCL2SSH
SSx after SCKx Edge TSCK + 20 — — ns —
Note 1: These parameters are characterized, but not tested in manufacturing.2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.3: The minimum clock period for SCKx is 40 ns.4: Assumes 50 pF load on all SPIx pins.
DS60001156H-page 386 2009-2013 Microchip Technology Inc.
ET10 ERXDx, ERXDV, ERXERR Setup and Hold 10 — 30 ns See Figure 31-22
RMII Timing Requirements
ET11 Reference Clock Frequency — 50 — MHz —
ET12 Reference Clock Duty Cycle 35 — 65 % —
ET13 ETXDx, ETEN, Setup and Hold 2 — 16 ns —
ET14 ERXDx, ERXDV, ERXERR Setup and Hold 2 — 16 ns —
Note 1: The Ethernet module is functional at VBORMIN < VDD < 2.9V, but with degraded performance. Unless other-wise stated, module functionality is tested, but not characterized.
ET3 (Hold)(Setup) ET3
MDC
MDIO
VIHMIN
VILMAX
VIHMIN
VILMAX
VIHMIN
VILMAX
VIHMIN
VILMAX
ET4
MDC
MDIO
DS60001156H-page 394 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 31-21: TRANSMIT SIGNAL TIMING RELATIONSHIPS AT THE MII
FIGURE 31-22: RECEIVE SIGNAL TIMING RELATIONSHIPS AT THE MII
ET7
TX Clock
ETXD<3:0>,
VIHMIN
VILMAX
VIHMIN
VILMAXETEN,ETXERR
ET10 (Hold)
RX Clock
ERXD<3:0>,
VIHMIN
VILMAX
VIHMIN
VILMAX
(Setup) ET10
ERXDV,ERXERR
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TABLE 31-36: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions (see Note 5): 2.5V to 3.6V(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial-40°C TA +105°C for V-Temp
Param. No.
Symbol Characteristics Min. Typical Max. Units Conditions
Device Supply
AD01 AVDD Module VDD Supply Greater ofVDD – 0.3
or 2.5
— Lesser ofVDD + 0.3
or 3.6
V—
AD02 AVSS Module VSS Supply VSS — VSS + 0.3 V —
Reference Inputs
AD05AD05a
VREFH Reference Voltage High AVSS + 2.02.5
——
AVDD
3.6VV
(Note 1)VREFH = AVDD (Note 3)
AD06 VREFL Reference Voltage Low AVSS — VREFH – 2.0 V (Note 1)
AD07 VREF Absolute Reference Voltage (VREFH – VREFL)
2.0 — AVDD V (Note 3)
AD08AD08a
IREF Current Drain ——
250—
4003
AA
ADC operatingADC off
Analog Input
AD12 VINH-VINL Full-Scale Input Span VREFL — VREFH V —
AD13 VINL Absolute VINL Input Voltage
AVSS – 0.3 — AVDD/2 V —
AD14 VIN Absolute Input Voltage AVSS – 0.3 — AVDD + 0.3 V —
AD15 Leakage Current — ±0.001 ±0.610 A VINL = AVSS = VREFL = 0V,AVDD = VREFH = 3.3VSource Impedance = 10 k
AD17 RIN Recommended Impedance of Analog Voltage Source
— — 5K (Note 1)
ADC Accuracy – Measurements with External VREF+/VREF-
Note 1: These parameters are not characterized or tested in manufacturing.
2: With no missing codes.
3: These parameters are characterized, but not tested in manufacturing.
4: Characterized with a 1 kHz sine wave.
5: The ADC module is functional at VBORMIN < VDD < 2.5V, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized.
DS60001156H-page 396 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
ADC Accuracy – Measurements with Internal VREF+/VREF-
Standard Operating Conditions (see Note 5): 2.5V to 3.6V(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial-40°C TA +105°C for V-Temp
Param. No.
Symbol Characteristics Min. Typical Max. Units Conditions
Note 1: These parameters are not characterized or tested in manufacturing.
2: With no missing codes.
3: These parameters are characterized, but not tested in manufacturing.
4: Characterized with a 1 kHz sine wave.
5: The ADC module is functional at VBORMIN < VDD < 2.5V, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized.
2009-2013 Microchip Technology Inc. DS60001156H-page 397
Standard Operating Conditions (see Note 3): 2.5V to 3.6V(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial-40°C TA +105°C for V-Temp
ADC Speed(2) TAD Minimum
Sampling Time
Minimum
RS Maximum
VDD ADC Channels Configuration
1 Msps to 400 ksps(1)
65 ns 132 ns 500 3.0V to 3.6V
Up to 400 ksps 200 ns 200 ns 5.0 k 2.5V to 3.6V
Note 1: External VREF- and VREF+ pins must be used for correct operation.
2: These parameters are characterized, but not tested in manufacturing.
3: The ADC module is functional at VBORMIN < VDD < 2.5V, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized.
VREF- VREF+
ADCANx
S&H
CHX
VREF- VREF+
ADCANx
S&H
CHX
ANx or VREF-
orAVSS
orAVDD
DS60001156H-page 398 2009-2013 Microchip Technology Inc.
AD63 TDPU Time to Stabilize Analog Stage from Analog-to-Digital Off to Analog-to-Digital On(3)
— — 2 s —
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures.
3: Characterized by design but not tested.
4: The ADC module is functional at VBORMIN < VDD < 2.5V, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized.
2009-2013 Microchip Technology Inc. DS60001156H-page 399
1 – Software sets ADxCON. ADON to start AD operation.
2 – Sampling starts after discharge period.
3 – Convert bit 9.
4 – Convert bit 8.
5 – Convert bit 0.
AD50
ch0_samp
eoc
7 3
AD55
6 – One TAD for end of conversion.
7 – Begin conversion of next channel.
8 – Sample for time specified by SAMC<4:0>.
TSAMPTCONV
3 4
Execution
TSAMP is described in Section 17. “10-bit A/D Converter” (DS60001104) of the “PIC32 Family Reference Manual.
2009-2013 Microchip Technology Inc. DS60001156H-page 401
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FIGURE 31-25: PARALLEL SLAVE PORT TIMING
CS
RD
WR
PMD<7:0>
PS1
PS2
PS3
PS4
PS5
PS6
PS7
TABLE 31-39: PARALLEL SLAVE PORT REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Param.No.
Symbol Characteristics(1) Min. Typical Max. Units Conditions
PS1 TdtV2wrH Data In Valid before WR or CS Inactive (setup time)
20 — — ns —
PS2 TwrH2dtI WR or CS Inactive to Data-In Invalid (hold time)
40 — — ns —
PS3 TrdL2dtV RD and CS Active to Data-Out Valid
— — 60 ns —
PS4 TrdH2dtI RD Activeor CS Inactive to Data-Out Invalid
0 — 10 ns —
PS5 Tcs CS Active Time TPB + 40 — — ns —
PS6 TWR WR Active Time TPB + 25 — — ns —
PS7 TRD RD Active Time TPB + 25 — — ns —
Note 1: These parameters are characterized, but not tested in manufacturing.
DS60001156H-page 402 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 31-26: PARALLEL MASTER PORT READ TIMING DIAGRAM
TPB TPB TPB TPB TPB TPB TPB TPB
PB Clock
PMALL/PMALH
PMD<7:0>
PMA<13:18>
PMRD
PMCS<2:1>
PMWR
PM5
DataAddress<7:0>
PM1
PM3
PM6
Data
PM7
Address<7:0>
Address
PM4
PM2
TABLE 31-40: PARALLEL MASTER PORT READ TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Param. No.
Symbol Characteristics(1) Min. Typical Max. Units Conditions
PM1 TLAT PMALL/PMALH Pulse Width — 1 TPB — — —
PM2 TADSU Address Out Valid to PMALL/PMALH Invalid (address setup time)
— 2 TPB — — —
PM3 TADHOLD PMALL/PMALH Invalid to Address Out Invalid (address hold time)
— 1 TPB — — —
PM4 TAHOLD PMRD Inactive to Address Out Invalid(address hold time)
5 — — ns —
PM5 TRD PMRD Pulse Width — 1 TPB — — —
PM6 TDSU PMRD or PMENB Active to Data In Valid (data setup time)
15 — — ns —
PM7 TDHOLD PMRD or PMENB Inactive to Data In Invalid (data hold time)
— 80 — ns —
Note 1: These parameters are characterized, but not tested in manufacturing.
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FIGURE 31-27: PARALLEL MASTER PORT WRITE TIMING DIAGRAM
TPB TPB TPB TPB TPB TPB TPB TPB
PB Clock
PMALL/PMALH
PMD<7:0>
PMA<13:18>
PMWR
PMCS<2:1>
PMRD
PM12PM13
PM11
Address
Address<7:0> Data
PM2 + PM3
PM1
TABLE 31-41: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Param. No.
Symbol Characteristics(1) Min. Typical Max. Units Conditions
PM11 TWR PMWR Pulse Width — 1 TPB — — —
PM12 TDVSU Data Out Valid before PMWR or PMENB goes Inactive (data setup time)
— 2 TPB — — —
PM13 TDVHOLD PMWR or PMEMB Invalid to Data Out Invalid (data hold time)
— 1 TPB — — —
Note 1: These parameters are characterized, but not tested in manufacturing.
DS60001156H-page 404 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-42: USB OTG ELECTRICAL SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Param. No.
Symbol Characteristics(1) Min. Typical Max. Units Conditions
USB313 VUSB3V3 USB Voltage 3.0 — 3.6 V Voltage on VUSB3V3 must be in this range for proper USB operation
USB315 VILUSB Input Low Voltage for USB Buffer — — 0.8 V —
USB316 VIHUSB Input High Voltage for USB Buffer 2.0 — — V —
USB318 VDIFS Differential Input Sensitivity — — 0.2 V The difference between D+ and D- must exceed this value while VCM is met
USB319 VCM Differential Common Mode Range 0.8 — 2.5 V —
USB320 ZOUT Driver Output Impedance 28.0 — 44.0 —
USB321 VOL Voltage Output Low 0.0 — 0.3 V 14.25 k load connected to 3.6V
USB322 VOH Voltage Output High 2.8 — 3.6 V 14.25 k load connected to ground
Note 1: These parameters are characterized, but not tested in manufacturing.
2009-2013 Microchip Technology Inc. DS60001156H-page 405
PIC32MX5XX/6XX/7XX
FIGURE 31-28: EJTAG TIMING CHARACTERISTICS
TTCKeye
TTCKhigh TTCKlowTrf
Trf
TrfTrf
TTsetup TThold
TTDOout TTDOzstate
Defined Undefined
TTRST*low
Trf
TCK
TDO
TRST*
TDI
TMS
TABLE 31-43: EJTAG TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Param.No.
Symbol Description(1) Min. Max. Units Conditions
EJ1 TTCKCYC TCK Cycle Time 25 — ns —
EJ2 TTCKHIGH TCK High Time 10 — ns —
EJ3 TTCKLOW TCK Low Time 10 — ns —
EJ4 TTSETUP TAP Signals Setup Time Before Rising TCK
5 — ns —
EJ5 TTHOLD TAP Signals Hold Time After Rising TCK
3 — ns —
EJ6 TTDOOUT TDO Output Delay Time from Falling TCK
— 5 ns —
EJ7 TTDOZSTATE TDO 3-State Delay Time from Falling TCK
— 5 ns —
EJ8 TTRSTLOW TRST Low Time 25 — ns —
EJ9 TRF TAP Signals Rise/Fall Time, All Input and Output
— — ns —
Note 1: These parameters are characterized, but not tested in manufacturing.
DS60001156H-page 406 2009-2013 Microchip Technology Inc.
2009
-2013 Microchip T
echnology Inc.
DS
60001156H
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PIC
32MX
5XX
/6XX
/7XX
3
F
F
IVER PINS
IVER PINS
re provided for design guidance purposested may be outside the specified operating
VOL (V)
50 2.00 2.50 3.00 3.50 4.00
VOL (V)
3V
3.3V
3.6V
Absolute Maximum
VOL (V)8X
50 2.00 2.50 3.00 3.50 4.00
VOL (V)8X
3V
3.3V
3.6V
Absolute Maximum
2.0 DC AND AC DEVICE CHARACTERISTICS GRAPHS
IGURE 32-1: VOH – 4x DRIVER PINS
IGURE 32-2: VOH – 8x DRIVER PINS
FIGURE 32-3: VOL – 4x DR
FIGURE 32-4: VOL – 8x DR
Note: The graphs provided following this note are a statistical summary based on a limited number of samples and aonly. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presenrange (e.g., outside specified power supply range) and therefore, outside the warranted range.
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33.0 PACKAGING INFORMATION
33.1 Package Marking Information
PIC32MX575F512H-80I/PT
05100173e
Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.
3e
64-Lead TQFP (10x10x1 mm)
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXYYWWNNN
Example
100-Lead TQFP (12x12x1 mm)
XXXXXXXXXXXXXXXXXXXXXXXXYYWWNNN
Example
PIC32MX575F512L-80I/PT0510017
3e
100-Lead TQFP (14x14x1 mm)
XXXXXXXXXXXXXXXXXXXXXXXXYYWWNNN
Example
PIC32MX575F512L-80I/PF0510017
3e
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33.1 Package Marking Information (Continued)
XXXXXXXXXX
64-Lead QFN (9x9x0.9 mm)
XXXXXXXXXXXXXXXXXXXXYYWWNNN
PIC32MX575F
Example
512H-80I/MR
05100173e
XXXXXXXXXX
121-Lead TFBGA (10x10x1.1 mm)
XXXXXXXXXXXXXXXXXXXXYYWWNNN
PIC32MX575F
Example
512H-80I/BG
05100173e
Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.
3e
XXXXXXXXXX
124-Lead VTLA (9x9x0.9 mm)
XXXXXXXXXXXXXXXXXXXXYYWWNNN
PIC32MX795F
Example
512L-80I/TL
05100173e
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33.2 Package Details
The following sections give the technical details of the packages.
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
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PIC32MX5XX/6XX/7XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
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APPENDIX A: MIGRATING FROM PIC32MX3XX/4XX TO PIC32MX5XX/6XX/7XX DEVICES
This appendix provides an overview of considerationsfor migrating from PIC32MX3XX/4XX devices to thePIC32MX5XX/6XX/7XX family of devices. The codedeveloped for the PIC32MX3XX/4XX devices can beported to the PIC32MX5XX/6XX/7XX devices aftermaking the appropriate changes outlined below.
A.1 DMA
PIC32MX5XX/6XX/7XX devices do not supportstopping DMA transfers in Idle mode.
A.2 Interrupts
PIC32MX5XX/6XX/7XX devices have persistentinterrupts for some of the peripheral modules. Thismeans that the interrupt condition for these peripheralsmust be cleared before the interrupt flag can becleared.
For example, to clear a UART receive interrupt, theuser application must first read the UART Receiveregister to clear the interrupt condition and then clearthe associated UxIF flag to clear the pending UARTinterrupt. In other words, the UxIF flag cannot becleared by software until the UART Receive register isread.
Table A-1 outlines the peripherals and associatedinterrupts that are implemented differently onPIC32MX5XX/6XX/7XX versus PIC32MX3XX/4XXdevices.
In addition, on the SPI module, the IRQ numbers for thereceive done interrupts were changed from 25 to 24and the transfer done interrupts were changed from 24to 25.
TABLE A-1: PIC32MX3XX/4XX VERSUS PIC32MX5XX/6XX/7XX INTERRUPT IMPLEMENTATION DIFFERENCES
Module Interrupt Implementation
Input Capture To clear an interrupt source, read the Buffer Result (ICxBUF) register to obtain the number of capture results in the buffer that are below the interrupt threshold (specified by ICI<1:0> bits).
SPI Receive and transmit interrupts are controlled by the SRXISEL<1:0> and STXISEL<1:0> bits, respectively. To clear an interrupt source, data must be written to, or read from, the SPIxBUF register to obtain the number of data to receive/transmit below the level specified by the SRXISEL<1:0> and STXISEL<1:0> bits.
UART TX interrupt will be generated as soon as the UART module is enabled.Receive and transmit interrupts are controlled by the URXISEL<1:0> and UTXISEL<1:0> bits, respectively. To clear an interrupt source, data must be read from, or written to, the UxRXREG or UxTXREG registers to obtain the number of data to receive/transmit below the level specified by the URXISEL<1:0> and UTXISEL<1:0> bits.
ADC All samples must be read from the result registers (ADC1BUFx) to clear the interrupt source.
PMP To clear an interrupt source, read the Parallel Master Port Data Input/Output (PMDIN/PMDOUT) register.
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APPENDIX B: REVISION HISTORY
Revision A (August 2009)
This is the initial released version of this document.
Revision B (November 2009)
The revision includes the following global update:
Added Note 2 to the shaded table that appearsat the beginning of each chapter. This new noteprovides information regarding the availability ofregisters and their associated bits.
Other major changes are referenced by their respectivechapter/section in Table B-1.
TABLE B-1: MAJOR SECTION UPDATES
Section Name Update Description
“High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers”
Added the following devices:
- PIC32MX575F256L
- PIC32MX695F512L
- PIC32MX695F512H
The 100-pin TQFP pin diagrams have been updated to reflect the current pin name locations (see the “Pin Diagrams” section).
Added the 121-pin Ball Grid Array (XBGA) pin diagram.
4.0 “Memory Organization” Added new Memory Maps (Figure 4-1, Figure 4-2 and Figure 4-3).
The bit named I2CSIF was changed to I2C1SIF and the bit named I2CBIF was changed to I2C1BIF in the Interrupt Register Map tables (Table 4-2, Table 4-3, Table 4-4, Table 4-5, Table 4-6 and Table 4-7)
Added the following devices to the Interrupt Register Map (Table 4-2):
Added the following devices to the Interrupt Register Map (Table 4-6):
• PIC32MX664F064L• PIC32MX664F128L
Added the following device to the Interrupt Register Map (Table 4-7):
• PIC32MX764F128L
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4.0 “Memory Organization” (Continued)
Made the following bit name changes in the I2C1, I2C3, I2C4 and I2C5 RegisterMap (Table 4-11):
• I2C3BRG SFR: I2C1BRG was changed to I2C3BRG• I2C4BRG SFR: I2C1BRG was changed to I2C4BRG• I2C5BRG SFR: I2C1BRG was changed to I2C5BRG• I2C4TRN SFR: I2CT1DATA was changed to I2CT2ADATA• I2C4RCV SFR: I2CR2DATA was changed to I2CR2ADATA• I2C5TRN SFR: I2CT1DATA was changed to I2CT3ADATA• I2C5RCV SFR: I2CR1DATA was changed to I2CR3ADATA
Added the RTSMD bit and UEN<1:0> bits to the UART1A, UART1B, UART2A,UART2B, UART3A and UART3B Register Map (Table 4-13)
Added the SIDL bit to the DMA Global Register Map (Table 4-17).
Changed the CM bit to CMR in the System Control Register Map (Table 4-23).
Added the following devices to the I2C2, SPI1, PORTA, PORTC, PORTD,PORTE, PORTF, PORTG, Change Notice and Pull-up Register Maps (Table 4-12,Table 4-14, Table 4-24, Table 4-27, Table 4-29, Table 4-31, Table 4-33, Table 4-35and Table 4-36):
Added the following devices to the PORTC, PORTD, PORTE, PORTF, PORTG,Change Notice and Pull-up Register Maps (Table 4-26, Table 4-28, Table 4-30,Table 4-32, Table 4-34 and Table 4-37):
Appendix A: “Migrating from PIC32MX3XX/4XX to PIC32MX5XX/6XX/7XX Devices”
Removed the A.3 Pin Assignments sub-section.
TABLE B-4: SECTION UPDATES (CONTINUED)
Section Name Update Description
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Revision G (May 2011)
The revision includes the following global update:
• All references to VDDCORE/VCAP have been changed to: VCORE/VCAP
• Added references to the new V-Temp temperature range: -40ºC to +105ºC
This revision also includes minor typographical andformatting changes throughout the data sheet text.Major updates are referenced by their respectivesection in Table B-5.
TABLE B-5: MAJOR SECTION UPDATES
Section Name Update Description
High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers
Removed the shading for all D- and D+ pins in all pin diagrams.
1.0 “Device Overview” Updated the VBUS description in Table 1-1.
1.0 “Guidelines for Getting Started with 32-bit Microcontrollers”
Added “Alternatively, inputs can be reserved by connecting the pin to Vss through a 1k to 10k resistor and configuring the pin as an input.”.
4.0 “Memory Organization” Added Note 3 to the Interrupt Register Map tables (see Table 4-2 through Table 4-7.
22.0 “10-bit Analog-to-Digital Converter (ADC)”
Updated the ADC Conversion Clock Period Block Diagram (see Figure 22-2).
1.0 “Comparator Voltage Reference (CVREF)”
Updated the Comparator Voltage Reference Block Diagram (see Figure 1-1).
1.0 “Special Features” Removed the second paragraph from 1.3.1 “On-Chip Regulator and POR”.
1.0 “Electrical Characteristics” Added the new V-Temp temperature range (-40ºC to +105ºC) to the heading of all specification tables.
Updated the Ambient temperature under bias, updated the Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V, and added Voltage on VBUS with respect to Vss in Absolute Maximum Ratings.
Added the characteristic, DC5a to Operating MIPS vs. Voltage (see Table 1-1).
Updated or added the following parameters to the Operating Current (IDD) DC Characteristics: DC20, DC20b, DC23, and DC23b (see Table 1-5).
Added the following parameters to the Idle Current (IIDLE) DC Characteristics: DC30b, DC33b, DC34c, DC35c, and DC36c (see Table 1-6).
Added the following parameters to the Power-down Current (IPD) DC Characteristics: DC40g, DC40h, DC40i, and DC41g, (see Table 1-7).
Added parameter IM51 and Note 3 to the I2Cx Bus Data Timing Requirements (Master Mode) (see Table 1-32).
Updated the 10-bit ADC Conversion Rate Parameters (see Table 1-37).
Updated parameter AD57 (TSAMP) in the Analog-to-Digital Conversion Timing Requirements (see Table 1-38).
1.0 “Packaging Information” Updated the 64-Lead Plastic Quad Flat, No Lead Package (MR) – 9x9x0.9 mm Body [QFN] packing diagram.
Product Identification System Added the new V-Temp (V) temperature information.
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Revision H (March 2013)
This revision includes the following global updates:
• Where applicable, control register tables have been added to the document
• All references to VCORE were removed
• All occurrences of XBGA have been updated to: TFBGA
• All occurrences of VUSB have been updated to: VUSB3V3
This revision also includes minor typographical andformatting changes throughout the data sheet text.
All other significant changes are referenced by theirrespective section in Table B-6.
TABLE B-6: MAJOR SECTION UPDATES
Section Name Update Description
“32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM) with Graphics Interface, USB, CAN, and Ethernet”
Updated Core features.
Added the VTLA to the Packages table.
Added Note 5 to the Feature tables (see Table 1, Table 2, and Table 3).
Section 2.0 “Guidelines for Getting Started with 32-bit MCUs”
The Recommended Minimum Connection was updated (see Figure 2-1).
Section 5.0 “Flash Program Memory”
A note regarding Flash page size and row size was added.
Section 8.0 “Oscillator Configuration”
The RP resistor was added and Note 1 was updated in the Oscillator Diagram (see Figure 8-1).
Section 31.0 “Electrical Characteristics”
Added Note 1 to Operating MIPS vs. Voltage (see Table 31-1).
Added the VTLA package to Thermal Packaging Characteristics (see Table 31-3).
Added Note 2 to DC Temperature and Voltage Specifications (see Table 31-4).
Updated Note 2 in the Operating Current DC Characteristics (see Table 31-5).
Updated Note 1 in the Idle Current DC Characteristics (see Table 31-6).
Updated Note 1 in the Power-Down Current DC Characteristics (see Table 31-7).
Updated the I/O Pin Output Specifications (see Table 31-9).
Added Note 2 to the BOR Electrical Characteristics (see Table 31-10).
Added Note 3 to the Comparator Specifications (see Table 31-13).
Parameter D320 (VCORE) was removed (see Table 31-15).
Updated the Minimum value for parameter OS50 (see Table 31-18).
Parameter SY01 (TPWRT) was removed (see Table 31-22).
Note 1 was added and the conditions for parameters ET3, ET4, ET7, and ET9 were updated in the Ethernet Module Specifications (see Table 31-35).
Added Note 6 to the ADC Module Specifications (see Table 31-36).
Added Note 3 to the 10-bit ADC Conversion Rate Parameter (see Table 31-37).
Added Note 4 to the Analog-to-Digital Conversion Timing Requirements (see Table 31-38).
The following figures were added:
• Figure 31-19: “MDIO Sourced by the PIC32 Device”
• Figure 31-21: “Transmit Signal Timing Relationships at the MII”
• Figure 31-22: “Receive Signal Timing Relationships at the MII”
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Section 32.0 “DC and AC Device Characteristics Graphs”
This new chapter was added.
Section 33.0 “Packaging Information”
Added the 124-lead VTLA package information (see Section 33.1 “Package Marking Information” and Section 33.2 “Package Details”).
“Product Identification System”
Added the TL definition for VTLA packages.
TABLE B-6: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Description
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NOTES:
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Layout......................................................................... 55Microchip Internet Web Site.............................................. 443Migration
PIC32MX3XX/4XX to PIC32MX5XX/6XX/7XX......... 425MPLAB ASM30 Assembler, Linker, Librarian................... 356MPLAB Integrated Development Environment Software.. 355MPLAB PM3 Device Programmer .................................... 358MPLAB REAL ICE In-Circuit Emulator System ................ 357MPLINK Object Linker/MPLIB Object Librarian ................ 356
Parallel Master Port (PMP) ............................................... 229PIC32 Family USB Interface Diagram............................... 174Pinout I/O Descriptions (table) ............................................ 34Power-on Reset (POR)
and On-Chip Voltage Regulator ................................ 350Power-Saving Features..................................................... 337
CPU Halted Methods ................................................ 337Operation .................................................................. 337with CPU Running..................................................... 337
AD1CHS (ADC Input Select) .................................... 253AD1CON1 (ADC Control 1) ...................................... 249AD1CON2 (ADC Control 2) ...................................... 251AD1CON3 (ADC Control 3) ...................................... 252AD1CSSL (ADC Input Scan Select) ......................... 254ALRMDATE (Alarm Date Value) ............................... 245ALRMTIME (Alarm Time Value) ............................... 244BMXBOOTSZ (Boot Flash (IFM) Size) ..................... 122BMXCON (Bus Matrix Configuration) ....................... 117BMXDKPBA (Data RAM Kernel Program
Base Address) .................................................. 118BMXDRMSZ (Data RAM Size) ................................. 121BMXDUDBA (Data RAM User Data Base Address) . 119BMXDUPBA (Data RAM User Program
Base Address) .................................................. 120BMXPFMSZ (Program Flash (PFM) Size) ................ 122BMXPUPBA (Program Flash (PFM) User Program
Base Address) .................................................. 121CHEACC (Cache Access) ........................................ 149CHECON (Cache Control) ........................................ 148CHEHIT (Cache Hit Statistics) .................................. 154CHELRU (Cache LRU) ............................................. 153CHEMIS (Cache Miss Statistics) .............................. 154CHEMSK (Cache TAG Mask) ................................... 151CHETAG (Cache TAG)............................................. 150CHEW0 (Cache Word 0)........................................... 151CHEW1 (Cache Word 1)........................................... 152CHEW2 (Cache Word 2)........................................... 152CHEW3 (Cache Word 3)........................................... 153CiCFG (CAN Baud Rate Configuration).................... 258CiCON (CAN Module Control) .................................. 256CiFIFOBA (CAN Message Buffer Base Address) ..... 283CiFIFOCINn (CAN Module Message Index Register ‘n’)
288CiFIFOCONn (CAN FIFO Control Register ‘n’)......... 284CiFIFOINTn (CAN FIFO Interrupt Register ‘n’) ......... 286CiFIFOUAn (CAN FIFO User Address Register ‘n’).. 288CiFLTCON0 (CAN Filter Control 0)........................... 266CiFLTCON1 (CAN Filter Control 1)........................... 268CiFLTCON2 (CAN Filter Control 2)........................... 270CiFLTCON3 (CAN Filter Control 3)........................... 272
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THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site atwww.microchip.com. This web site is used as a meansto make files and information easily available tocustomers. Accessible by using your favorite Internetbrowser, the web site contains the followinginformation:
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip consultant program member listing
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CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keepcustomers current on Microchip products. Subscriberswill receive e-mail notification whenever there arechanges, updates, revisions or errata related to aspecified product family or development tool of interest.
To register, access the Microchip web site atwww.microchip.com. Under “Support”, click on“Customer Change Notification” and follow theregistration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistancethrough several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Development Systems Information Line
Customers should contact their distributor,representative or field application engineer (FAE) forsupport. Local sales offices are also available to helpcustomers. A listing of sales offices and locations isincluded in the back of this document.
Technical support is available through the web siteat: http://microchip.com/support
2009-2013 Microchip Technology Inc. DS60001156H-page 443
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchipproduct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which ourdocumentation can better serve you, please FAX your comments to the Technical Publications Manager at(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO: Technical Publications Manager
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DS60001156HPIC32MX5XX/6XX/7XX
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS60001156H-page 444 2009-2013 Microchip Technology Inc.
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PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Architecture MX = 32-bit RISC MCU core
Product Groups 5XX = General purpose microcontroller family6XX = General purpose microcontroller family7XX = General purpose microcontroller family
Flash Memory Family F = Flash program memory
Program Memory Size 256 = 256K512 = 512K
Pin Count H = 64-pinL = 100-pin
Speed 80 = 80 MHz
Temperature Range I = -40°C to +85°C (Industrial)V = -40°C to +105°C (V-Temp)
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NOTES:
DS60001156H-page 446 2009-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.
2009-2013 Microchip Technology Inc.
QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV
== ISO/TS 16949 ==
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their respective companies.
Microchip received ISO/TS-16949:2009 certification for its worldwide
DS60001156H-page 447
headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS60001156H-page 448 2009-2013 Microchip Technology Inc.
AMERICASCorporate Office2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 480-792-7200 Fax: 480-792-7277Technical Support: http://www.microchip.com/supportWeb Address: www.microchip.com
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