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PIC16(L)F170X/171XCost Effective 8-Bit Intelligent Analog Flash Microcontrollers
Description:PIC16F(L)170X/171X microcontrollers combine Intelligent Analog integration with low cost and extreme low power (XLP) tosuit a variety of general purpose applications. These 14 to 44-pin devices deliver on-chip Op Amps, Core IndependentPeripherals (CLC, NCO and COG), Peripheral Pin Select and Zero-Cross Detect, providing for increased design flexibility.
Core Features:• C Compiler Optimized RISC Architecture• Only 49 Instructions• Operating Speed:
• Interrupt Capability• 16-Level Deep Hardware Stack• Up to Four 8-bit Timers• One 16-bit Timer• Power-on Reset (POR)• Power-up Timer (PWRT)• Low-Power Brown-Out Reset (LPBOR)• Programmable Watchdog Timer (WDT) up to 256s• Programmable Code Protection
Memory:• Up to 16 Kwords Flash Program Memory• Up to 2048 Bytes Data SRAM Memory• Direct, Indirect and Relative Addressing modes
Operating Characteristics:• Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF170X/171X)- 2.3V to 5.5V (PIC16F170X/171X)
• Temperature Range:- Industrial: -40°C to 85°C- Extended: -40°C to 125°C
PIC16F1703 x x x xPIC16F1704 x x x xPIC16F1705 x x x xPIC16F1707 x x x xPIC16F1708 x x x xPIC16F1709 x x x xPIC16F1713 x x x x xPIC16F1716 x x x x xPIC16F1717 x x xPIC16F1718 x x x x xPIC16F1719 x x x
DS40001708A-page 2 Advance Information 2013 Microchip Technology Inc.
PIC16(L)F170X/171X
PIN DIAGRAM – 14-PIN PDIP, SOIC, SSOP
PIN DIAGRAM – 16-PIN QFN
PIC
16(L
)F17
03PI
C16
(L)F
1704
PIC
16(L
)F17
05
1234567
VDD
RA5RA4
VPP/MCLR/RA3RC5RC4RC3
RA0/ICSPDATRA1/ICSPCLKRA2RC0RC1RC2
1413121110
98
VSS
Note: See Table 1 and Table 2 for the pin allocation tables.
23
1
9101112
RC
4
4
VS
S
RA0/ICSPDATRA1/ICSPCLKRA2RC0
NC
NCV
DD
RA5RA4
RA3/MCLR/VPP
RC5
RC
3R
C2
RC
1
6 75 8
15 1416 13
PIC16(L)F1703PIC16(L)F1704PIC16(L)F1705
Note: See Table 1 and Table 2 or the pin allocation tables.
2013 Microchip Technology Inc. Advance Information DS40001708A-page 3
PIC16(L)F170X/171X
PIN DIAGRAM – 20-PIN PDIP, SOIC, SSOP
PIN DIAGRAM – 20-PIN QFN
PIC
16(L
)F17
07PI
C16
(L)F
1708
PIC
16(L
)F17
09
2
3
4
5
6
7
8
9
10
VDD
RA5
RA4
VPP/MCLR/RA3
RC5
RC4
RC3RC6
RC7
RB7
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RC0
RC1
RC2RB4
RB5
RB6
20
19
18
17
16
15
1413
12
11
VSS1
Note: See Table 3 and Table 4 for the pin allocation tables.
2345
1
6 7 8 9
20 19 18 17 1610
12131415
11
PIC16(L)F1707PIC16(L)F1708PIC16(L)F1709
RB4
RB5
RB6
RB7
RC
7
VPP/MCLR/RA3RC5RC4RC3RC6
RA
4R
A5
VD
DV
SS
RA
0/IC
SP
DAT
RA1/ICSPCLKRA2RC0RC1RC2
Note: See Table 3 and Table 4 for the pin allocation tables.
DS40001708A-page 4 Advance Information 2013 Microchip Technology Inc.
PIC16(L)F170X/171X
PIN DIAGRAM – 28-PIN PDIP, SOIC, SSOP
PIN DIAGRAM – 28-PIN (U)QFN
PIC
16L(
F)17
13/6
/8
1
2
3
4
5
6
789
10
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
RA4RA5
RB6
RB5
RB4
RB3RB2RB1RB0
VDD
VSS
11
12
13
14 15
16
17
18
1920
28
27
26
25
2423
22
21VSS
RA7
RA6RC0
RC1RC2
RC3
RC5
RC4
RC7
RC6
RB7
Note: See Table 5 and Table 6 for the pin allocation table.
23
6
1
18192021
1571617
RC
0
54
RB
7R
B6
RB
5R
B4
RB0VDD
VSS
RC7
RC
6R
C5
RC
4
RE
3/M
CLR
/VP
P
RA
0R
A1
RA2RA3RA4RA5VSS
RA7RA6
RC
1R
C2
RC
3
9 10 138 141211
27 26 2328 222425
PIC16L(F)1713/6/8
RB3RB2RB1
Note: See Table 5 and Table 6 for the pin allocation table.
2013 Microchip Technology Inc. Advance Information DS40001708A-page 5
PIC16(L)F170X/171X
PIN DIAGRAM – 40-PIN PDIP
PIC
16L(
F)17
17/9
2
3
4
5
6
789
10
VPP/MCLR/RE3
RA0RA1
RA2
RA3
RA4RA5RE0
RE1RE2
RB6/ICSPCLK
RB5
RB4
RB0
VDD
VSS
RD2
11
12
13
14
15
16
1718
19
20
40
39
38
37
36
35
343332
3130
29
28
27
26
25
2423
22
21
VDD
VSS
RA7
RA6RC0
RC1
RC2RC3RD0
RD1
RC5RC4RD3
RD4
RC7
RC6
RD7
RD6
RD5
RB7/ICSPDAT1
RB3
RB2RB1
Note: See Table 7 and Table 8 for the pin allocation table.
DS40001708A-page 6 Advance Information 2013 Microchip Technology Inc.
PIC16(L)F170X/171X
PIN DIAGRAM – 44-PIN TQFP (10x10)
PIN DIAGRAM – 40-PIN UQFN (5x5)
1011
23
6
1
18 19 20 21 2212 13 14 15
38
87
44 43 42 41 40 3916 17
2930313233
232425262728
36 3435
9
37
54
PIC16L(F)1717/9
RC
6R
C5
RC
4R
D3
RD
2R
D1
RD
0R
C3
RC
2R
C1
RC0
RA
1R
A0
VPP
/MC
LR/R
E3
RB3
ICS
PD
AT/R
B7
ICS
PC
LK/R
B6
RB
5R
B4
NC
RA
3R
A2
RC7RD4RD5RD6RD7VSSVDDRB0RB1RB2
RA6RA7VSS
NC
VDDRE2RE1RE0RA5RA4
NC
NC
Note: See Table 7 and Table 8 for the pin allocation table.
10
11
2
3456
1
18 19 20
2122
12 13 14 1538
87
40 39
16 17
2930
313233
232425262728
36 3435
9
37
RA
1R
A0
VPP
/MC
LR/R
E3
RB
3
ICS
PD
AT/R
B7
ICS
PC
LK/R
B6
RB
5R
B4
RC
6R
C5
RC
4R
D3
RD
2R
D1
RD
0R
C3
RC
2R
C1
RC0RA6RA7VSSVDDRE2RE1RE0RA5RA4
RC7RD4RD5RD6RD7VSS
VDD
RB0RB1RB2
PIC16L(F)1717/9
RA
3R
A2
Note: See Table 7 and Table 8 for the pin allocation table.
2013 Microchip Technology Inc. Advance Information DS40001708A-page 7
PIC16(L)F170X/171X
DS
40001708A-page 8
Advance Inform
ation
2013 Microchip Technology Inc.
Pull-
up
Bas
ic
Y ICSPDAT
Y ICSPCLK
Y —
Y MCLRVPP
Y CLKOUT
Y CLKIN
Y —
Y —
Y —
Y —
Y —
Y —
— VDD
— VSS
— —
— —
— —
rs.
TABLE 1: 14-PIN AND 16-PIN ALLOCATION TABLE (PIC16(L)F1703)I/O
(2)
PDIP
/SO
IC/S
SOP
QFN
AD
C
Ref
eren
ce
Op
Am
p
Zero
Cro
ss
Tim
ers
CC
P
MSS
P
CLC
Inte
rrup
t
RA0 13 12 AN0 VREF- — — — — — — IOC
RA1 12 11 AN1 VREF+ — — — — — — IOC
RA2 11 10 AN2 — — ZCD T0CKI(1) — — — INT(1)
IOC
RA3 4 3 — — — — — — — — IOC
RA4 3 2 AN3 — — — T1G(1) — — — IOC
RA5 2 1 — — — — T1CKI(1) — — — IOC
RC0 10 9 AN4 — OPA1IN+ — — — SCK(1)
SCL(3)— IOC
RC1 9 8 AN5 — OPA1IN- — — — SDI(1)
SDA(3)— IOC
RC2 8 7 AN6 — OPA1OUT — — — — — IOC
RC3 7 6 AN7 — OPA2OUT — — CCP2(1) SS(1) — IOC
RC4 6 5 — — OPA2IN- — — — — — IOC
RC5 5 4 — — OPA2IN+ — — CCP1(1) — — IOC
VDD 1 16 — — — — — — — — —
VSS 14 13 — — — — — — — — —
OUT(2)
— — — — — — — CPP1 SDA(3) — —
— — — — — — — CPP2 SCL(3)
SCK— —
— — — — — — — — SDO — —
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. 2: All pin digital outputs default to PORT latch data. Any pin can be selected as a peripheral digital output with the PPS output selection registe3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
2013 M
icrochip Technology Inc.A
dvance Information
DS
40001708A-page 9
PIC16(L)F170X/171X
TA
EUSA
RT
CLC
Inte
rrup
t
Pull-
up
Bas
ic
R — — IOC Y ICSPDAT
R — — IOC Y ICSPCLK
R — — INT(1)
IOCY —
R — — IOC Y MCLRVPP
R — — IOC Y CLKOUTOSC2
R — CLCIN3(1) IOC Y CLKINOSC1
R — — IOC Y —
R — CLCIN2(1) IOC Y —
R — — IOC Y —
R — CLCIN0(1) IOC Y —
R K(1) CLCIN1(1) IOC Y —
R X(3) — IOC Y —
V — — — — VDD
V — — — — VSS
O
CK CLC1OUT — — —
T(3) CLC2OUT — — —
TX CLC3OUT — — —
— — — — —
No
BLE 2: 14-PIN AND 16-PIN ALLOCATION TABLE (PIC16(L)F1704/5)I/O
te 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. 2: All pin digital outputs default to PORT latch data. Any pin can be selected as a peripheral digital output with the PPS output selection registers. 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. 2: All pin digital outputs default to PORT latch data. Any pin can be selected as a peripheral digital output with the PPS output selection registe3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
2013 M
icrochip Technology Inc.A
dvance Information
DS
40001708A-page 11
PIC16(L)F170X/171X
TA
EUSA
RT
CLC
Inte
rrup
t
Pull-
up
Bas
ic
— — IOC Y ICSPDAT
— — IOC Y ICSPCLK
— — INT(1)
IOCY —
— — IOC Y MCLRVPP
— — IOC Y CLKOUTOSC2
— CLCIN3(1) IOC Y CLKINOSC1
— — IOC Y —
X(1) (3)
IOC Y —
— — IOC Y —
K(1) (3)
— IOC Y —
— — IOC Y —
— CLCIN2(1) IOC Y —
— — IOC Y —
— CLCIN0(1) IOC Y —
— CLCIN1(1) IOC Y —
— — IOC Y —
— — IOC Y —
— — IOC Y —
— — — — VDD
— — — — VSS
No
BLE 4: 20-PIN ALLOCATION TABLE (PIC16(L)F1708/9)I/O
te 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. 2: All pin digital outputs default to PORT latch data. Any pin can be selected as a peripheral digital output with the PPS output selection registers. 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
PIC16(L)F170X/171X
DS
40001708A-page 12
Advance Inform
ation
2013 Microchip Technology Inc.
) CK CLC1OUT — — —) DT CLC2OUT — — —
TX CLC3OUT — — —
— — — — —
EUSA
RT
CLC
Inte
rrup
t
Pull-
up
Bas
ic
rs.
OUT(2)
— — — — C1OUT — — — — CPP1 PWM3OUT COGA SDA(3
— — — — C2OUT — — — — CPP2 PWM4OUT COGB SCL(3
— — — — — — — — — — — COGC SDO
— — — — — — — — — — — COGD —
I/O(2
)
PDIP
/SO
IC/
SSO
P
QFN
AD
C
Ref
eren
ce
Com
para
tor
Op
Am
p
DA
C
Zero
Cro
ss
Tim
ers
CC
P
PWM
CO
G
MSS
P
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. 2: All pin digital outputs default to PORT latch data. Any pin can be selected as a peripheral digital output with the PPS output selection registe3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
2013 M
icrochip Technology Inc.A
dvance Information
DS
40001708A-page 13
PIC16(L)F170X/171X
TA
Inte
rrup
t
Pull-
up
Bas
ic
R CLCIN0(1) IOC Y
R CLCIN1(1) IOC Y
R IOC Y
R IOC YR IOC YR IOC Y
R IOCOSC2
CLKOUT
R IOCOSC1CLKIN
R INT(1)
IOC
R IOC
R IOC
R IOC
R IOC YR IOC Y
R CLCIN2(1) IOC Y ICSPCLK
R CLCIN3(1) IOC Y ICSPDAT
R IOC Y
R IOC Y
R IOC Y
No
No egisters.
No
No
No
EUSA
RT
CLC
R YIOC
BLE 5: 28-PIN ALLOCATION TABLE (PIC16L(F)1713/6/8) (PART 1)I/O
(2)
PDIP
,SO
IC,
SSO
P
QFN
, UQ
FN
AD
C
Ref
eren
ce
Op
Am
p
DA
C
Zero
Cro
ss
NC
O
A0 2 27 AN0
A1 3 28 AN1 OPA1OUT
A2 4 1 AN2 Vref- DAC1OUT1
A3 5 2 AN3 Vref+A4 6 3 OPA1IN+ T0CKI(1)
A5 7 4 AN4 OPA1IN- DAC2OUT1 nSS(1)
A6 10 7
A7 9 6 NCOCLK
B0 21 18 AN12 ZCD
B1 22 19 AN10 OPA2OUT
B2 23 20 AN8 OPA2IN-
B3 24 21 AN9 OPA2IN+
B4 25 22 AN11B5 26 23 AN13 T1G(1)
B6 27 24 SCL(1)
B7 28 25DAC1OUT2DAC2OUT2
T1CKI(1)
SOSCO
C1 12 9 SOSCI
C2 13 10 AN14
C3 14 11 AN15 SCK(1)
te 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.
te 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection r
te 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
te 4: Alternate outputs are excluded from solid shaded areas.
te 5: Alternate inputs are excluded from dot shaded areas.
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.
Note 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output sele
Note 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
Note 4: Alternate outputs are excluded from solid shaded areas.
Note 5: Alternate inputs are excluded from dot shaded areas.
RC4 15 12 AN16
Com
para
tor
Tim
ers
CO
GIN
Vss
CC
P
PWM
CO
G
2013 M
icrochip Technology Inc.A
dvance Information
DS
40001708A-page 15
PIC16(L)F170X/171X
TA
Inte
rrup
t
Pul
lup
Basi
c
CLCIN0(1) IOC Y
CLCIN1(1) IOC Y
IOC Y
IOC YIOC YIOC Y
IOC OSC2CLKOUT
IOC OSC1CLKIN
INT(1)
IOC
IOC
IOC
IOC
IOC YIOC Y
CLCIN2(1) IOC Y ICSPCLK
CLCIN3(1) IOC Y ICSPDAT
IOC Y
IOC YIOC YIOC Y
registers.
CLC
EUS
ART
YIOC
BLE 7: PIN ALLOCATION TABLE (PIC16L(F)1717/9) (PART 1)I/O
(2)
PDI
P
TQFP
UQFN
ADC
Ref
eren
ce
Op
Am
p
DAC
Zero
Cro
ss
NCO
RA0 2 19 17 AN0
RA1 3 20 18 AN1 OPA1OUT
RA2 4 21 19 AN2 Vref- DAC1OUT1
RA3 5 22 20 AN3 Vref+RA4 6 23 21 OPA1IN+ T0CKI(1)
RA5 7 24 22 AN4 OPA1IN- DAC2OUT1 nSS(1)
RA6 14 31 29
RA7 13 30 28 NCOCLK
RB0 33 8 8 AN12 ZCD
RB1 34 9 9 AN10 OPA2OUT
RB2 35 10 10 AN8 OPA2IN-
RB3 36 11 11 AN9 OPA2IN+
RB4 37 14 12 AN11RB5 38 15 13 AN13 T1G(1)
RB6 39 16 14 SCL(1)
RB7 40 17 15 DAC1OUT2DAC2OUT2
T1CKI(1)
SOSCO
RC1 16 35 31 SOSCI
RC2 17 36 32 AN14RC3 18 37 33 AN15 SCK(1)
SDI(1)
SDA(1)
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers. Note 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection
Note 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.Note 4: Alternate outputs are excluded from solid shaded areas.
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers. Note 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS outp
Note 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.Note 4: Alternate outputs are excluded from solid shaded areas.Note 5: Alternate inputs are excluded from dot shaded areas.
Com
para
tor
Tim
ers
CCP
PWM
CO
G
Vdd
Vss
CO
GIN
Note the following details of the code protection feature on Microchip devices:• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.
2013 Microchip Technology Inc. Advance Info
QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV
== ISO/TS 16949 ==
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their respective companies.
Microchip received ISO/TS-16949:2009 certification for its worldwide
rmation DS40001708A-page 17
headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS40001708A-page 18 Advance Information 2013 Microchip Technology Inc.
AMERICASCorporate Office2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 480-792-7200 Fax: 480-792-7277Technical Support: http://www.microchip.com/supportWeb Address: www.microchip.comAtlantaDuluth, GA Tel: 678-957-9614 Fax: 678-957-1455BostonWestborough, MA Tel: 774-760-0087 Fax: 774-760-0088ChicagoItasca, IL Tel: 630-285-0071 Fax: 630-285-0075ClevelandIndependence, OH Tel: 216-447-0464 Fax: 216-447-0643DallasAddison, TX Tel: 972-818-7423 Fax: 972-818-2924DetroitFarmington Hills, MI Tel: 248-538-2250Fax: 248-538-2260IndianapolisNoblesville, IN Tel: 317-773-8323Fax: 317-773-5453Los AngelesMission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608Santa ClaraSanta Clara, CA Tel: 408-961-6444Fax: 408-961-6445TorontoMississauga, Ontario, CanadaTel: 905-673-0699 Fax: 905-673-6509