Physics 124: Lecture 5physics124.barreiro.ucsd.edu/wp-content/uploads/... · Phys 124: Lecture 5 13 Logic Family Levels • CMOS is closer to the “ideal” that logic low is zero

Physics124:Lecture5

Binary,Hexadecimal,andLogic

adaptedfromT.Murphy’slectures

Binary,HexadecimalNumbers• Computersstoreinformationinbinary

– 1or0,correspondingtoVCC and0volts,typically– theCCsubscriptoriginatesfrom“collector”oftransistor

• Becomefamiliarwithbinarycountingsequence

2Phys124:Lecture8

binary decimal hexadecimal

00000000 0 0x00

0000 0001 1 0x01

00000010 2 0x02

00000011 2+1=3 0x03

00000100 4 0x04

00000101 4+1 =5 0x05

etc.

1111 1100 128+64+32+16+8+4 =252 0xfc

11111101 128+64+32+16+8+4+1=253 0xfd

11111110 128+64+32+16+8+4+2=254 0xfe

11111111 128+64+32+16+8+4+2+1=255 0xff

BinarytoHex:easy!• Noteseparationofprevious8-bit(one-byte)numbersintotwo4-bitpieces(nibbles)– makesexpressioninhex(base-16;4-bits)natural

Phys124:Lecture8 3

binary hexadecimal decimal

0000 0 0

0001 1 1

0010 2 2

0011 3 3

0100 4 4

0101 5 5

0110 6 6

0111 7 7

1000 8 8

1001 9 9

1010 A(lowercasefine) 10

1011 B 11

1100 C 12

1101 D 13

1110 E 14

1111 F 15

Phys 124: Lecture 5 4

Hexadecimal, continued

• Onceitiseasyforyoutorecognizefourbitsatatime,8bitsistrivial:– 01100001is0x61– 10011111is0x9f

• CanbehandybecausetheASCIIcodeisbuiltaroundhex:– ‘A’is0x41,‘B’is0x42,…,‘Z’is0x5a– ‘a’is0x61,‘b’is0x62,…,‘z’is0x7a– ‘Â’(control-A)is0x01,‘^B’is0x02,‘^Z’is0x1a– ‘0’is0x30,‘9’is0x39

0 1 2 3 4 5 6 7

0 NUL ^@ null (\0) DLE ^P SP space 0 @ P ` p

1 SOH Â startofhdr DC1 ^Q ! 1 A Q a q

2 STX ^B starttext DC2 ^R “ 2 B R b r

3 ETX ^C endtext DC3 ^S # 3 C S c s

4 EOT ^D endtrans DC4 ^T $ 4 D T d t

5 ENQ Ê NAK Û % 5 E U e u

6 ACK ^F acknowledge SYN ^V & 6 F V f v

7 BEL ^G bell ETB ^W ‘ 7 G W g w

8 BS ^H backspace CAN ^X ( 8 H X h x

9 HT Î horiz.tab(\t) EM ^Y ) 9 I Y i y

A LF ^J linefeed (\r) SUB ^Z * : J Z j z

B VT ^K verticaltab ESC escape + ; K [ k {

C FF ^L formfeed FS , < L \ l |

D CR ^M carriage ret(\n) GS - = M ] m }

E SO ^N RS . > N ^ n ~

F SI Ô US / ? O _ o DELPhys124:Lecture8 5

firsthexdigitsecond

hexdigit

ASCIITable inHex

ASCIIinHex

• NotethepatternsandconveniencesintheASCIItable– 0thru9ishex0x30to0x39(justadd0x30)– A-Zparallelsa-z;justadd0x20

• startsat0x41and0x61,soHis8th letter, is0x48,etc.

– thefirst32charactersarecontrolcharacters,oftenrepresentedasCtrl-C,denoted̂ C,forinstance

• associatedcontrolcharactersmirror0x40to0x5F• putcommoncontrolcharacters inred;useful toknowinsomeprimitiveenvironments

Phys124:Lecture8 6

Phys124:Lecture5 7

Parenthesis:Thru-holevsSMT(SurfaceMountedTechnology)

Thru-hole

SMT

Phys124:Lecture5 8

Introtosoldering

• https://learn.sparkfun.com/tutorials/how-to-solder-through-hole-soldering

Phys124:Lecture5 9

Solderingequipmentandsupplies

Phys124:Lecture5 10

solder

brasssponge

Solderingtips

soldering irons

solderingwand

“DosandDon’ts”

Phys124:Lecture5 11


LogicFamilies• TTL:transistor-transistorlogic:BJTbased

– subtypes: L(owpower),LS(chotky),F(ast),A(dvanced)S,ALS,orH(igh-speed),LVTTL– output: logichighhasVOH >3.3V;logiclowhasVOL <0.35V– input: logichighhasVIH >2.0V;logiclowhasVIL <0.8V– deadzonebetween0.8Vand2.0V

• nominalthreshold:VT =1.5V

• CMOS:complimentaryMOSFET(Metal-Oxide-Semicond FET)– chipshaveHCorAHCdesignation (AdvancedHigh-speed CMOS)– output: logichighhasVOH >4.7V;logiclowhasVOL <0.2V– input: logichighhasVIH >3.7V;logiclowhasVIL <1.3V– deadzonebetween1.3Vand3.7V

• nominalthreshold:VT =2.5V– chipsw/HCTdesignation areCMOSwithTTL-compatible thresholds


LogicFamilyLevels• CMOSisclosertothe“ideal”that

logiclowiszerovoltsandlogichighis5volts– andhasabiggerdeadzone

• Example:ATTLdevicemust:– interpretanyinputbelow0.8Vas

logic low– interpretanyinputabove2.0Vas

logichigh– putoutatleast 3.3Vforlogichigh– putoutless than0.35Vforlogiclow

• Thediffering input/output thresholdsleadtonoiseimmunity

Phys124:Lecture5 14


Transistors

• Transistorsareversatile,highlynon-lineardevices

• Twofrequentmodesofoperation:– amplifiers/buffers– switches

• Twomainflavors:– npn (more common)orpnp,describingdoping

structure• Alsomanyvarieties:

– bipolarjunctiontransistors(BJTs)suchasnpn,pnp– fieldeffecttransistors(FETs):n-channel andp-

channel– metal-oxide-semiconductor FETs (MOSFETs)

• We’lljusthittheessentialsoftheBJThere– MOSFET laterinlecture

B

C

E

B

E

C

npn pnp


BJTAmplifierMode• Centralideaisthatwhenintherightregime,theBJT

collector-emittercurrent isproportionaltothebasecurrent:– namely, Ice =βIb,where theDCcurrentgainβ (orhfe)is~100– Inthisregime, thebase-emitter voltageis~0.6V– below, Ib =(Vin − 0.6)/Rb; Ice = βIb = β(Vin − 0.6)/Rb– sothatVout =Vcc − IceRc =Vcc − β(Vin − 0.6)(Rc/Rb)– ignoringDCbiases,wigglesonVin becomeβ (Rc/Rb)bigger(and

inverted): thusamplified

out

Rc

Rbin

Vcc

B

C

E


Switching:DrivingtoSaturation• Whatwouldhappenifthebasecurrentissobig thatthe

collectorcurrentgotsobig thatthevoltagedropacrossRc wantstoexceedVcc?– wecallthissaturated:VCE=Vc − Ve cannotdipbelow~0.2V– evenifIb isincreased, Ic won’tbudgeanymore

• Theexamplebelowisagoodlogicinverter– ifVcc =5V;Rc =1kΩ; Ic(sat)≈ 5mA;need Ib >0.05mA– soRb <20kΩ wouldputussafely intosaturationifVin =5V– now5Vin→ ~0.2Vout;<0.6Vin→ 5Vout

out

Rc

Rbin

Vcc

fromLecture3:Transistorasaswitch

Phys124:Lecture3 18

Operateineithercut-off (OFF)orsaturation(ON)regions

Example:Bipolar junctiontransistor(BJT)

http://www.electronics-tutorials.ws/transistor/tran_4.html

Phys124:Lecture3 19

fromLecture3:Transistorasaswitch

OFF

ON

http://www.electronics-tutorials.ws/transistor/tran_4.html


TransistorBuffer

• Inthehookupabove(emitterfollower,orcommoncollector),Vout =Vin − 0.6– soundsuseless, right?– thereisnovoltage“gain,”butthere is currentgain– ImaginewewiggleVin byΔV:Vout wiggles bythesameΔV– sothetransistorcurrentchangesbyΔIe =ΔV/R– butthebasecurrentchanges1/β timesthis(muchless)– sothe“wiggler” thinks theloadisΔV/ΔIb =β·ΔV/ΔIe =βR– theloadthereforeislessformidable

• The“buffer”isawaytodrivealoadwithoutthedriverfeelingthepain(asmuch):it’simpedanceisolation

out

R

in

Vcc


Field-EffectTransistors• The“standard”npn andpnp transistorsusebase-current tocontrolthetransistorcurrent

• FETs useafield(voltage)tocontrolcurrent• Resultisnocurrentflows intothecontrol“gate”• FETs areusedalmostexclusivelyasswitches

– popafewvoltsonthecontrolgate,andtheeffectiveresistanceisnearlyzero

2N7000FET


FETGeneralities• EveryFEThasatleastthree

connections:– source(S)

• akintoemitter(E)onBJT– drain(D)

• akintocollector(C)onBJT– gate(G)

• akintobase(B)onBJT

• Somehaveabodyconnection too– thoughoftentiedtosource

FET

BJT

notepinoutcorrespondence


FETTypes• Twoflavors:n andp• Twotypes:JFET,MOSFET• MOSFETs morecommon• JFETs conduct“bydefault”

– whenVgate =Vsource

• MOSFETs are“open”bydefault– mustturnondeliberately

• JFETs haveap-n junctionatthegate,somustnotforwardbiasmorethan0.6V

• MOSFETs havetotalisolation:dowhatyouwant

0 2 4−2−4

logcurrent

Vgate − Vsource

p-channelMOSFET n-channelMOSFET

n-channelJFET

p-channelJFET


MOSFETSwitches

• MOSFETs,asappliedtologicdesigns,actasvoltage-controlledswitches– n-channel MOSFETisclosed (conducts)whenpositivevoltage

(+5V)isapplied,openwhenzerovoltage– p-channel MOSFETisopenwhenpositivevoltage(+5V)is

applied, closed(conducts) whenzerovoltage• (MOSFETmeansmetal-oxide semiconductor fieldeffecttransistor)

source

drain

gate

source

gate

drain5V 5V

0V0V

5V0V

+voltage +voltage

0V 5V

<5V <5V

n-channelMOSFET p-channelMOSFET

“body”connectionoftentiedto“source”


Datamanipulation

• Alldatamanipulationisbasedonlogic• Logicfollowswelldefinedrules,producingpredictabledigitaloutputfromcertaininput

• Examples:

A B C0 0 00 1 01 0 01 1 1

AND

A B C0 0 00 1 11 0 11 1 1

OR

A B C0 0 00 1 11 0 11 1 0

XOR

A B C0 0 10 1 11 0 11 1 0

NAND

A B C0 0 10 1 01 0 01 1 0

NOR

AB

AB

AB

AB

AB C

bubblesmeaninverted(e.g.,NOTAND→ NAND)

A

A C0 11 0

NOT


Aninverter(NOT)fromMOSFETS:5V

0V

input output

5V

5V

0V

0V

5V

5V0V

0V

• 0VinputturnsOFF lower(n-channel)FET,turnsONupper(p-channel),sooutputisconnectedto+5V

• 5VinputturnsON lower(n-channel)FET,turnsOFFupper(p-channel),sooutputisconnectedto0V– Neteffectislogicinversion: 0→ 5;5→ 0

• ComplementaryMOSFETpairs→ CMOS

A

A C0 11 0

NOT

n-channelMOSFET

p-channelMOSFET


ANANDgatefromscratch:

5V

0V

INA

INB

OUTC

• Bothinputsatzero:– lowertwoFETsOFF,uppertwoON– result isoutputHI

• Bothinputsat5V:– lowertwoFETsON,uppertwoOFF– result isoutputLOW

• INAat5V,INBat0V:– upperleftOFF,lowestON– upperrightON,middleOFF– result isoutputHI

• INAat0V,INBat5V:– opposite ofpreviousentry– result isoutputHI

A B C0 0 10 1 11 0 11 1 0

NAND

AB

0V C

p p

n

n


ANANDgatefromscratch:

5V

0V

INA

INB

OUTC



• INAat5V,INBat0V:– upperleftOFF,lowestON– upperrightON,middleOFF– result isoutputHI

• INAat0V,INBat5V:– opposite ofpreviousentry– result isoutputHI

A B C0 0 10 1 11 0 11 1 0

NAND

AB

0V C

p p

n

n

5V

0V

OFF

OFF

ON

ON


ANORgatefromscratch:

5V

0V

INA

INB

OUTC



• INAat5V,INBat0V:– lowerleftOFF,lowerrightON– upperON,middleOFF– result isoutputLOW

• INAat0V,INBat5V:– opposite ofpreviousentry– result isoutputLOW

A B C0 0 10 1 01 0 01 1 0

NOR

5V

AB

C

justaNANDflippedupside-down…


AllLogicfromNANDsAlone

A B C0 0 10 1 11 0 11 1 0

NAND

AB

A C0 11 0

NOT

A B C0 0 00 1 01 0 01 1 1

AND

A B C0 0 00 1 11 0 11 1 1

OR

A B C0 0 10 1 01 0 01 1 0

NOR

invert output (invert NAND)

invert both inputs

invert inputs and output (invert OR)


Onelasttype:XOR

• XOR=(ANANDB)AND(AORB)• AndthisyoualreadyknowyoucanmakefromcompositeNANDgates(thoughrequiring6total)

• Then,obviously,XNORistheinverseofXOR– sojuststickaninverterontheoutputofXOR

AB

C


RuletheWorld

• NowyouknowhowtobuildALL logicgatesoutofn-channel andp-channel MOSFETs– becauseyoucanbuildaNANDfrom4MOSFETs– andallgatesfromNANDs

• Thatmeansyoucanbuildcomputers

• Sonowyoucanruletheworld!


ArithmeticExample

• Let’saddtwobinarynumbers:00101110= 0x2e=46

+01001101= 0x4d=7701111011= 0x7b=123

• Howdidwedothis?Wehaverules:0+0=0;0+1=1+0=1;1+1=10(2):(0,carry1);1+1+(carried1)=11(3):(1,carry1)

• Rulescanberepresentedbygates– IftwoinputdigitsareA&B,outputdigitlookslikeXOR

operation (butneed toaccountforcarryoperation)

A B C0 0 00 1 11 0 11 1 0

XOR

AB


Canmakeruletable:Cin A B0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

D Cout0 01 01 00 11 00 10 11 1

• DigitsA&Bareadded,possiblyaccompaniedbycarryinstructionfrompreviousstage

• Outputisnewdigit,D,alongwithcarryvalue– DlookslikeXORofA&BwhenCin is0– DlookslikeXNORofA&BwhenCin is1– Cout is1iftwoormoreofA,B,Cin are1


BinaryArithmeticinGates

ABCin

D

CoutF

E

H

G

A B Cin E F H G D Cout0 0 0 0 0 0 0 0 00 1 0 1 1 0 0 1 01 0 0 1 1 0 0 1 01 1 0 0 1 0 1 0 10 0 1 0 0 0 0 1 00 1 1 1 1 1 0 0 11 0 1 1 1 1 0 0 11 1 1 0 1 1 1 1 1

Input Intermediate OutputEach digit requires 6 gates

Each gate has ~6 transistors

~36 transistors per digit

+A

B

Cin

D

Cout

“Integrated” Chip


8-bitbinaryarithmetic(cascaded)

0

1

0

0

1

1

0

1

0

0

1

0

1

1

1

0

0

1

1

1

1

0

1

1

0

0

0

1

1

0

0

00101110 = 46+ 01001101 = 77

01111011 = 123

1 1+

+

+

+

+

+

+

+0

MSB

LSB = Least Significant Bit

Carry-out tied to carry-in of next digit.

“Magically” adds two binary numbers

Up to ~300 transistors for this basicfunction. Also need –, ×, /, & lots more.

Integrated one-digit binary arithmetic unit (prev. slide)


Computertechnologybuiltupfrompieces

• Theforegoingexampleillustratesthewayinwhichcomputertechnologyisbuilt– startwithlittlepieces(transistorsactingasswitches)– combine pieces intofunctionalblocks(gates)– combine theseblocksintohigher-level function(e.g.,addition)– combine thesenewblocksintocascade(e.g.,8-bitaddition)– blocksgetincreasingly complex,morecapable

• Nobodyonearthunderstands everynitofmodernCPU– Grabpreviously developed blocksandrun– Letacomputerdesignthegatearrangements (eyes closed!)


Bitwise logicoperatorsinC• Logicaloperatorsappliedtointegersorcharactersgetappliedbit-wise

– operatorsinclude&(and),|(or),^(xor),~(not)– don’tconfusewithconditional&&(AND),||(OR),etc.(doubled-up)

• Examples:– 21 & 7→ 5:00010101&00000111→ 00000101– 21 & 0xff → 21:00010101&11111111→ 00010101– 21 & 0→ 0:00010101&00000000→ 00000000– 21 | 7→ 23:00010101|00000111→ 00010111– 21 ^ 7→ 18:00010101̂ 00000111→ 00010010– ~21→ 234:~00010101→ 11101010

• Masking– 234 &= 0x1f → 11101010&00011111→ 00001010 =0x0a

• Bitshiftingwith>> or<< operators– 01101011 >> 2→ 00011010 (effectivelydivideby4)– 01101011 << 1→ 11010110 (effectivelymultiply by2)

Physics 124: Lecture 5physics124.barreiro.ucsd.edu/wp-content/uploads/... · Phys 124: Lecture 5 13 Logic Family Levels • CMOS is closer to the “ideal” that logic low is zero

Documents