-
Photonic Logic Gates at 640 Gbits/s
A critical review 28th July 2015
Arjun Iyer EP12B005
Abstract In this review I critically analyse the paper which
demonstrates high speed logic operations for optical communication
for realising logic operations A* And B, B* And A, at 640 Gbits/s.
These operations are realised using only pump depletion in SFG in
PPLN.
Part I Introduction In this paper authors have demonstrated
ultrafast logic gates A* And B, B* And A, at 640 Gbits/s using only
pump depletion in PPLN waveguide for OOK signals. These outputs can
be further used to achieve various other logic gates like XOR, OR,
half subtraction etc. Since only the depleted pumps are of concern,
one gets rid of various undesireable effects like Group velocity
mismatch or generation of additional frequencies etc. The scheme
also ensures a very low BER(bit error rate) particularly desirable
for communication systems. All of these aspects are analysed
through various simulations in MATLAB.
-
1.1 Basic scheme of the proposed method As shown in the figure
above, logic operations are realised by using nonlinear
interaction
between two synchronized optical time demultiplxed signals at
640 Gbits/sec. These interact
nonlinearly within the PPLN waveguide and SFG occurs due to
Quasi Phase Matchin (QPM), the
output at wavelength of A and B represent our desired logic
operations A* And B , B* And A
respectively.
One at this point may be tempted to use the sum frequency
generated itself as logic output as it
would represent A And B, since OR function is very easily
implemented by a optical coupler one
would then be theoretically equipped to implement any logic
systems using these operations, but
the latter suffers major drawback being that the SFG suffers
from Group Velocity
Mismatch(GVM) leading to broadening and distortion of the pulse
and this severly limits the data
speed that can be processed. The effect of group velocity can be
seen in Figure 2.
1.2 Pump Depletion in Quasi Matched PPLN waveguide I will now
demonstrate the depletion of pump in a Quasi phased matched PPLN
waveguide. The
equations governing the SFG process in a three way mixing
process is easily derived from
nonlinear wave equation with a nonlinear source term, which
easily follows from Maxwells
equations. The following equations govern the evolution of the
space dependent amplitude,
these are obtained after one does a 'Slow Varying Amplitude
Approximation'.
-
These are equations are solved in the following simulation in
MATLAB using the Runge-Kutta
(ODE45) Diffrential solver, the precision was set to 15 places
after decimal for maximum
accuracy.
The following parameter values were used for the simulation:
1 =1542 nm k1 =8.7109 1 0 6 m-1, n1 =2.1378
2 =1560 nm k2 =8.608 1 0 6 m-1, n2 =2.1373
then SF then is at 3=( 1 / 1 + 1/ 2 )-1 =775.47nm , k 3 =1.7649
1 0 7 m-1 , n3 =2.1783
Length of PPLN used = 5.00cm
Phase mismatch= k=3.3016 105m-1 Coherence length= Lc =9.51m
Nonlinear coefficient= deff =5.7pm/V
Input incident power of pumps= 500mw and 10mw
Effective area= 50 m2
The following are the simulated results with associated
inferences:
1.) As shown in the figure below, the pump amplitude varies
sinusoidally with distance along the
crystal- when there is no perodic reversal of interaction
coefficient i.e there is no QPM. Pump
depletion is much more prominent for one pump having much larger
power than the other,
and hence authors amplify one of the pumps to much larger value
to efficiently deplete the
other and hence for realising the two logic gates, one will have
to amplify one of the pumps
corresponding to each output, e.g: if one wants to realise A*
And B then one must amplify A
to high powers(27dBm) and vice versa for A And B*; . Authors
suggest using 2 PPLN
waveguides each one optimised for each of the pumps and hence
one can obtain both the
desired operations simultaneously.
-
2.) With the QPM in place the amplitude can now be seen varying
as one would expect in QPM
PPLN waveguide, i.e series of half sinusoids building up on each
other, in the same figure one
can then compare it with the case where there was no QPM and
hence appreciate the
applicability of it.
-
3.) Figure 3 shows the growth of the SFG in the QPM case and the
non-QPM case.
-
4.) Finally, the figure below shows the pump depletion of one of
the pumps over a length of
5cm. The efficiency the process simulated would be =I(L )SFG/I(0
) SFG ,but since we not
interested in the SF component lets define the depleted
efficiency as
=I(0)pump I(L)pump / I(0 )pump which in this case would be-
I(0)pump=2 108 W/m2 ,I(L)pump =1.611 108 W/m2
dep =0.1943, i.e one gets ~20% of depletion efficiency in the
intensity and
correspondingly ~10% efficiency in depletion of amplitude, in
all further calculations
these will be the depletions efficiencies we will be
considering.
-
Part II: Experimental Setup
Figure below shows the complete experimental setup used in this
experiment. The setup consists
of a central Mode Locked Laser (MLL) generating ~1ps pulses at
40GHz at a =1542nm is
modulated in a Mach Zedner Modulator(MZM) at 40Gbits/s .
Psuedo-random sequences are
generated by modulating MZM using Psuedo-Random Binary
Sequence(PBRS). This is then split
into two parts (using the modulator itself). One of the path is
directly multiplexed to 640 Gbits/s
using a 40-to-640 multiplexer, this output then passes through a
polariser so that all the
polarisations are aligned for maximum efficiency( As in this
case one uses d33 coefficient of
LiNbO3 and hence for maximum conversion input beams must be
polarised along extraordiranary
direction).
The second branch is then propagated through 200m of Highly
Nonlinear Fiber(HNLF) with a
high nonlinear coefficient of -0.85ps/nm/km at 1550nm. This
output is then filtered to obtain
40 Gbits/s at b =1560nm . This is then multiplexed to 640
Gbits/s.
For obtaining maximum depletion pertaining the concerned output
the following peak
powers are used, for A* And B is 27dBm power for signal A and
16dBm power for signal B
,for B* And A the reverse is used, ie 27dBm for B and 16dBm for
A . The pulse widths are
~1ps and ~0.9ps. Various other parameters are identical to the
one used in above section
pertaining to pump depletion.
-
The output is then passed through two Band Pass Filters(BPFs)
and then amplified using erbium-
doped amplifier to extract the desired logic gate. Finally, the
output signal is demultiplexed back
to 40Gbits/sec using a NonLinear Optical Loop Mirror(NOLM).
Part III: Simulations
Simulations under ideal conditions
These simulation for the given logic gate under ideal
conditions, such as ignoring noise, walk off
etc, each of these elements will introduces so as to give a
complete picture of these effects on
our results.
First we will begin by demonstrating a few output sequences. For
all consequent simulations I
will assume that A pump depletion is optimised, hence we will
restrict ourselves to A And B*.
The complimentary gate is exactly identical in implementation to
this one.
Let A=111 and B=101. So assuming them to gaussian pulses of ~1ps
they would look like the
figure below(each of the pumps has been seperately
normalised).
-
The figure below would then be the simulated output, for
completely synchronous pulses
suffering no walk-off.
Another example would be A=101, B=011
-
Effect of Group Velocity Mismatch
Since the input pulses are at different central frequency they
would naturally have different
group velocity and hence in the process they could walk off from
each other leading to
distortion effects, in the following figures we would be
studying such effects which could not
only be because of walk off but also fault in the communication
line causing undesireable
delay resulting in non-synchronised pulses at the input.
For the parameters we have considered L=5cm the walk off time
would be merely 0.0018ps
which is negligible. The following simulations are then much
more apt for cases where pulses at
the input are not synchronised owing some undesireable delay in
one of the pulses.
For desynchronisation of 0.5ps
-
The corresponding output for the above input is
This can be repeated to find out the maximum tolerence of such a
system to such
synchronisation errors, which would be when the peak power of
the '0' bit is within some
threshold region of '1' bit which would then be governed by the
sensitivity of detector to
detect small changes. With a reasonable threshold of 0.9 for bit
'0' then increasing this pulse
desynchronisation, could see the tolerence of such a scheme to
such errors. With simulation
results such a time delay threshold is discovered to be ~0.8ps.
The results for this level of delay
is presented below.
-
Corresponding output for such an input would be
-
Introducing Gaussian White noise
Another problem that could be faced is noise in the input
pulses, in this section we try and
simulate the above results and seeing the effects of Gaussian
White Noise on the output at
various SNR, giving us an idea as to how much noise can such an
implementation handle.
The following simulation is again simulated with the same input
sequence of A=111 and B=101,
but this time we add various levels of noise and then analyse
the output.
The following is the output with SNR=50
-
It is clearly visible that at SNR=50 the high and the low levels
are easily distinguishable.
The following is the output with SNR=30.
Even at SNR of 30 the bits seem to be visually seperable,
continuing these simulations one can
find the SNR at which the bit '1' and bit '0' become
indistinguishable, and that was seen at SNR
of 25. The point to be noted is that these are without any
further amplification. With post output
amplification one can obtain even cleaner outputs at worser
SNR's.
-
Bit error rate analysis(BER)
In this section we will be analysing the error rates in such a
system, even though for such
calculations extensive experimentation is required to confirm
such parameters. A good guess
can be made regarding the penalty that would be required to get
a decent BER.
We will be making an approximation by assuming ideal OOK
signals(square pulses) rather than
gaussian pulses as this massively simplifies calculations at the
same time giving a good
estimate of BER. Additionally we will be assuming as above that
the whole process induces a
gaussian white noise(including the final amplification) and we
will then calculate BER by first
calculating Q(quality factor).
Quality factor is measure of how far the '0' bit and '1' bit are
which is calculated by:
Q=1- 0/1+0
Where signifies the average of the '1' and '0' bits and refers
to the std.deviation at '1' and
'0' respectively. The Bit Error Rate is defined as number of
error bits as a ratio of total number of
bits. Given Q one can find BER by the following formula:
BER= 0.5 x erfc(Q /2 )
For the same bit sequences ie A=111 and B=101, in the square
approximation we would have
the following:
-
The corresponding output to the above input sequence would then
be:
-
To study the effects of noise we will now add gaussian white
noise to the amplitude starting
with a reasonable value of SNR as 30 and in this configuration
study the penalty that one would
have to bear in the form of further amplification and its effect
on BER.
The effect of this gaussian white noise would look like the
figure below and also attached is
the output of such an input:
-
Consider the Histogram of its output:
One can see a large intersection of the Gaussian pointing
towards the fact that the quality is poor
at SNR=30 to improve this one must amplify the output.
Below is the Bimodal Gaussian curve fitted for the above
histogram:
-
Now consider amplifying the same input sequence by 2dB then the
output obtained would be:
-
One can then construct the histogram corresponding to the output
obtained above which is
displayed below, and thing to notice is that one can see clear
seperation of the '1' bit and '0' bit
with increasing amplification and hence this results in
significant decrease BER rates which is
confirmed by the calculations below.
-
One can clearly see a much better seperation and hence a much
better bit rate. One can go on to
curve fit bimodal gaussians to this and then proceed to
calculate Q value. The curve fitting is
shown below.
The Q value for the above plot was calculated to be 2.3767 which
corresponds to a BER of
3.88 10-5 compared to Q value without amplification which was
calculated to be 1.294 and
corresponding BER would be 6.7 10-2. Hence just by an
amplification of 2dB one sees a massive
decrease in the BER and hence massive improvement in the
effectiveness of the scheme.
-
One can further amplify the signal so obtained to obtain much
higher Q values, for eg:
simulations for amplification of 3dB were done. The bimodal
gaussian for 3dB amplification is
presented below:
Part IV Advantages and disadvantages
Advantages and possible applications 1.) This implementation of
logic gates is elegant and efficient as it bypasses many
processing
cost that would otherwise be present in alternative methods
which get very complex due to
the number of processes taking place(like many methods require
combining SFG and DFG)and
also outputs of such methods of implementation requires it to be
compensated through
various methods. For e.g: the most evident of this being that
this has no effect due to grou
velocity dispersion and hence larger lengths of PPLN can be used
without getting cocerned by
GVM or walk-off between the input pulses.
-
2.) These PPLN can be operated at room temperature and hence do
not require seperate
temperature control setup and in process saving power otherwise
that would be consumed in
such a control. In this case it has to be ensured that at the
room temperature the wavelength
mismatch is sufficiently small for considerable efficiency.
3.) The input pulses undergo negligible( but observable)
chromatic dispersion or distortions that
accompany nonlinear processes, and since (2) are extremely
sensitive to phase matching
hence noise frequencies cannot propagate through such a medium
making it very robust to
noise, which would otherwise be present in (3) processes.
4.) This nonlinear process preserves phase information and hence
can be additionally exploited
for phase-shift keying signals.
5.) This method of implementation also produces excllent BER
with power penalities of ~2dB.
6.) These outputs can be further used for operations like
OR,XOR, half subtracter etc. Hence can
realize a multitude of logic operations in this scheme.
2.) Disadvantages Since SFG processes are sensitive to input
polarisations it is necessary to compensate any
polarisations rotations etc and requires many polarisers to
maximise efficiency.
Pump depletion effects cannot be simulataneously maximised for
both the signals one of the
signals needs to be amplified to 27dBm for efficient depletion
of the other pump. Hence for
realising both A* And B, B* And A one will have to use two
different PPLN for realising each of the
outputs. One of which will have A signal amplified to 27dBm and
the other one would have B
amplified.
The difference between 0 and 1 level is extremely small, 0 is
just 0.8 of 1 without amplification and hence to detect such levels
one requires extremely sensitive detectors or one needs post output
amplification.
-
Part V Conclusion The above method of implementation has been
reviewed through the use of simulations and found
to be effective for high speed data applications, even though it
has a lot of elements in its
implimentation, simplicity in its working principle ensures a
good BER especially useful for
communication systems.