1 Photomask Technology Challenges at the 45nm Node Patrick Martin
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1
Photomask Technology Challenges at the 45nm Node
Patrick Martin
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Mask Materials and Infrastructure
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Significance of 193nm Immersion to Mask Making
Materials Engineering
nki)k(nne 2222~~ +−==
λπkd
eRODonTransmissi4
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−=−=
∆φ = (2π / λ)(ni-1) t
( )22
1min
NAk
DOF
NAk
R
λ
λ
=
=
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Significance of 193nm Immersion to Mask Making
Fused SiO2Low Birefringence
Absorber
ARC (Reflectivity)
Pellicle
193nm WetλAttribute
157nm (Dry)
193nm Dry
Attenuator (PSM)Variable T%
Substrate Fused SiO2Low Birefringence
F2 Doped
Chrome,Other
Fused SiO2
TBD %
Chrome,Other
MoSi,Other
<5%15 – 20 %
Organic
SiON + MNMoSi,Other
Chrome
Fused SiOrganic
Avoidance: Process Development/Integration of 157nmOpportunity: Material Properties for Immersion
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Limiting Industry Trends
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2001 2002 2003 2004 2005 2006 2007 2008 2009 2010
Nor
mal
ized
Inde
x
130nm
90nm
65nm
45nm Est
Mask Unit
# of SemiconductorCompanies
ASIC Design Starts
Development cycles are accelerating, but everything elseis going in the wrong direction!!! Source: Dataquest
Photronics estimate
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Cost Drivers
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Equipment
Repair and Disposition
Inspection
Write Platform
No Known Solution
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Impact of Model-Based OPC
§ Nominal design is shaded.§ OPC version is fractured into rectangles.§ Up to 10× increase in shape count when OPC applied.§ Several hundred billion geometries on mask at 100 nm node.
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Vector Tool Write Time ImpactD
esig
nV
ecto
r
Model-Based OPCRule-Based OPCNo OPC
12 Shots 27 Shots2 Shots
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Write Time vs. Complexity
§ A 90nm device with very aggressive OPC can take up to 20 hrs to write on a $15 million E-beam tool.
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100
200
300
400
500
600
Via(Optical)
Contact(EB)
Metal (EB)
Active(EB)
Gate (EB)
Wri
te T
ime
(min
ute
s)
130nm90nm65nm
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# Layers by Stepper Wavelength
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5
10
15
20
25
30
35
40
45
DRAM Logic
193nm/193i248nmi-line
180nm130nm 110nm
90nm
65nm
180nm 130nm
90nm
65nm
Lay
ers
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B1 B2 B3 B4 B5 B6 B7 B8 B8 E1 E2 E3 A1 A2 C1Product Type
No
rmal
ized
Pri
ce
Cost vs. Complexity
180nm
130nm
90nm
Code: B = Binary, E = EAPSM, A = AAPSM, C = CPL
65nm
130nm
90nm
90nm
65nm
No OPC, 248nm Mild OPC, 193nm Aggressive OPC, 193nm
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Mask Cost for 45nmØ General Assumptionsü 193nm wet compared to 157nm dry
§ 193nm Dry Not Capable of 45nm
ü 7 year depreciation model on cap ex of ~70 M$ü Single Line, No Redundancyü 3 layer AAPSM, 12 layer EAPSM, 22 Layer BIMü First three years of engagement (not mature)
ü Moderate OPC, k1 ≤ 0.35 on critical layersü 8 customers total, 3 captiveü 12 Tape Outs
2.5 – 3.5 x/90nm Set
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Mask Cost is only 8% of the Overall Problem
Wafers1%
Boards2% Masks
8%
Software28%
Apps3%
Test Engineering
7%
Product Engineering
12%
I/O Design5%
Logic Design34%
Source: Synopsys, Altera, 90nm Node
The only way to bring the development cost down is to have all involved work together.
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Integrating the Lithography Plane(ILP)
Electrical Design
Design Layout
Mask Build
Do over !
Wafer Build Is it OK ?
$$$$ wasted assilicon piles up on the floor
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0.5
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1.5
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2.5
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4X 180nm 4X 90nm 8X 90nm
No
rmal
ized
Mas
t S
et C
ost
(1)
EAPSM 193nmBinary 193nmEAPSM 248nmBinary 248nmBinary 365nm
Increase Magnification, Reduce Field Size
§ If magnification increases to 8X, current 180nm process and tool set can be used for 90nm production.
+ 7X+ 3X
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Summary
§ Advantages of 193nm Immersion Lithography§ Single Wavelength Solution through 2009§ Simplification of Materials; blank and pellicle§ Simplification of Internal Process Development
and Integration§ Overall Cost Benefit vs. 157nm Dry
§ Opportunity§ Integration with Design and Reticle Enhancement
Technology is Key to Cost Minimization§ Small Field § Higher Magnification, 4x – 8x reduction ratio§ Reduced Field Size
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