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Published by QM/JY 0966 BU TV Consumer Care Printed in the Netherlands Subject to modification EN 3122 785 18400
Contents Page Contents Page1. Revision List 22. Technical Specifications, Connections, and Chassis
Overview 23. Precautions, Notes, and Abbreviation List 54. Mechanical Instructions 95. Service Modes, Error Codes, and Fault Finding 136. Alignments 167. Circuit Descriptions 188. IC Data Sheets 229. Block Diagrams
2. Technical Specifications, Connections, and Chassis Overview
Index of this chapter:2.1 Technical Specifications2.2 Directions for Use2.3 Connections2.4 Chassis Overview
Notes:• Figures can deviate due to the different set executions.• Specifications are indicative (subject to change).
2.1 Technical Specifications
For on-line product support please use the links in Table 2-1. Here is product information available, as well as getting started, user manuals, frequently asked questions and software & drivers.
Table 2-1 Described Model Numbers:
Note: The given Model Numbers are subject to change.
2.2 Directions for Use
Directions for use can be downloaded from the following websites:http://www.philips.com/supporthttp://www.p4c.philips.com
13 - Service Connector (UART)1 - UART_TX Transmit �
2 - Ground Gnd �
3 - UART_RX Receive �
2.4 Chassis Overview
Refer to chapter 9. Block Diagrams for PWB/CBA locations.
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Precautions, Notes, and Abbreviation List EN 5TPM3.1E LA 3.
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3. Precautions, Notes, and Abbreviation List
Index of this chapter:3.1 Safety Instructions3.2 Warnings3.3 Notes3.4 Abbreviation List
3.1 Safety Instructions
Safety regulations require the following during a repair:• Connect the set to the Mains/AC Power via an isolation
transformer (> 800 VA).• Replace safety components, indicated by the symbol ,
only by components identical to the original ones. Any other component substitution (other than original type) may increase risk of fire or electrical shock hazard. Of de set ontploft!
Safety regulations require that after a repair, the set must be returned in its original condition. Pay in particular attention to the following points: • Route the wire trees correctly and fix them with the
mounted cable clamps.• Check the insulation of the Mains/AC Power lead for
external damage. • Check the strain relief of the Mains/AC Power cord for
proper function.• Check the electrical DC resistance between the Mains/AC
Power plug and the secondary side (only for sets that have a Mains/AC Power isolated power supply): 1. Unplug the Mains/AC Power cord and connect a wire
between the two pins of the Mains/AC Power plug. 2. Set the Mains/AC Power switch to the “on” position
(keep the Mains/AC Power cord unplugged!). 3. Measure the resistance value between the pins of the
Mains/AC Power plug and the metal shielding of the tuner or the aerial connection on the set. The reading should be between 4.5 MΩ and 12 MΩ.
4. Switch “off” the set, and remove the wire between the two pins of the Mains/AC Power plug.
• Check the cabinet for defects, to prevent touching of any inner parts by the customer.
3.2 Warnings
• All ICs and many other semiconductors are susceptible to electrostatic discharges (ESD ). Careless handling during repair can reduce life drastically. Make sure that, during repair, you are connected with the same potential as the mass of the set by a wristband with resistance. Keep components and tools also at this same potential.
• Be careful during measurements in the high voltage section.
• Never replace modules or other components while the unit is switched “on”.
• When you align the set, use plastic rather than metal tools. This will prevent any short circuits and the danger of a circuit becoming unstable.
3.3 Notes
3.3.1 General
• Measure the voltages and waveforms with regard to the chassis (= tuner) ground (�), or hot ground (�), depending on the tested area of circuitry. The voltages and waveforms shown in the diagrams are indicative. Measure them in the Service Default Mode with a colour bar signal and stereo sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and
picture carrier at 475.25 MHz for PAL, or 61.25 MHz for NTSC (channel 3).
• Where necessary, measure the waveforms and voltages with (�) and without (�) aerial signal. Measure the voltages in the power supply section both in normal operation ( ) and in stand-by (�). These values are indicated by means of the appropriate symbols.
3.3.2 Schematic Notes
• All resistor values are in ohms, and the value multiplier is often used to indicate the decimal point location (e.g. 2K2 indicates 2.2 kΩ).
• Resistor values with no multiplier may be indicated with either an “E” or an “R” (e.g. 220E or 220R indicates 220 Ω).
• All capacitor values are given in micro-farads (μ = × 10-6), nano-farads (n = × 10-9), or pico-farads (p = × 10-12).
• Capacitor values may also use the value multiplier as the decimal point indication (e.g. 2p2 indicates 2.2 pF).
• An “asterisk” (*) indicates component usage varies. Refer to the diversity tables for the correct values.
• The correct component values are listed on the Philips Spare Parts Web Portal.
3.3.3 Spare Parts
For the latest spare part overview, consult your Philips Spare Part web portal.
3.3.4 BGA (Ball Grid Array) ICs
IntroductionFor more information on how to handle BGA devices, visit this URL: http://www.atyourservice-magazine.com. Select “Magazine”, then go to “Repair downloads”. Here you will find Information on how to deal with BGA-ICs.
BGA Temperature ProfilesFor BGA-ICs, you must use the correct temperature-profile. Where applicable and available, this profile is added to the IC Data Sheet information section in this manual.
3.3.5 Lead-free Soldering
Due to lead-free technology some rules have to be respected by the workshop during a repair:• Use only lead-free soldering tin. If lead-free solder paste is
required, please contact the manufacturer of your soldering equipment. In general, use of solder paste within workshops should be avoided because paste is not easy to store and to handle.
• Use only adequate solder tools applicable for lead-free soldering tin. The solder tool must be able:– To reach a solder-tip temperature of at least 400°C.– To stabilize the adjusted temperature at the solder-tip.– To exchange solder-tips for different applications.
• Adjust your solder tool so that a temperature of around 360°C - 380°C is reached and stabilized at the solder joint. Heating time of the solder-joint should not exceed ~ 4 sec. Avoid temperatures above 400°C, otherwise wear-out of tips will increase drastically and flux-fluid will be destroyed. To avoid wear-out of tips, switch “off” unused equipment or reduce heat.
• Mix of lead-free soldering tin/parts with leaded soldering tin/parts is possible but PHILIPS recommends strongly to avoid mixed regimes. If this cannot be avoided, carefully clear the solder-joint from old tin and re-solder with new tin.
Precautions, Notes, and Abbreviation ListEN 6 TPM3.1E LA3.
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3.3.6 Alternative BOM identification
It should be noted that on the European Service website, “Alternative BOM” is referred to as “Design variant”.
The third digit in the serial number (example: AG2B0335000001) indicates the number of the alternative B.O.M. (Bill Of Materials) that has been used for producing the specific TV set. In general, it is possible that the same TV model on the market is produced with e.g. two different types of displays, coming from two different suppliers. This will then result in sets which have the same CTN (Commercial Type Number; e.g. 28PW9515/12) but which have a different B.O.M. number.By looking at the third digit of the serial number, one can identify which B.O.M. is used for the TV set he is working with.If the third digit of the serial number contains the number “1” (example: AG1B033500001), then the TV set has been manufactured according to B.O.M. number 1. If the third digit is a “2” (example: AG2B0335000001), then the set has been produced according to B.O.M. no. 2. This is important for ordering the correct spare parts!For the third digit, the numbers 1...9 and the characters A...Z can be used, so in total: 9 plus 26= 35 different B.O.M.s can be indicated by the third digit of the serial number.
Identification: The bottom line of a type plate gives a 14-digit serial number. Digits 1 and 2 refer to the production centre (e.g. AG is Bruges), digit 3 refers to the B.O.M. code, digit 4 refers to the Service version change code, digits 5 and 6 refer to the production year, and digits 7 and 8 refer to production week (in example below it is 2006 week 17). The 6 last digits contain the serial number.
Figure 3-1 Serial number (example)
3.3.7 Board Level Repair (BLR) or Component Level Repair (CLR)
If a board is defective, consult your repair procedure to decide if the board has to be exchanged or if it should be repaired on component level.If your repair procedure says the board should be exchanged completely, do not solder on the defective board. Otherwise, it cannot be returned to the O.E.M. supplier for back charging!
3.3.8 Practical Service Precautions
• It makes sense to avoid exposure to electrical shock. While some sources are expected to have a possible dangerous impact, others of quite high potential are of limited current and are sometimes held in less regard.
• Always respect voltages. While some may not be dangerous in themselves, they can cause unexpected reactions that are best avoided. Before reaching into a powered TV set, it is best to test the high voltage insulation. It is easy to do, and is a good service precaution.
3.4 Abbreviation List
0/6/12 SCART switch control signal on A/V board. 0 = loop through (AUX to TV), 6 = play 16 : 9 format, 12 = play 4 : 3 format
AARA Automatic Aspect Ratio Adaptation: algorithm that adapts aspect ratio to remove horizontal black bars; keeps the original aspect ratio
ACI Automatic Channel Installation: algorithm that installs TV channels directly from a cable network by means of a predefined TXT page
ADC Analogue to Digital ConverterAFC Automatic Frequency Control: control
signal used to tune to the correct frequency
AGC Automatic Gain Control: algorithm that controls the video input of the feature box
AM Amplitude ModulationAP Asia PacificAR Aspect Ratio: 4 by 3 or 16 by 9ASF Auto Screen Fit: algorithm that adapts
aspect ratio to remove horizontal black bars without discarding video information
ATSC Advanced Television Systems Committee, the digital TV standard in the USA
ATV See Auto TVAuto TV A hardware and software control
system that measures picture content, and adapts image parameters in a dynamic way
AV External Audio VideoAVC Audio Video ControllerAVIP Audio Video Input ProcessorB/G Monochrome TV system. Sound
carrier distance is 5.5 MHzBLR Board-Level RepairBTSC Broadcast Television Standard
Committee. Multiplex FM stereo sound system, originating from the USA and used e.g. in LATAM and AP-NTSC countries
B-TXT Blue TeleteXTC Centre channel (audio)CEC Consumer Electronics Control bus:
remote control bus on HDMI connections
CL Constant Level: audio output to connect with an external amplifier
CLR Component Level RepairComPair Computer aided rePairCP Connected Planet / Copy ProtectionCSM Customer Service ModeCTI Color Transient Improvement:
manipulates steepness of chroma transients
CVBS Composite Video Blanking and Synchronization
DAC Digital to Analogue ConverterDBE Dynamic Bass Enhancement: extra
low frequency amplificationDDC See “E-DDC”D/K Monochrome TV system. Sound
carrier distance is 6.5 MHzDFI Dynamic Frame InsertionDFU Directions For Use: owner's manualDMR Digital Media Reader: card readerDMSD Digital Multi Standard DecodingDNM Digital Natural Motion
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DNR Digital Noise Reduction: noise reduction feature of the set
DRAM Dynamic RAMDRM Digital Rights ManagementDSP Digital Signal ProcessingDST Dealer Service Tool: special remote
control designed for service technicians
DTCP Digital Transmission Content Protection; A protocol for protecting digital audio/video content that is traversing a high speed serial bus, such as IEEE-1394
DVB-C Digital Video Broadcast - CableDVB-T Digital Video Broadcast - TerrestrialDVD Digital Versatile DiscDVI(-d) Digital Visual Interface (d= digital only)E-DDC Enhanced Display Data Channel
(VESA standard for communication channel and display). Using E-DDC, the video source can read the EDID information form the display.
EDID Extended Display Identification Data (VESA standard)
EEPROM Electrically Erasable and Programmable Read Only Memory
EMI Electro Magnetic InterferenceEPLD Erasable Programmable Logic DeviceEU EuropeEXT EXTernal (source), entering the set by
SCART or by cinches (jacks)FDS Full Dual Screen (same as FDW)FDW Full Dual Window (same as FDS)FLASH FLASH memoryFM Field Memory or Frequency
ModulationFPGA Field-Programmable Gate ArrayFTV Flat TeleVisionGb/s Giga bits per secondG-TXT Green TeleteXTH H_sync to the module HD High DefinitionHDD Hard Disk DriveHDCP High-bandwidth Digital Content
Protection: A “key” encoded into the HDMI/DVI signal that prevents video data piracy. If a source is HDCP coded and connected via HDMI/DVI without the proper HDCP decoding, the picture is put into a “snow vision” mode or changed to a low resolution. For normal content distribution the source and the display device must be enabled for HDCP “software key” decoding.
HDMI High Definition Multimedia InterfaceHP HeadPhoneI Monochrome TV system. Sound
carrier distance is 6.0 MHzI2C Inter IC busI2D Inter IC Data busI2S Inter IC Sound busIF Intermediate FrequencyIR Infra RedIRQ Interrupt RequestITU-656 The ITU Radio communication Sector
(ITU-R) is a standards body subcommittee of the International Telecommunication Union relating to radio communication. ITU-656 (a.k.a. SDI), is a digitized video format used for broadcast grade video. Uncompressed digital component or digital composite signals can be used. The SDI signal is self-synchronizing,
uses 8 bit or 10 bit data words, and has a maximum data rate of 270 Mbit/s, with a minimum bandwidth of 135 MHz.
ITV Institutional TeleVision; TV sets for hotels, hospitals etc.
LS Last Status; The settings last chosen by the customer and read and stored in RAM or in the NVM. They are called at start-up of the set to configure it according to the customer's preferences
LATAM Latin AmericaLCD Liquid Crystal DisplayLED Light Emitting DiodeL/L' Monochrome TV system. Sound
carrier distance is 6.5 MHz. L' is Band I, L is all bands except for Band I
LPL LG.Philips LCD (supplier)LS LoudspeakerLVDS Low Voltage Differential SignallingMbps Mega bits per secondM/N Monochrome TV system. Sound
carrier distance is 4.5 MHzMIPS Microprocessor without Interlocked
Pipeline-Stages; A RISC-based microprocessor
MOP Matrix Output ProcessorMOSFET Metal Oxide Silicon Field Effect
Transistor, switching deviceMPEG Motion Pictures Experts GroupMPIF Multi Platform InterFaceMUTE MUTE LineNC Not ConnectedNICAM Near Instantaneous Compounded
Audio Multiplexing. This is a digital sound system, mainly used in Europe.
NTC Negative Temperature Coefficient, non-linear resistor
NTSC National Television Standard Committee. Color system mainly used in North America and Japan. Color carrier NTSC M/N= 3.579545 MHz, NTSC 4.43= 4.433619 MHz (this is a VCR norm, it is not transmitted off-air)
NVM Non-Volatile Memory: IC containing TV related data such as alignments
O/C Open CircuitOSD On Screen DisplayOTC On screen display Teletext and
Control; also called Artistic (SAA5800)P50 Project 50: communication protocol
between TV and peripheralsPAL Phase Alternating Line. Color system
mainly used in West Europe (color carrier= 4.433619 MHz) and South America (color carrier PAL M= 3.575612 MHz and PAL N= 3.582056 MHz)
PCB Printed Circuit Board (same as “PWB”)PCM Pulse Code ModulationPDP Plasma Display PanelPFC Power Factor Corrector (or Pre-
conditioner)PIP Picture In PicturePLL Phase Locked Loop. Used for e.g.
FST tuning systems. The customer can give directly the desired frequency
POD Point Of Deployment: a removable CAM module, implementing the CA system for a host (e.g. a TV-set)
POR Power On Reset, signal to reset the uPPTC Positive Temperature Coefficient,
non-linear resistorPWB Printed Wiring Board (same as “PCB”)
Precautions, Notes, and Abbreviation ListEN 8 TPM3.1E LA3.
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PWM Pulse Width ModulationQRC Quasi Resonant ConverterQTNR Quality Temporal Noise ReductionQVCP Quality Video Composition ProcessorRAM Random Access MemoryRGB Red, Green, and Blue. The primary
color signals for TV. By mixing levels of R, G, and B, all colors (Y/C) are reproduced.
RC Remote ControlRC5 / RC6 Signal protocol from the remote
control receiver RESET RESET signalROM Read Only MemoryRSDS Reduced Swing Differential Signalling
data interfaceR-TXT Red TeleteXTSAM Service Alignment ModeS/C Short CircuitSCART Syndicat des Constructeurs
d'Appareils Radiorécepteurs et Téléviseurs
SCL Serial Clock I2CSCL-F CLock Signal on Fast I2C busSD Standard DefinitionSDA Serial Data I2CSDA-F DAta Signal on Fast I2C busSDI Serial Digital Interface, see “ITU-656”SDRAM Synchronous DRAMSECAM SEequence Couleur Avec Mémoire.
Color system mainly used in France and East Europe. Color carriers= 4.406250 MHz and 4.250000 MHz
SIF Sound Intermediate FrequencySMPS Switched Mode Power SupplySoC System on ChipSOG Sync On GreenSOPS Self Oscillating Power SupplySPI Serial Peripheral Interface bus; a 4-
wire synchronous serial data link standard
S/PDIF Sony Philips Digital InterFaceSRAM Static RAMSRP Service Reference ProtocolSSB Small Signal BoardSTBY STand-BYSVGA 800 × 600 (4:3)SVHS Super Video Home SystemSW SoftwareSWAN Spatial temporal Weighted Averaging
Noise reductionSXGA 1280 × 1024TFT Thin Film TransistorTHD Total Harmonic DistortionTMDS Transmission Minimized Differential
SignallingTXT TeleteXTTXT-DW Dual Window with TeleteXTUI User InterfaceuP MicroprocessorUXGA 1600 × 1200 (4:3)V V-sync to the module VESA Video Electronics Standards
Y Luminance signalY/C Luminance (Y) and Chrominance (C)
signalYPbPr Component video. Luminance and
scaled color difference signals (B-Y and R-Y)
YUV Component video
Mechanical Instructions EN 9TPM3.1E LA 4.
2009-Jun-26
4. Mechanical Instructions
Index of this chapter:4.1 Cable Dressing4.2 Service Positions4.3 Assy/Panel Removal TPM3.1E LA Styling4.4 Set Re-assembly.
Notes:• Figures below can deviate slightly from the actual situation,
due to the different set executions.
4.1 Cable Dressing
Figure 4-1 Cable dressing 32" set with AUO panel
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Figure 4-2 Cable dressing 32" set with LGD panel
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Figure 4-3 Cable dressing 42" set
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4.2 Service Positions
For easy servicing of this set, there are a few possibilities created:• The buffers from the packaging.• Foam bars (created for Service).
4.2.1 Foam Bars
Figure 4-4 Foam bars
The foam bars (order code 3122 785 90580 for two pieces) can be used for all types and sizes of Flat TVs. See Figure 4-4 for details. Sets with a display of 42" and larger, require four foam bars [1]. Ensure that the foam bars are always supporting the cabinet and never only the display.Caution: Failure to follow these guidelines can seriously damage the display!By laying the TV face down on the (ESD protective) foam bars, a stable situation is created to perform measurements and alignments. By placing a mirror under the TV, the screen can be monitored.
4.3 Assy/Panel Removal TPM3.1E LA Styling
4.3.1 Rear Cover
Warning: Disconnect the mains power cord before removing the rear cover.1. Remove the fixation screws that secure the rear cover.2. Lift the rear cover from the TV. Make sure that wires and
flat foils are not damaged while lifting the rear cover from the set.
4.3.2 Small Signal Board (SSB)
Caution: it is mandatory to remount all different screws at their original position during re-assembly. Failure to do so may result in damaging the SSB.
1. Unplug LVDS connector.Caution: be careful, as these are very fragile connectors!
2. Unplug all other connectors.3. Remove all fixation the screws.4. The SSB can now be taken out of the set.
4.3.3 Power Board
1. Unplug the power board connectors.2. Remove the screws.3. Lift the unit and take it out of the set.When defective, replace the whole unit.
4.3.4 Speakers
1. Unplug the speaker cable connector from the SSB.2. Take the speakers out together with their casing. When defective, replace the whole unit.
4.3.5 Key Board
1. Release the clip at the top and take whole the unit out.2. Unplug the connector.3. Remove the fixation screws and take the panel from the
unit.When defective, replace the whole unit.
4.3.6 IR Board
1. Remove the speaker that covers the IR board.2. Unplug the IR board connector.3. Remove the screw closest to the connector.4. Lift the IR board and take it out of the set.When defective, replace the whole board.
4.3.7 Display Panel
1. Unplug the backlight and LVDS connectors.2. Take the speakers out of their fixation position.3. Release the key board unit from the bezel.4. Release the IR board connector.5. Remove the four fixation screws that fix the subframe to the
front bezel.6. Lift the complete subframe with boards and speakers from
the front bezel.7. Remove the four fixation screws from the side of the
subframe that fix the LCD panel to the subframe.8. Lift the complete subframe from the LCD panel.When defective, replace the whole unit.
4.4 Set Re-assembly
To re-assemble the whole set, execute all processes in reverse order.
Notes:• While re-assembling, make sure that all cables are placed
and connected in their original position. See Figure 4-1.• Pay special attention not to damage the EMC foams on the
SSB shields. Ensure that EMC foams are mounted correctly.
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Service Modes, Error Codes, and Fault Finding EN 13TPM3.1E LA 5.
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5. Service Modes, Error Codes, and Fault Finding
Index of this chapter:5.1 Service Modes5.2 Software Upgrading5.3 Error Codes5.4 Fault Finding and Repair Tips
5.1 Service Modes
The Customer Service Mode (CSM) is used for communication between the call centre and the customer, while the Factory Mode offers several features for the service technician.
This chassis also offers the option of using ComPair, a hardware interface between a computer and the TV chassis. It offers the abilities of structured troubleshooting, error code reading, and software version read-out for all chassis.
5.1.1 Customer Service Mode (CSM)
Purpose The Customer Service Mode shows error codes and information on the TV’s operation settings.The call centre can instruct the customer (by telephone) to enter CSM in order to identify the status of the set.This helps the call centre to diagnose problems and failures in the TV set before making a service call.The CSM is a read-only mode; therefore, modifications are not possible in this mode.
How to Activate CSMKey in the code “123654” via the standard RC transmitter. Note: Activation of the CSM is only possible if there is no (user) menu on the screen!
Figure 5-1 CSM Menu
How to NavigateBy means of the “CURSOR-DOWN/UP” knob (or the scroll wheel) on the RC-transmitter, can be navigated through the menus.
Contents of CSM
General• Model. Philips model type• Production serial number
Philips serial number• Software version
Format:TPAA.AA V2.XX Y ZTPAA.AA is the chassis nameV2.XX is the revisionY is the display code (1 digit).Z is the panel revision code (1 digit).
• CodesShow the latest 5 error codes (layer 2)status:000 = No problem, 011 = I2C bus error, 012 = tuner error
• SSBPhilips 12NC of SSB (small signal board)
• DisplayPhilips 12NC of display (LCD panel)
• PSUPhilips 12NC of PSU (Power Supply Unit)
• NVM versionRevision (4 letters)
• PQ VersionRevision (4 letter)
• HDCP keyHDCP status (Valid, Invalid)
• Signal quality/presentDTV shows (Digital percentage)ATV shows (analog Yes/No)
• Audio systemMono, Stereo, Dual
• Video formatPAL, SECAM, NTSC
• Standby μP SW versionRevision (4 letters)
How to Exit CSMPress “INFO” on the RC-transmitter.
5.1.2 Factory mode
How to enterTo enter the factory mode, use the following method:• Press the following key sequence on the remote control
transmitter: “062596”directly followed by the “INFO” button.After entering the factory mode, the following screen is visible on the top and right of the panel.
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Figure 5-2 Factory Mode Menu
How to NavigateWith the up/dowm cursor keys can be navigated arround the items, with the Left/Right cursor the values can be changed.
How to EXITChoose "EXIT", then press"OK"button.
5.2 Software Upgrading
5.2.1 ComPair
IntroductionComPair (Computer Aided Repair) is a Service tool for Philips Consumer Electronics products. and offers the following:1. ComPair helps to quickly get an understanding on how to
repair the chassis in a short and effective way.2. ComPair allows very detailed diagnostics and is therefore
capable of accurately indicating problem areas. No knowledge on I2C or UART commands is necessary, because ComPair takes care of this.
3. ComPair speeds up the repair time since it can automatically communicate with the chassis (when the uP is working) and all repair information is directly available.
4. ComPair features TV software up possibilities.
SpecificationsComPair consists of a Windows based fault finding program and an interface box between PC and the (defective) product. The ComPair II interface box is connected to the PC via an USB cable. For the TV chassis, the ComPair interface box and the TV communicate via a bi-directional cable via the service connector(s).The ComPair fault finding program is able to determine the problem of the defective television, by a combination of
automatic diagnostics and an interactive question/answer procedure.
How to ConnectThis is described in the chassis fault finding database in ComPair.
Figure 5-3 ComPair II interface connection
Caution: It is compulsory to connect the TV to the PC as shown in the picture above (with the ComPair interface in between), as the ComPair interface acts as a level shifter. If one connects the TV directly to the PC (via UART), ICs will be blown!
How to OrderComPair II order codes:• ComPair II interface: 3122 785 91020.• Programming software can be downloaded from the Philips
Service portal. • ComPair UART interface cable for TPS2.2x xx.
(using JST PHR-3, 2 mm pitch connector): 3122 785 90630.
Note: While having problems, contact the local support desk.
5.3 Error Codes
The error code buffer contains all errors detected since the last time the buffer was erased. The buffer is written from left to right. When an error occurs that is not yet in the error code buffer, it is displayed at the left side and all other errors shift one position to the right.
5.4 Fault Finding and Repair Tips
5.4.1 Exit “SAM”
Choose "EXIT",then press"OK"button. Turn off the TV and then turn on the TV.
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TOUART SERVICECONNECTOR
TOUART SERVICECONNECTOR
TOI2C SERVICECONNECTOR
TO TV
PC
HDMII2C only
Optional power5V DC
ComPair II Developed by Philips Brugge
RC outRC in
OptionalSwitch
Power ModeLink/Activity I2C
ComPair IIMulti
function
RS232 /UART
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5.4.2 Speakers
Make sure that the volume is set to minimum during disconnecting the speakers in the ON-state of the TV. The audio amplifier can be damaged by disconnecting the speakers during ON-state of the set!
5.4.3 Tuner
Attention: In case the tuner is replaced, always check the tuner options.
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6. Alignments
Index of this chapter:6.1 General Alignment Conditions6.2 TV Mode display adjust6.3 PC mode Display Adjustment6.4 Serial Number Definition
Note: The Service Mode are described in chapter 5. Menu navigation is done with the CURSOR UP, DOWN, LEFT or RIGHT keys of the remote control transmitter.
6.1 General Alignment Conditions
Perform all electrical adjustments under the following conditions:• Power supply voltage (depends on region):
– 195 V to 264 VAC, 50/60 ±3 Hz.• Connect the set to the mains via an isolation transformer
with low internal resistance.• Allow the set to warm up for approximately 15 minutes.• Measure voltages and waveforms in relation to correct
ground (e.g. measure audio signals in relation to AUDIO_GND).Caution: It is not allowed to use heatsinks as ground.
• Test probe: Ri > 10 MΩ, Ci < 20 pF.• Use an isolated trimmer/screwdriver to perform
alignments.
6.2 TV Mode display adjust
6.2.1 White balance adjustment
General set-up:• Equipment Requirements: Colour analyser.• Input requirements:
Input Signal Type:– RF signal– Set to PAL B/G system, frequency is decided in factory– Pattern is white of 100%
• Input Signal Strength: 10 mV (80 dBμV) terminal voltage.• Input Injection Point: TV Tuner input
Colour Temp Alignment Apply full white pattern, and smart picture setting to be standard (Brightness 50, Contrast 50, and Colour 50). Adjusting SCALER GAIN R G B to reach W/D and luminance in factory mode as below.Adjust the colour temperature in the factory mode OSD by adjusting RGB Gain from 127. The CIE1931 chromaticity (X, Y) co-ordinates shall be:
Table 6-1 Reading with Minolta CA-210
If you do not have a colour analyser, you can use the default values. This is the next best solution. The default values are average values coming from production (statistics).• Select a COLOUR TEMPERATURE (e.g. COOL,
NORMAL, or WARM).• Set the RED, GREEN and BLUE default values according
to the values in Table 6-2.• When finished return to the SAM root menu and press
STANDBY on the RC to store the aligned values to the NVM.
Table 6-2 Tint settings
Luminance: – >360 cd/m2 for AUO T315XW02– >400 cd/m2 for LGD LC320WXEIn the centre of the screen when Smart mode at “Vivid” or set brightness to 100.
Note: These group settings about colour temp are also applied automatically into HDMI1/HDMI2/Side HDMI/CVI1/CVI2/SIDE AV/VGA. That means TV/HDMI/CVI/PC are used the same setting.
6.3 PC mode Display Adjustment
Auto colour adjustment Set Brightness 100 and Contrast 50 and apply 1024 × 768 at 60 Hz mode with 50 Black and 50 White pattern at the factory mode.Activate AUTO-COLOR function for auto ADC offset and gain setup.
Figure 6-1 50-Black 50-White
Colour temperature alignment is automatically set during TV alignment.Apply full white pattern, check picture must satisfy following table.
Table 6-3 Reading with Minolta CA-210
If you do not have a colour analyser, you can use the default values. This is the next best solution. The default values are average values coming from production (statistics).• Select NORMAL COLOUR TEMPERATURE.• Set the RED, GREEN and BLUE default values according
to the values in the “Tint settings” table.• When finished return to the SAM root menu and press
STANDBY on the RC to store the aligned values to the NVM.
Table 6-4 Tint settings
Colour Temp x y
Normal 0.289 ± 0.004 0.291 ± 0.004
Warm 0.314 ± 0.004 0.319 ± 0.004
Cool 0.278 ± 0.004 0.278 ± 0.004
Colour Temp R G B
Normal 85 74 85
Warm 84 63 49
Cool 75 63 85
Colour Temp x y
Normal 0.289 ± 0.015 0.291 ± 0.015
Colour Temp R G B
Normal 85 74 85
18400_203_090301.eps090617
Alignments EN 17TPM3.1E LA 6.
2009-Jun-26
6.3.1 Comp video Mode display adjust
Auto Colour Adjustment General set-up:Equipment: Quantum Data Pattern Generator 802G or 802R or 882.Apply 720p/50 Hz, and the pattern TVBAR100 as shown in Figure 6-2.
Figure 6-2 TVBAR100 pattern
Initial Set-up: Set Smart picture as “Personal” (Brightness to 50, Contrast to 50 and Colour to 50). Access to factory OSD first, then to enable AUTO-COLOR to get HD ADC OFFSET and HD ADC GAIN. Check if 32 gray scales can be distinguished.
Colour temperature alignment is automatically done during TV alignment.
6.4 Serial Number Definition
BOM Code:
Table 6-5 BOM Code
Panel Supplier Code
AU 1
CPT 2
LPL(LG) 3
QDI 4
CMO 5
HSD 6
SVA 7
18290_200_090330.eps090416
Circuit DescriptionsEN 18 TPM3.1E LA7.
2009-Jun-26
7. Circuit Descriptions
Index of this chapter:7.1 Introduction7.2 Block Diagram7.3 MT8222TMMU
Notes: • Only new circuits (circuits that are not published recently)
are described. • Figures can deviate slightly from the actual situation, due
to different set executions.• For a good understanding of the following circuit
descriptions, please use the wiring, block (chapter 9) and circuit diagrams (chapter 10). Where necessary, you will find a separate drawing for clarification.
7.1 Introduction
This platform LCD-TV uses two main ICs: MT8222TMMU (One Chip LCD-TV Controller) and WT6703F (Stand-by MCU). The MediaTek MT8222TMMU is an ultra highly integrated single chip for flat panel TV supporting multimedia video/audio input and output format up to full HDTV. It includes advanced 3D comb filter TV decoder to retrieve the best image from popular composite signals and embedded HDTV/VGA decoders for the high bandwidth input signals perfectly reproducing.The new 4th generation advanced motion adaptive and motion estimation de-interlace converts accordingly the interlace video into progressive one with overlay of a 2D graphic processor. Independent two flexible scalars provide wide adoption to various LCD panels for two of different video sources at the same time. On-chip audio processor decodes analog signals from tuner with lip sync control, delivering high quality post-processed sound effect to customers. The WT6703F is mainly for TV stand-by remaining function during off/stand-by mode. When TV set enters to off/stand-by mode, MT8222 CLD will be totally shutdown and remain only WT6703F to meet the lowest power consumption.The WT6703F is a micro controller for system power manager with Turbo 8051 compatible (3T) CPU, flash memory, SRDAM, two pulse width modulators, DPMS detector, double timers and UART, three slave I2C interface, a 4 channel 8-bit A/D converter, real time clock, watch-dog timer, embedded ISP, power down mode and embedded ICE mode.
7.2 Block Diagram
7.2.1 Features
See Block diagram Functional diagram for details.The tuner supports NTSC\PAL\SECAM RF signals. For TV signal, MT8222TMMU with single high-quality 4th generation TV decoder Automatic TV standard detection supporting NTSC, NTSC-4.43, PAL (B, G, D, H, M, N, I, Nc), PAL (Nc), PAL, SECAM New 4th generation NTSC/PAL/PAL-M/PAL-N Motion Adaptive 3D comb filter Embedded VBI decoder for Closed-Caption/XDS/ Teletext/ WSS/VPS Supporting macrovision detection.The platform supports different I/O sources: • CVI supports YPbPr component input, it can support SD/
HD format • SIDE-AV supports CVBS, S-Video signal shares with same
audio.• HDMI supports up to HDMI 1.3a with CEC & HDCP
function, audio included and also supports PC DVI signal with HDCP function, the audio shares with PC audio connector via PC mini-jack
• PC supports analog PC input via 15 pin D-sub input• Analog audio out supports via RCA jack Each video/audio signal of all sources will directly deliver to MT8222TMMU for video/audio further digital processing.
Pre-Audio out signal is sent through the DAC out and is amplified to main speaker by audio amplifier MAX9728AETC + TPA3123D2 and is simultaneously amplified to head phone by audio amplifier MAX9728AETC.
Circuit Descriptions EN 19TPM3.1E LA 7.
2009-Jun-26
7.2.2 32" & 42" SSB Cell Layout
Figure 7-1 32" & 42" SSB layout
7.3 MT8222TMMU
7.3.1 Function Description
Analog front end• set of high resolution ADC with corresponding PGAs
adopting to 0.5 V to 2 V input dedicated for TV/AV/SV input signals.
• 3 high speed ADCs dedicated for VGA/HDTV input signals up to 160 MHz.
• All 8-bit programmable gain pre-amplifiers.• Embedded Schmitt trigger and de-glitch circuits on Hsync/
Vsync/SOG/SOY inputs.
Video InputEmbedded input multiplexers without external switch including.
• 8 for TV/AV/S-video input pins available for any possible combination.
• 3 sets for VGA/Component/Scart/D-connector with differential input pairs.
• 3 sets of HDMI/DVI input port with internal multiplexers.• Input sources can be flexibly routed to Main/PIP internally.
Sync Processor• Two enhance sync processors for all timing detection
supporting Macrovision detection.• Enhanced measuring mechanism for VGA auto
adjustment.
DecoderTVD• Single high-quality 4th generation TV decoder.
18400_206_090301.eps090617
TUNER
DDR
CLASS D
FFC
Scaler
VGA
HDMI
HDMI
USB
Scart
Component
AV Input
Circuit DescriptionsEN 20 TPM3.1E LA7.
2009-Jun-26
• Automatic TV standard detection supporting NTSC, NTSC-4.43, PAL (B, G, D, H, M, N, I, Nc), PAL (Nc), PAL, SECAM.
• New 4th generation NTSC/PAL/PAL-M/PAL-N Motion Adaptive 3D comb filter.
• Embedded VBI decoder for Closed-Caption/XDS/Teletext/ WSS/VPS.
input.• Smart detection on Scart function for European region.• Smart detection on D-connector for Japan region.• Supporting SCART RGB inputs mixed with composite
signal by adjustable horizontal delay.
VGA• Supporting various VGA input timings up to UXGA
Contrast/Brightness/Sharpness Management• Sharpness and DLTI/DCTI• Brightness and contrast adjustment• Black level extender to get more detail at dark scene• White peak level limiter• Adaptive Luma/Chroma management.
with motion estimation & motion compensation de-interlacing.
• Automatic detect film or video source.• 3 : 2/2 : 2 pull down source detection.
Scaling• 4th generation high resolution arbitrary ratio vertical/
horizontal scaling of video, from 1/32× to 32×.
• Advanced linear and non-linear Panorama scaling.• Programmable Zoom viewer.• Picture-in-Picture (PIP).• Picture-Out-Picture (POP).
Display• Advanced dithering processing for LCD display with 8/10
bit output.• Gamma correction• Supporting alpha blending for Video and OSD planes.• Frame rate conversion• Gamma/anti-Gamma correction to optimise the display
device performance
Seamless performance comparing demonstration function• Support Left/Right video processing comparing function
without additional resources (DRAM) for customers demonstration
• All the video functions (De-interlace/3D comb/NR/Flesh tone/CTI) can be included
Video Output• Programmable output timing up to 1920 × 1080 @ 60 Hz
panel support.• Dual-channel 8/10-bit LVDS, single channel 8/10-bit LVDS• One CVBS output with CVBS / S-video mixed input• Spread spectrum function to eliminate display clock EMI
issue on board
Audio Features• Supporting BTSC/EIAJ/A2/NICAM decode• Stereo demodulation, SAP demodulation• Mode selection (Main/SAP/Stereo)• Equalizer• Sub-woofer/Bass enhancement• MTK proprietary 3D surround processing (Virtual surround)• Audio and video lip synchronization• Supporting Reverberation
Audio Input/Output• Decode audio AF from Tuner• 2 channels audio L/R digital line in.• Supports 1-channel (1 R/L pairs) analog audio input.• Embedded internal 3-ch (L/R) audio DAC & could bundle
with 8292 (MTK audio OP & MUX).• Supporting 1 tuner audio decoder and 1 digital input and
both output for SCART1/2 output application• Support SPDIF in/output
2D-Graphic/OSD processor• Embedded one bitmap OSD plane to support 4-/8-bpp
index colour mode, and 16-/32-bpp direct colour mode with horizontal/vertical scaling function
• Another character based OSD plane to support 1-/2-/4-/8-bpp index colour mode for low DRAM usage setup menu and Teletext / Close-caption display
• Supporting alpha blending among these two planes and video
Host Micro controller• RISC microprocessor & 8032 dual core CPU inside.• Supporting serial type flash interface• Supporting 5/3.3-Volt. FLASH interface• IR control serial input
Circuit Descriptions EN 21TPM3.1E LA 7.
2009-Jun-26
• Supporting two RS232 interfaces for external source communication (Including one RS232 port speeding up to 3 Mbps)
• Supporting up to 4 PWM outputs• Programmable GPIO setting for complex external device
control
Multi-Media Engine• Supports HD JPEG decode• Supports SD MPEG-1/2/4 decode• Support RM decode (option)
DRAM Controller• Supporting up to 32M-bytes DDRI/SDR DRAM• Supporting 16 bits DDRI/SDR bus interfaces• Build in a DRAM interface programmable clock to optimise
the DRAM performance• Programmable DRAM access cycle and refresh cycle
timings• Supporting 2.5/3.3 Volt DDRI/SDR Interface
Flash Usage• Flash is used to store FW code, fonts, bitmaps, big tables
for VGA, Video, Gamma.• For single country, we need around 20KB to store font
data.• For more bitmaps, we need more flash space to store
them.
USB Host• Embedded host controller• Compliant with USB specification Rev. 2.0 at high-speed
and full-speed data transfer rate• Complies with USB Storage Class specification Rev. 1.0• Support independent USB 2 channel & copy function
This section shows the internal block diagrams and pin configurations of ICs that are drawn as “black boxes” in the electrical diagrams (with the exception of “memory” and “logic” ICs).
8.1 MT8222TMMU/B (IC U4201)
Figure 8-1 Internal block diagram and pin configuration
18400_300_090301.eps090619
Block Diagram
Pin Configuration
IC Data Sheets EN 23TPM3.1E LA 8.
2009-Jun-26
8.2 WT6703F (IC U4101)
Figure 8-2 Internal block diagram and pin configuration
18400_301_090301.eps090619
Block Diagram
Pin Configuration
IC Data SheetsEN 24 TPM3.1E LA8.
2009-Jun-26
8.3 MX25L6405DMI (IC U4105)
Figure 8-3 Pin configuration
18400_302_090301.eps090619
Block Diagram
Pin Configuration
IC Data Sheets EN 25TPM3.1E LA 8.
2009-Jun-26
8.4 EM6AA160TS (IC U5101)
Figure 8-4 Internal block diagram
CK
CKE
CSRASCASWE
DLLCLOCKBUFFER
COMMANDDECODER
COLUMNCOUNTER
CONTROLSIGNAL
GENERATOR
ADDRESSBUFFER
REFRESHCOUNTER
4M x 16CELL ARRAY
(BANK #0)Row
Dec
oder
4M x 16CELL ARRAY
(BANK #1)Row
Dec
oder
4M x 16CELL ARRAY
(BANK #2)Row
Dec
oder
4M x 16CELL ARRAY
(BANK #3)Row
D
ecod
er
Column Decoder
Column Decoder
Column Decoder
Column Decoder
MODEREGISTER
A10/AP
A9A11A12BA0BA1
~
A0
CK
DATASTROBEBUFFER
LDQSUDQS DQ
Buffer
LDMUDM
DQ15
DQ0~
18400_303_090301.eps090619
Block Diagram
IC Data SheetsEN 26 TPM3.1E LA8.
2009-Jun-26
8.5 EM6AA160TS (IC U5101)
Figure 8-5 Pin configuration
VSSQ
1 66 SSVDDV
2 65 51QD0QD
3 64 QSSVQDDV
4 63 41QD1QD
5 62 31QD2QD
6 61VSSQ VDDQ
7 60 21QD3QD
8 59 11QD4QD
9 58 QSSVQDDV
10 57 01QD5QD
11 56 9QD6QD
12 55 QDDVQSSV
13 54 8QD7QD
14 53 CNCN
15 52VDDQ
16 51 SQDUSQDL
18 49 FERVDDV
19 48 SSVCN
20 47 MDUMDL
22 45 KCSAC
23 44 EKCSAR
24 43 CNSC
25 42 21ACN
26 41 11A0AB
27 40 9A1AB
28 39 8APA/01A
29 38A0 A7
17 50 CNCN
21 46 KCEW
31 36 5A2A
32 35 4A3A
33 34 SSVDDV
30 37 6A1A
Pin Configuration
18400_304_090301.eps090619
IC Data Sheets EN 27TPM3.1E LA 8.
2009-Jun-26
8.6 MAX9728AETC (IC U1501, U1502, U6202)
Figure 8-6 Internal block diagram and pin configuration
CHARGEPUMP
UVLO/SHUTDOWNCONTROL
CLICK-AND-POPSUPPRESSION
C1N
C1P
PVSS SVSS PGND SGND INR
VDD SHDN
ONOFF
SVSS
VDD
SGND
INL
RF*30k?
RIN*20k?
RIN*20k?
OUTR
LEFTAUDIOINPUT
RIGHTAUDIOINPUT
HEADPHONEJACK
5(8)
12(2)
1(3)
2(4)
3(5)
4(7)
9(12)
11(1)
6(9)
10(14)
7(10)
C11µF
C21µF
4.5V TO 5.5V
C31µF
CIN0.47µF
SVSS
VDD
OUTL
CIN0.47µF
8(11)
RF*30k?
MAX9728A
Block Diagram
Pin Configuration
18400_305_090301.eps090619
TOP VIEW
12
11
10
4
5
6
1 2 3
9 8 7
MAX9728AMAX9728B
TQFN
C1P
PG
ND
C1N
PVSS
SHDN
INL
SG
ND
INR
SV S
S
OUTR
OUTL
+VDD
IC Data SheetsEN 28 TPM3.1E LA8.
2009-Jun-26
8.7 TPA3123D2PWPR (IC U6301)
Figure 8-7 Internal block diagram and pin configuration
EN 42TPM3.1E LA 10.Circuit Diagrams and PWB Layouts
2009-Jun-26
Power Board Inverter, 32PFL54xx LGD panel1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
0 1
0 1
1 1
1 1
A A
B B
C C
D D
E E
F F
G G
H H
D L O C
InverterD L O C T O H
!
!
!
!
!
!
D L O C T O H
T O H
8 A 3 0 8 N C 8 D 2 0 8 N C 5 C 2 0 8 C 4 B 1 0 8 C 5 C 4 0 8 C 4 B 3 0 8 C 7 B 6 0 8 C 8 B 5 0 8 C 7 D 8 0 8 C 7 B 7 0 8 C 8 D 0 1 8 C 7 D 9 0 8 C 2 B 2 1 8 C 2 B 1 1 8 C 2 C 4 1 8 C 2 B 3 1 8 C 2 C 6 1 8 C 2 C 5 1 8 C 6 E 1 2 8 C 4 D 9 1 8 C 2 C 3 2 8 C 5 E 2 2 8 C 9 D 5 2 8 C 5 F 4 2 8 C 8 B 7 2 8 C 8 B 6 2 8 C 8 B 1 0 8 D 7 D 8 2 8 C 9 D 3 0 8 D 8 D 2 0 8 D 3 B 1 0 8 C I 4 A 1 0 8 B F 5 D 4 0 8 C I 5 D 3 0 8 C I 5 F 6 0 8 C I 5 E 5 0 8 C I 5 B 2 0 8 Q 5 B 1 0 8 Q 5 E 7 0 8 Q 5 C 6 0 8 Q 5 B 1 0 8 R 5 F 8 0 8 Q 5 C 4 0 8 R 5 C 2 0 8 R 4 D 7 0 8 R 2 C 6 0 8 R 4 D 9 0 8 R 5 D 8 0 8 R 5 D 1 1 8 R 2 C 0 1 8 R 5 D 3 1 8 R 5 D 2 1 8 R 4 F 5 1 8 R 5 E 4 1 8 R 5 F 7 1 8 R 4 F 6 1 8 R 6 F 9 1 8 R 6 F 8 1 8 R 9 D 1 2 8 R 6 E 0 2 8 R 6 C 3 2 8 R 7 C 2 2 8 R 6 C 5 2 8 R 4 E 4 2 8 R 4 D 7 2 8 R 6 E 6 2 8 R 6 B 3 0 8 T 7 C 1 0 8 T
6 E 2 0 8 D Z 5 D 1 0 8 D Z
t r o h s V
B F I
d d V
F N
2 2 8 C V 0 5 N 0 0 1
6 0 8 C
V 0 5 2 N 1
3 0 8 C V 0 5 4 F U 1
3 0 8 N C N N O C
1 2
7 2 8 R M H O 0
9 1 8 R W 4 / 1 % 5 - + M H O K 0 9 3
8 0 8 Q 1 3 4 L T
2 0 8 R 7 R 4
5 1 8 C V 0 5 P 7 4
8 2 8 C V 0 5 P 0 2 2
8 0 8 C V 0 5 2 N 1
3 0 8 D 9 9 V A B
3
1
2
0 2 8 R % 1 W 8 / 1 K 0 9 3 1 2 8 C
V 0 5 N 0 0 1
4 1 8 R % 1 W 8 / 1 7 K 2
6 1 8 R K 7 4
9 1 8 C V 0 5 N 0 1
1 0 8 Q P F Z 0 5 K N 4 1 P T S
2
1
3
2 2 8 R % 1 W 8 / 1 K 0 1
2 0 8 C V 0 5 4 F N 0 7 4
9 0 8 C V K 6 / F p 5 1
6 0 8 C I 3 0 1 1 T E C T
1 2
4 3
6 0 8 Q G L C 8 4 8 C B
2 1 8 R % 5 W 6 / 1 R 0 7 4
8 0 8 R K 8 6
1 1 8 C V 0 5 N 5 1
3 2 8 C P 0 7 4
0 1 8 C V 0 5 P 0 7 4
1 0 8 C V 0 5 N 0 0 1
7 1 8 R % 1 W 8 / 1 7 K 2
2 0 8 Q P F Z 0 5 K N 4 1 P T S
2
1
3
5 2 8 R R 3 3
4 0 8 C V 5 2 2 U 2
5 0 8 C V 0 5 P 0 7 4
1 0 8 T
8 . 9 U U - F R T
1 4
2 3
7 0 8 Q 4 0 9 3 S B M P
1
3 2
4 0 8 C I 3 0 1 1 T E C T
1 2
4 3
3 1 8 R % 5 W 6 / 1 R 0 7 4
3 1 8 C 7 N 2
4 2 8 R % 5 W 6 / 1 K 0 1
2 0 8 D Z B 6 . 3 Z L R
1 2
1 2 8 R K 8 6
7 0 8 R % 1 W 8 / 1 K 0 0 1
3 2 8 R R 7 2
5 1 8 R % 1 W 8 / 1 7 K 2
5 0 8 C I 3 0 1 1 T E C T
1 2
4 3
7 2 8 C V 0 5 7 N 4
1 0 8 D 9 9 V A B
3
1 2
8 1 8 R % 1 W 8 / 1 4 K 5 1
6 2 8 R W 8 / 1 % 5 - + K 0 1
9 0 8 R W 8 / 1 % 5 - + M H O K 9 3
1 0 8 C I
1 7 0 2 A B U
1
2
3
4
5
6
7
8
9
2 1 3 1
4 1
5 1
6 1
7 1
9 1
0 2
8 1
0 1
1 1
1 2
2 2
4 2
3 2
B F I
B F I C
B F V
B F V C
P W S C
T C
F C
F E R I
M W P C
d M W P T L U A F , N
a M W P
N E
D D V
D N G P
C N
C N
L G
D N G S
M M O C
C N
H S
H G
S F
1 0 8 B F
Jum
p w
ire
4 1 8 C V 0 5 N 0 5 1
3 0 8 T 8 2 U U - F R T
6
5
7 4
1
8 3
2
7 0 8 C V K 6 / F p 5 1
4 0 8 R % 1 W 8 / 1 R 0 7 4
4 2 8 C V 5 2 F U 1
2 1 8 C V 0 5 N 0 5 1
1 1 8 R K 0 0 1
1 0 8 R 7 R 4
3 0 8 C I 3 0 1 1 T E C T
1 2
4 3
5 2 8 C 7 N 2
6 1 8 C V 0 5 P 8 6
1 0 8 D Z B 3 1 Z L R
1 2
6 2 8 C V 0 5 P 0 2 2
2 0 8 D 9 9 V A B
3
1 2
0 1 8 R
M H O 0
2 0 8 N C N N O C
1 2
K 3 3 6 0 8 R
V 2 1
V 2 1
A N E
M I D
S - d d V
+ B
A01 A01
18400_502_090301.eps090619
Circuit Diagrams and PWB Layouts EN 43TPM3.1E LA 10.
Circuit Diagrams and PWB Layouts EN 45TPM3.1E LA 10.
2009-Jun-26
Power Board Adapter, 32PFL56xx1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
0 1
0 1
1 1
1 1
A A
B B
C C
D D
E E
F F
G G
H H
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
! !
D L O C T O H
D L O C T O H
V 0 5 2 H A 0 . 5 T E P Y T C E I
1 G 1 0 9 N C 1 B 1 0 9 D B 1 F 4 0 9 N C 8 G 2 0 9 N C
1 D 2 0 9 C 1 D 1 0 9 C 8 B 4 0 9 C 1 E 3 0 9 C 1 F 6 0 9 C 9 B 5 0 9 C 1 E 8 0 9 C 6 A 7 0 9 C 3 G 0 1 9 C 2 A 9 0 9 C 6 F 2 1 9 C 7 E 1 1 9 C 6 F 4 1 9 C 6 F 3 1 9 C 5 D 6 1 9 C 6 G 5 1 9 C 8 C 8 1 9 C 6 B 7 1 9 C 7 B 0 2 9 C 5 C 9 1 9 C 6 C 2 2 9 C 5 C 1 2 9 C 8 A 4 2 9 C 5 A 3 2 9 C 9 B 6 2 9 C 9 A 5 2 9 C 9 B 8 2 9 C 0 1 B 7 2 9 C 0 1 B 0 3 9 C 9 B 9 2 9 C
8 E 2 3 9 C 9 D 1 3 9 C 9 E 4 3 9 C 8 E 3 3 9 C 0 1 E 6 3 9 C 8 F 5 3 9 C
8 B 8 3 9 C 4 G 7 3 9 C 8 G 0 4 9 C 8 G 9 3 9 C 2 B 2 4 9 C 8 H 1 4 9 C 2 C 4 4 9 C 2 B 3 4 9 C 3 B 6 4 9 C 2 C 5 4 9 C 5 G 2 0 9 D 4 B 7 4 9 C 7 E 5 0 9 D 7 E 4 0 9 D 7 B 8 0 9 D 7 B 7 0 9 D 9 B 0 1 9 D 8 B 9 0 9 D 8 E 2 1 9 D 9 B 1 1 9 D 4 A 4 1 9 D 3 C 3 1 9 D 8 E 2 0 9 B F 1 A 1 0 9 B F 4 A 5 0 9 B F 1 F 3 0 9 B F 1 A 1 0 9 D B H 1 G 1 0 9 F 8 B 1 0 9 Q H 9 B 1 1 9 D H
5 F 1 0 9 C I 4 B 4 0 9 Q H 8 C 3 0 9 C I 6 B 2 0 9 C I 8 D 5 0 9 C I 9 D 4 0 9 C I 8 F 7 0 9 C I 7 F 6 0 9 C I 1 E 1 0 9 L 2 B 9 0 9 C I 9 B 3 0 9 L 1 D 2 0 9 L 8 E 5 0 9 L 9 B 4 0 9 L 8 B 1 0 9 Q 3 A 6 0 9 L 5 D 3 0 9 Q 6 G 2 0 9 Q 6 B 5 0 9 Q 4 B 4 0 9 Q 9 F 8 0 9 Q 9 E 7 0 9 Q 5 C 0 1 9 Q 7 G 9 0 9 Q 1 F 1 0 9 V R 5 A 1 1 9 Q 1 E 1 0 9 R 1 C 5 0 9 V R
4 G 3 0 9 R 5 A 2 0 9 R 5 B 5 0 9 R 5 A 4 0 9 R 4 B 7 0 9 R 5 B 6 0 9 R 3 B 9 0 9 R 3 B 8 0 9 R 7 G 1 1 9 R 5 B 0 1 9 R 5 F 3 1 9 R 6 G 2 1 9 R 6 F 5 1 9 R 6 F 4 1 9 R 7 F 8 1 9 R 7 F 7 1 9 R 5 B 0 2 9 R 6 G 9 1 9 R 6 G 2 2 9 R 7 B 1 2 9 R 7 C 5 2 9 R 8 B 4 2 9 R 8 C 7 2 9 R 7 B 6 2 9 R 8 D 9 2 9 R 7 C 8 2 9 R 6 D 1 3 9 R 5 C 0 3 9 R 9 A 5 3 9 R 5 D 2 3 9 R 9 B 7 3 9 R 9 A 6 3 9 R
0 1 B 9 3 9 R 9 B 8 3 9 R 9 C 1 4 9 R 9 C 0 4 9 R
0 1 C 3 4 9 R 9 D 2 4 9 R 8 C 5 4 9 R 0 1 D 4 4 9 R
9 E 7 4 9 R 9 E 6 4 9 R 8 F 9 4 9 R 0 1 E 8 4 9 R
8 F 1 5 9 R 8 F 0 5 9 R 8 F 3 5 9 R 8 F 2 5 9 R 9 G 5 5 9 R 8 F 4 5 9 R 2 B 7 5 9 R 9 F 6 5 9 R 2 C 9 5 9 R 2 B 8 5 9 R 3 B 1 6 9 R 2 C 0 6 9 R 4 B 3 6 9 R 3 B 2 6 9 R 3 C 5 6 9 R 4 B 4 6 9 R 9 G 7 6 9 R 4 C 6 6 9 R 1 E 1 0 9 G S 5 C 8 6 9 R 1 D 3 0 9 G S 2 E 2 0 9 G S 1 G 1 0 9 H T 1 D 4 0 9 G S
7 E 2 0 9 T 8 A 1 0 9 T 4 G 2 0 9 D Z 5 F 1 0 9 D Z 7 E 4 0 9 D Z 6 F 3 0 9 D Z
0 1 B 6 0 9 D Z 6 B 5 0 9 D Z 8 F 8 0 9 D Z 8 D 7 0 9 D Z 6 F 0 1 9 D Z 5 D 9 0 9 D Z
7 A 1 1 9 D Z
B S V 5 +
6 5 9 R % 1 K 2 2
5 2 9 R W 8 / 1 % 5 - + M H O 0 0 1
6 2 9 R M H O 0 1
2 0 9 C I
D 1 7 2 1 P C N
1
2
3
4 5
6
7
8 P I K S
B F
S C
V R D D N G
C C V
C N
V H
8 3 9 R M H O 0 0 1
5 4 9 R M H O 0 0 1
6 0 9 C V 5 7 2 / F u 7 4 . 0
1 5 9 R M H O 0
4 1 9 C F u 1 . 0
1 0 9 V R Y F 4 C F K 1 6 5 4 1 R V T
1 3 9 C V 5 2 / F u 2 2 0 . 0
4 0 9 Q S E 0 6 N 1 1 V M F
- +
1 0 9 D B
G 8 0 6 J B K
2
1
3
4
0 4 9 C F u 1 . 0
Q90
2 B
C85
7C
ZD
908
RLZ
5.6B
1
2
1 0 9 D Z C N _ B 1 . 9 Z L R
1 2
4 2 9 R K 1
4 2 9 C V 0 0 5 / F u 2 2 0 0 . 0
4 0 9 C V 0 5 2 / F P 0 0 2 2
3 0 9 L H u 8 . 0
7 0 9 D Z B 3 1 Z L R
1 2
8 3 9 C V 0 0 1 F P 0 2 2
6 6 9 R % 1 W 1 5 1 R 0
5 0 9 D 7 0 0 1 F U
1 1 9 D 0 0 1 0 1 P S
1 2
3
+
C90
7 12
0uF
/450
V
1 0 9 G S A M 1 0 2 - 1 4 S G
7 6 9 R % 5 W 8 / 1 K 0 3 3
3 1 9 R C N _ 2 M 2
6 4 9 C
V 5 2 2 U 2
8 1 9 C V 0 5 N 1
1 4 9 R W 8 / 1 M H O K 1
2 0 9 G S A M 1 0 2 - 1 4 S G
3 0 9 Q K A 7 0 9 2 T B M M
1
2 3
5 0 9 C R E P M U J
2 2 9 R W 8 / 1 % 5 - + M H O 0
9 0 9 C I
1 6 9 6 G S
1
2
3
4
8
7
6
5
B F
p m o C
t l u M
S C
c c V
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D N G
D C Z
8 0 9 D
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0 6 0 1 P S 2 1 9 D
1
3 2
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% 5 W 8 / 1 7 R 4
9 3 9 C F u 1 . 0
0 1 9 D D 0 3 P G E
+ 3 3 9 C
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7 0 9 D
8 4 1 4 L L
0 2 9 R K 0 1
8 0 9 C V 5 7 2 / F u 7 4 . 0
5 0 9 V R
C N _ Y F 4 C F K 1 1 5 4 1 R V T
2 4 9 C F P 0 6 5
8 4 9 R
W 8 / 1 % 5 - + M H O K 1
4 5 9 R R 0
1 0 9 T
8 2 - R E R E W O P
1
6
2
3
5
9
1 1 2 1
7 8
0 1
1 6 9 R W 8 / 1 % 5 - + M H O K 7 4
6 0 9 C I 3 0 1 1 T E C T
1 2
4 3
1 0 9 B F D A E B
1 2
2 0 9 R C N _ K 0 0 1
W 2 / 1 % 5 2 M 1 1 0 9 R
9 0 9 D 7 0 0 1 F U
0 2 9 C F u 1 . 0
8 1 9 R K 0 9 3
8 0 9 Q 2 0 0 7 K R
2 5 9 R % 1 W 8 / 1 K 1 1
2 0 9 C F P 0 7 4
1 1 9 Q C N _ A 4 9 A S P M
3 5 9 R % 1 K 8 1
3 0 9 B F D A E B
1 2
3 1 9 C F p 0 0 1
3 0 9 C I G 3 0 1 1 T E C T 1
2
4 3
5 0 9 L H u 8 . 0
2 6 9 R R 7 4
8 0 9 R
% 1 W 4 / 1 M 1
1 1 9 D Z A 0 0 2 E K 6 P
1 2
3
2 0 9 T L A 9 1 0 7 H P P
2
1
4
5
7
8
0 1
9
5 4 9 C V 0 5 N 0 1
2 1 9 R C N _ % 5 W 4 / 1 K 1
6 F D 1 3
4 1 9 D
9 3 9 R R 7 4
5 6 9 R R 0 3 3
ZD
909
RLZ
20B
1 2
+ 6 2 9 C V 5 3 F u 0 0 0 1
t
1 0 9 H T 5 1 0 Y G M 6 5 R 2 3 1 K C S
1 2
1 1 9 C V 0 0 5 / 2 n 2
1 2
3 4 9 R W 8 / 1 K 0 1
3 4 9 C
V 5 2 N 0 3 3
2 0 9 N C M M 5 . 2 P 3 1 3 4 8 4 6
1 2 3 4 5 6 7 8 9
0 1 1 1 2 1 3 1
9 4 9 R R 0 0 1
4 0 9 C I 1 3 4 L T
7 2 9 R K 2 2
5 0 9 C I G 3 0 1 1 T E C T
1 2
4 3
2 3 9 C V 0 0 5 / F u 2 2 0 0 . 0
ZD
910
BZ
X79
-C9V
1
1 2
7 0 9 C I 1 3 4 L T
2 0 9 B F
8 6 7 - W 0 3 0 5 2 L - F B
1 2
1 0 9 C F P 0 7 4
7 1 9 R R 0
9 0 9 C V 0 2 5 / F u 1
1 1 9 D H
1
6 0 9 L 8 2 - R E
1 12
5 4 6 7 8
8 2 9 C V K 1 F P 0 7 2
8 2 9 R K 1
3 0 9 C e r i w p m u J
5 3 9 R M H O 0 0 1
+
C92
1 22
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0V
1 1 9 R C N _ W 2 M H O K 5 1
C92
2 1u
F/2
5V
0 4 9 R W 8 / 1 M H O K 7 . 4
0 1 9 R
C N _ M 3 . 3
9 0 9 R
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7 4 9 R K 0 3 3
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+
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3 1 9 D
8 4 1 4 L L
5 0 9 R C N _ M 3 . 3
1 3 9 R W 8 / 1 K 2 2
3 0 9 D Z B 5 1 Z L R
1 2
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9 0 9 Q C N _ 4 4 A T Z P
0 1 9 Q C N _ 4 4 A T Z P
4 0 9 N C e r i w p m u J
1 2
5 2 9 C V K 1 F P 0 7 2
7 3 9 C
C N _ V 0 5 N 2 2
1 0 9 Q H
1
2 0 9 D 1 2 V A B
+ 9 2 9 C V 6 1 F u 0 0 2 2
7 3 9 R M H O 0 0 1
6 3 9 R M H O 0 0 1
0 3 9 R R 7 . 4
8 5 9 R K 7 . 8 1
1 0 9 F V 0 5 2 A 5 E S U F
3 4
1 2
3 0 9 R W 4 / 1 % 5 - + M H O K 0 1
1 0 9 N C T E K C O S
1 2
2 3 9 R W 4 / 1 M H O K 0 1
C91
9 10
0pF
6 3 9 C F u 1 0 . 0
5 0 9 Q C 7 5 8 C B
1 0 9 C I
L T - N P 4 7 2 Y N T
1 2
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M / P B
D S S S S
4 0 9 D Z A 0 8 1 E K 6 P
1 2
7 0 9 Q 2 0 0 7 K R
7 4 9 C C N _ V K 1 / F P 0 2 2
1 0 9 Q P F Z 0 8 K N 8 P T S
+ 7 2 9 C V 5 3 F u 0 2 2
6 0 9 R C N _ M 3 . 3
+
4 3 9 C V 0 1 F u 0 7 4
9 5 9 R K 3 3
4 4 9 C V 5 2 U 1
8 6 9 R C N _ K 3 3
4 0 9 D D 0 1 P G R
9 2 9 R W 1 % 5 8 6 R 0
5 0 9 B F
3.5*
4.7
5 3 9 C F u 1 . 0
3 0 9 G S A M 1 0 2 - 1 4 S G
1 2 9 R
K 2 2
R95
7 62
0R 1
/8W
1%
0 6 9 R K 9 3
2 0 9 L A 0 . 2 H m 6
1
4
2
3
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+ 2 1 9 C V 0 5 / F u 2 2
C91
7 0.
01uF
4 0 9 R R 0
5 1 9 C F u 3 3 . 0
4 0 9 Q H
1 2
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ZD
902
BZ
X79
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1
1 2
7 0 9 R
W 4 / 1 % 1 - + M 1
0 1 9 C
V K 1 F P 0 0 5 1
4 0 9 G S A M 1 0 2 - 1 4 S G
5 5 9 R K 1
ZD
905
RLZ
18B
1
2
6 0 9 D Z A 3 1 E K 6 P
1 2
1 4 9 C F u 1 . 0
1 0 9 D B H
1
2
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9 1 9 R K 0 3 4
0 5 9 R K 3 . 3
6 4 9 R W 8 / 1 M H O K 2 . 2
5 1 9 R R 7 4
1 0 9 L A 0 . 2 H m 4 1
1
4
2
3
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+ B
V 4 2
V 2 1
B / S
B S V 5 +
V 2 1
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A N E M I D
B / S
A01 A01
18400_507_090301.eps090619
Adapter
EN 46TPM3.1E LA 10.Circuit Diagrams and PWB Layouts
2009-Jun-26
Power Board Inverter, 32PFL56xx1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
0 1
0 1
1 1
1 1
A A
B B
C C
D D
E E
F F
G G
H H
D L O C
Inverter
D L O C T O H
!
!
!
!
!
!
T O H
D L O C T O H
8 E 2 0 8 N C 8 B 3 0 8 N C
4 C 1 0 8 C 6 C 2 0 8 C 4 B 3 0 8 C 5 C 4 0 8 C 8 B 5 0 8 C 7 C 6 0 8 C 7 B 7 0 8 C 7 D 8 0 8 C 7 E 9 0 8 C 8 E 0 1 8 C 3 C 1 1 8 C 3 C 2 1 8 C 3 C 3 1 8 C 3 C 4 1 8 C 3 C 5 1 8 C 3 D 6 1 8 C 4 D 9 1 8 C 6 F 1 2 8 C 5 F 2 2 8 C 3 D 3 2 8 C 5 G 4 2 8 C 9 E 5 2 8 C 8 C 6 2 8 C 8 C 7 2 8 C 8 D 8 2 8 C 8 C 1 0 8 D 8 D 2 0 8 D 9 D 3 0 8 D 4 C 1 0 8 C I 5 E 3 0 8 C I 5 E 4 0 8 C I 5 E 5 0 8 C I 5 F 6 0 8 C I 5 B 1 0 8 Q 5 C 2 0 8 Q 5 D 6 0 8 Q 5 F 7 0 8 Q 5 G 8 0 8 Q 5 C 1 0 8 R 5 C 2 0 8 R 6 D 4 0 8 R 3 C 6 0 8 R 4 E 7 0 8 R 5 D 8 0 8 R 4 E 9 0 8 R 3 C 0 1 8 R 5 D 1 1 8 R 6 D 2 1 8 R 5 E 3 1 8 R 6 E 4 1 8 R 5 G 5 1 8 R 5 F 6 1 8 R 5 F 7 1 8 R 6 G 8 1 8 R 6 G 9 1 8 R 6 F 0 2 8 R 9 E 1 2 8 R 7 C 2 2 8 R 6 C 3 2 8 R 5 F 4 2 8 R 6 C 5 2 8 R 7 F 6 2 8 R 4 D 7 2 8 R 7 C 1 0 8 T 6 B 3 0 8 T 5 D 1 0 8 D Z 6 F 2 0 8 D Z
t r o h s V
B F I
d d V
F N
5 2 8 C 7 N 2
1 0 8 C I
1 7 0 2 A B U
1
2
3
4
5
6
7
8
9
2 1 3 1
4 1
5 1
6 1
7 1
9 1
0 2
8 1
0 1
1 1
1 2
2 2
4 2
3 2
B F I
B F I C
B F V
B F V C
P W S C
T C
F C
F E R I
M W P C
d M W P T L U A F , N
a M W P
N E
D D V
D N G P
C N
C N
L G
D N G S
M M O C
C N
H S
H G
S F
4 2 8 C V 5 2 F U 1
4 1 8 C V 0 5 N 0 5 1
6 2 8 C V 0 5 P 0 2 2
1 0 8 D 9 9 V A B
3
1 2
1 0 8 R 7 R 4
1 0 8 D Z B 3 1 Z L R
1 2
0 1 8 R
M H O 0
5 1 8 C V 0 5 P 7 4
3 0 8 C V 0 5 4 F U 1
3 0 8 C I 3 0 1 1 T E C T
1 2
4 3
7 0 8 C V K 6 / F p 5 1
7 2 8 R M H O 0
2 2 8 C V 0 5 N 0 0 1
2 0 8 N C N N O C
1 2
4 0 8 C V 5 2 2 U 2
6 1 8 C V 0 5 P 8 6
4 1 8 R % 1 W 8 / 1 7 K 2
8 0 8 C V 0 5 2 N 1
9 1 8 C V 0 5 N 0 1
3 0 8 N C N N O C
1 2
K 3 3 6 0 8 R
2 0 8 D 9 9 V A B
3
1 2
6 0 8 C
V 0 5 2 N 1
1 2 8 C V 0 5 N 0 0 1
8 2 8 C V 0 5 P 0 2 2
2 0 8 R 7 R 4
1 0 8 Q P F Z 0 5 K N 4 1 P T S
2
1
3
3 2 8 C P 0 7 4
2 2 8 R % 1 W 8 / 1 K 0 1
8 0 8 R K 8 6
2 1 8 R % 5 W 6 / 1 R 0 7 4
3 0 8 D 9 9 V A B
3
1
2
0 1 8 C V 0 5 P 0 7 4
9 1 8 R W 4 / 1 % 5 - + M H O K 0 9 3
8 0 8 Q 1 3 4 L T
6 0 8 Q G L C 8 4 8 C B
9 0 8 C V K 6 / F p 5 1
1 1 8 C V 0 5 N 5 1
7 1 8 R % 1 W 8 / 1 7 K 2
6 1 8 R K 7 4
6 0 8 C I 3 0 1 1 T E C T
1 2
4 3
3 1 8 R % 5 W 6 / 1 R 0 7 4
2 0 8 C V 0 5 4 F N 0 7 4
4 2 8 R % 5 W 6 / 1 K 0 1
2 0 8 Q P F Z 0 5 K N 4 1 P T S
2
1
3
5 0 8 C V 0 5 P 0 7 4
5 2 8 R R 3 3
1 0 8 C V 0 5 N 0 0 1
5 1 8 R % 1 W 8 / 1 7 K 2
2 0 8 D Z B 6 . 3 Z L R
1 2
4 0 8 C I 3 0 1 1 T E C T
1 2
4 3
7 2 8 C V 0 5 7 N 4
1 2 8 R K 8 6
9 0 8 R W 8 / 1 % 5 - + M H O K 9 3
7 0 8 Q 4 0 9 3 S B M P
1
3 2
6 2 8 R W 8 / 1 % 5 - + K 0 1
7 0 8 R % 1 W 8 / 1 K 0 0 1
3 1 8 C 7 N 2
3 2 8 R R 7 2
1 0 8 T
8 . 9 U U - F R T
1 4
2 3
0 2 8 R % 1 W 8 / 1 K 0 9 3
8 1 8 R % 1 W 8 / 1 4 K 5 1
4 0 8 R % 1 W 8 / 1 R 0 7 4
1 1 8 R K 0 0 1
3 0 8 T 8 2 U U - F R T
6
5
7 4
1
8 3
2
2 1 8 C V 0 5 N 0 5 1
5 0 8 C I 3 0 1 1 T E C T
1 2
4 3
V 2 1
V 2 1
M I D
A N E
S - d d V
+ B
A02 A02
18400_508_090301.eps090619
Circuit Diagrams and PWB Layouts EN 47TPM3.1E LA 10.
Circuit Diagrams and PWB Layouts EN 49TPM3.1E LA 10.
2009-Jun-26
Power Board Adapter, 42PFL56xx1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
0 1
0 1
1 1
1 1
A A
B B
C C
D D
E E
F F
G G
H H
!
!
!
!
!
!
!
!
! !
!
!
!
!
!
!
! !
!
C N
!
!
C N
!
!
!
!
C N
C N
C N
C N
C N
C N
2 E 1 0 9 N C 1 B 1 0 9 D B 1 C 1 0 9 C 0 1 F 3 0 9 N C
8 B 3 0 9 C 2 C 2 0 9 C 1 C 5 0 9 C 8 B 4 0 9 C 2 D 8 0 9 C 6 A 7 0 9 C 3 G 0 1 9 C 1 C 9 0 9 C 2 B 2 1 9 C 3 A 1 1 9 C 4 E 4 1 9 C 2 B 3 1 9 C 2 B 6 1 9 C 6 C 5 1 9 C 5 C 8 1 9 C 5 B 7 1 9 C 3 B 0 2 9 C 7 B 9 1 9 C 3 C 2 2 9 C 7 A 1 2 9 C 5 A 4 2 9 C 7 C 3 2 9 C 7 B 7 2 9 C 6 E 6 2 9 C 7 A 9 2 9 C 5 B 8 2 9 C 8 A 1 3 9 C 9 E 0 3 9 C 9 B 3 3 9 C 9 B 2 3 9 C 8 C 5 3 9 C 8 B 4 3 9 C 9 B 7 3 9 C 7 C 6 3 9 C
0 1 F 9 3 9 C 0 1 B 8 3 9 C 0 1 F 1 4 9 C 0 1 F 0 4 9 C
5 E 5 4 9 C 5 G 2 4 9 C 5 F 7 4 9 C 5 F 6 4 9 C 7 E 9 4 9 C 5 F 8 4 9 C 8 E 1 5 9 C 7 E 0 5 9 C 6 A 3 5 9 C 7 F 2 5 9 C 2 C 5 5 9 C 5 C 4 5 9 C 7 B 2 0 9 D 5 A 1 0 9 D 4 B 0 1 9 D 3 G 4 0 9 D 6 E 4 1 9 D 7 C 3 1 9 D 5 F 6 1 9 D 6 E 5 1 9 D 8 B 1 2 9 D 7 E 7 1 9 D 7 B 3 2 9 D 8 A 2 2 9 D
1 E 2 0 9 B F 1 A 1 0 9 B F 7 E 7 0 9 B F 5 A 5 0 9 B F 8 B 1 2 9 D H 1 E 1 0 9 F
7 B 3 0 9 Q H 5 B 2 0 9 Q H 3 B 2 0 9 C I 5 B 1 0 9 C I 8 D 4 0 9 C I 8 C 3 0 9 C I 6 F 7 0 9 C I 4 F 5 0 9 C I 8 D 1 2 9 C I 7 F 8 0 9 C I 1 C 2 0 9 L 1 D 1 0 9 L 9 A 1 2 9 L 8 E 7 0 9 L 1 D 3 2 9 L 9 B 2 2 9 L 7 B 3 0 9 Q 4 B 2 0 9 Q 9 E 9 0 9 Q 4 D 7 0 9 Q 6 B 1 1 9 Q 8 G 0 1 9 Q 4 C 6 1 9 Q 5 G 5 1 9 Q 4 G 8 1 9 Q 5 A 7 1 9 Q 1 B 2 0 9 V R 2 E 1 0 9 V R
6 A 4 0 9 R 2 D 1 0 9 R 4 C 6 0 9 R 5 B 5 0 9 R 4 A 8 0 9 R 5 A 7 0 9 R 6 A 0 1 9 R 3 A 9 0 9 R 5 B 2 1 9 R 2 A 1 1 9 R 2 B 4 1 9 R 2 B 3 1 9 R 4 B 6 1 9 R 6 B 5 1 9 R 3 B 8 1 9 R 4 B 7 1 9 R 4 C 0 2 9 R 4 B 9 1 9 R 5 F 2 2 9 R 7 F 1 2 9 R 7 C 4 2 9 R 7 A 3 2 9 R 4 D 6 2 9 R 4 D 5 2 9 R 7 C 8 2 9 R 7 B 7 2 9 R 7 C 0 3 9 R 4 B 9 2 9 R 3 G 4 3 9 R 6 B 1 3 9 R 9 A 6 3 9 R 9 A 5 3 9 R 9 D 8 3 9 R 8 C 7 3 9 R 9 D 1 4 9 R 8 C 9 3 9 R 9 B 3 4 9 R 9 B 2 4 9 R 9 E 5 4 9 R 8 E 4 4 9 R 9 E 7 4 9 R 4 G 6 4 9 R 9 C 9 4 9 R 5 G 8 4 9 R 5 F 1 5 9 R 3 B 0 5 9 R 7 F 3 5 9 R 8 G 2 5 9 R 7 F 5 5 9 R 9 B 4 5 9 R 7 G 7 5 9 R 7 F 6 5 9 R 6 F 9 5 9 R 9 C 8 5 9 R 8 B 1 6 9 R 8 F 0 6 9 R 8 C 3 6 9 R 6 F 2 6 9 R 4 G 6 6 9 R 4 F 5 6 9 R 4 F 8 6 9 R 3 G 7 6 9 R 6 F 0 7 9 R 5 F 9 6 9 R
2 D 2 0 9 G S 1 D 1 0 9 G S 2 C 5 0 9 G S 1 C 4 0 9 G S 4 G 3 0 9 H T 1 E 2 0 9 H T
4 A 2 0 9 T 8 A 1 0 9 T 6 E 4 0 9 T 3 A 3 0 9 T 7 F 3 0 9 D Z 3 A 5 0 9 T 5 F 7 0 9 D Z 6 B 5 0 9 D Z 3 G 9 0 9 D Z 5 F 8 0 9 D Z 9 B 4 2 9 D Z 4 F 2 1 9 D Z
8 D 5 2 9 D Z
+ B
B S V 5 +
+ 6 4 9 C V 5 3 F u 7 4
7 0 9 R W 4 / 1 % 1 - + M H O M 1
4 5 9 C V 0 5 P 0 7 4
9 5 9 R W 4 / 1 M H O 0
0 1 9 D 8 4 1 4 L L M
5 4 9 C V 0 0 5 / F u 2 2 0 0 . 0
2 5 9 R M H O K 2 2
7 0 9 Q K A 7 0 9 2 T B M M
1
2 3
2 0 9 D 7 0 0 1 F U
5 1 9 C V 5 2 / F u 1
4 0 9 D 1 2 V A B
6 3 9 R M H O 0 0 1
9 3 9 R M H O 0 0 1
5 4 9 R W 8 / 1 K 0 1
8 4 9 R K 2 . 2
2 0 9 L H m 6
1
4
2
3
1 2 9 C V 0 0 5 / F u 2 2 0 0 . 0
1 0 9 C F P 0 7 4
5 1 9 D 7 0 0 1 F U
2 4 9 R M H O 0 0 1
+ 7 0 9 C
V 0 5 4 / F u 0 2 1
4 4 9 R W 8 / 1 M H O K 2 . 2
5 3 9 R M H O 0 0 1
7 3 9 R W 8 / 1 M H O K 1
3 5 9 C V 0 5 4 F U 1
4 5 9 R W 4 / 1 M H O 0 0 1
5 0 9 C I
L T - N P 7 7 2 Y N T
1 2
4 5 6 7 8 V U / N E
M / P B
D S S S S
1 2 9 D H
1
2 0 9 G S A M 1 0 2 - 1 4 S G
3 0 9 N C
N N O C
1 2 3 4 5 6 7 8 9 0 1 1 1 2 1 3 1
8 1 9 Q 5 4 A T B M P
2 0 9 C I
1 6 9 6 G S
1
2
3
4
8
7
6
5
B F
p m o C
t l u M
S C
c c V
r e v i r D
D N G
D C Z
3 2 9 L
0 _ L - 2 3 - 4 7 1 L 3 7 1
2
4
3
1 1 9 R M H O K 7 . 8 1
0 2 9 C V 5 2 / F u 1
8 0 9 R W 4 / 1 % 1 - + M H O M 1
1 6 9 R K 1
7 0 9 L H u 8 . 0
1 2 9 L H u 8 . 0
8 4 9 C F u 1 . 0
5 2 9 R W 8 / 1 K 2 2
ZD
905
RLZ
18B
1
2
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G 8 0 6 J B K
2
1
3
4
6 5 9 R K 0 1
+ 2 2 9 C V 0 5 2 F u 2
1 2 9 R K 3 . 3
1 0 9 C I
1 7 2 1 P C N
1
2
3
4 5
6
7
8 P I K S
B F
S C
V R D D N G
C C V
C N
V H
2 0 9 V R 1 6 5 4 1 R V T
1 0 9 B F D A E B
1 2
4 3 9 R W 3 M H O K 5 1
0 1 9 C F p 0 0 5 1
3 0 9 C C A V 0 5 2 F p 0 0 2 2
0 4 9 C F u 1 . 0
0 2 9 R M H O K 3 3
4 1 9 R W 8 / 1 K 9 3
3 0 9 C I G 3 0 1 1 T E C T
1 2
4 3 6 1 9 Q
5 4 A T B M P
9 0 9 R W 4 / 1 % 1 - + M H O M 1
7 0 9 D Z B 1 . 9 Z L R
1 2
8 6 9 R R 0
8 3 9 R K 5 . 1
5 1 9 Q C 7 5 8 C B
3 1 9 D 8 4 1 4 L L M
t
3 0 9 H T C T P
1 2
9 4 9 R W 8 / 1 K 0 1
1 0 9 L H m 6
1
4
2
3
1 3 9 R
K 2 2
8 0 9 D Z B 5 1 Z L R
1 2
5 2 9 D Z B 3 1 Z L R
1 2
7 1 9 Q A 4 9 A S P M
2 6 9 R % 5 W 4 / 1 R 7 4
1 1 9 C V 0 5 4 F U 1
1 0 9 F V 0 5 2 A 5 E S U F
3 4
1 2
1 0 9 D P F 6 0 L 5 H T T S
3 4 9 R M H O 0 0 1
5 5 9 C V 0 5 P 7 2
4 1 9 D A 0 8 1 E K 6 P
+ 1 5 9 C V 6 1 / F u 0 7 4
7 0 9 B F
3.5*
4.7
7 4 9 R K 7 4
+ 8 3 9 C V 5 3 F u 0 2 2
3 0 9 D Z B 6 . 5 Z L R
1 2
0 1 9 R W 8 / 1 K 0 0 1
2 1 9 R W 8 / 1 K 0 1
1 3 9 C V K 1 F P 0 7 2
2 0 9 B F D A E B
1 2
0 3 9 C F u 1 . 0
5 0 9 G S A M 1 0 2 - 1 4 S G
9 1 9 C F u 1 . 0
1 5 9 R R 7 4
8 1 9 R W 8 / 1 K 7 4
4 0 9 C I G 3 0 1 1 T E C T
1 2
4 3
2 1 9 C V 5 2 / F u 1
7 2 9 R M H O 0 1
0 7 9 R W 8 / 1 K 0 9 3
6 0 9 R W 4 / 1 3 M 3
3 2 9 D 1 2 V A B
4 2 9 R W 1 % 5 8 6 R 0
6 1 9 R M H O 7 . 4
9 2 9 R W 8 / 1 M H O K 2 2
4 2 9 C V K 1 / F N 5 . 1
2 2 9 L H u 8 . 0
0 3 9 R M H O K 1
3 1 9 R W 8 / 1 K 0 1
1 0 9 T
8 2 - R E R E W O P
1
6
2
3
5
9
1 1 2 1
7 8
0 1
5 0 9 R W 4 / 1 3 M 3
3 0 9 Q H
1
1 4 9 R K 1 6 . 2
8 2 9 R K 2 2
8 0 9 C I 1 3 4 L T
9 0 9 C V 5 7 2 N 0 8 6
0 4 0 1 F B S 7 1 9 D
1
3 2
9 6 9 R R 0
2 2 9 D D 0 3 P G E
6 2 9 C V 0 5 4 / F u 1 . 0
4 1 9 C V 5 2 F N 0 1
4 2 9 D Z A 3 1 E K 6 P
1 2
2 0 9 Q H
2
5 5 9 R M H O 0
4 0 9 R W 4 / 1 3 M 3
3 0 9 Q P F Z 0 8 K N 8 P T S
6 2 9 R W 8 / 1 K 0 1
8 0 9 C V 5 7 2 N 0 8 6
9 4 9 C V 0 0 1 F u 1 0 . 0
2 1 9 D Z 1 V 9 C - 5 5 X Z B
1 2
6 3 9 C V K 1 F P 0 0 1
8 1 9 C F p 0 0 1
+ 2 3 9 C
V 6 1 F u 0 0 2 2
1 2 9 C I P / T A - A 1 3 4 A I K
7 5 9 R W 8 / 1 % 1 M H O K 4 . 5 1
4 3 9 C V K 1 F P 0 7 2
0 5 9 R W 4 / 1 M H O K 1
3 6 9 R W 8 / 1 M H O K 7 . 4
8 2 9 C V K 1 / F P 0 2 2
5 0 9 C r e p m u j
9 1 9 R W 3 M H O 3 3 . 0
2 2 9 R W 8 / 1 K 5 1
5 1 9 R M H O 0 0 1
2 4 9 C V 5 2 N 0 3 3
1 0 9 G S A M 1 0 2 - 1 4 S G
7 0 9 C I 3 0 1 1 T E C T
1 2
4 3
3 5 9 R M H O 0 0 1
1 2 9 D 0 0 1 0 1 P S
1 2
3
3 2 9 C V 0 5 5 N 1
3 1 9 C V 0 5 P 0 7 4
7 2 9 C V K 1 F P 0 7 2
7 1 9 R M H O 7 4
9 2 9 C V 0 5 4 / F u 1 . 0
6 4 9 R K 1
4 0 9 T 0 2 F E
3
2
1
4
5
8
0 1
6
9
7
t
2 0 9 H T 7 3 0 5 1 K C S
1 2
7 4 9 C F p 0 0 1
4 0 9 C C A V 0 5 2 F p 0 0 2 2
7 1 9 C V 5 2 / F u 1
5 6 9 R 2 M 2
1 0 9 R W 2 / 1 % 5 7 M 2
6 1 9 C F u 1 0 . 0
6 1 9 D D 0 1 P G R
2 0 9 T 8 2 - R E
1 12
5 4
2 5 9 C F u 1 . 0
1 4 9 C F u 1 . 0
2 0 9 Q S L 7 8 0 4 K S 2 2
1
3
3 2 9 R W 1 M H O K 2 8
0 6 9 R W 8 / 1 % 1 - + M H O K 2 2
2 0 9 C F P 0 7 4
5 3 9 C V 5 2 / F u 2 2 0 . 0
1 0 9 N C T E K C O S
1 2
3
3 0 9 T 8 2 - R E
1 12
4 5 9 3
0 1 9 Q 2 0 0 7 K R
9 3 9 C F u 1 . 0
1 1 9 Q C 7 5 8 C B
+
7 3 9 C V 6 1 F u 0 2 2
5 0 9 B F
3.5*
4.7
+ 3 3 9 C
V 5 3 / F u 0 0 0 1
8 5 9 R W 8 / 1 % 5 - + M H O 0 4 2
7 6 9 R W 4 / 1 K 0 1
+ 0 5 9 C
V 0 1 F u 0 0 2 2
5 0 9 T L 8 2 - R E
1 12
5 4
4 0 9 G S A M 1 0 2 - 1 4 S G
9 0 9 D Z 1 V 9 C - 5 5 X Z B
1 2
1 0 9 V R 1 6 5 4 1 R V T
9 0 9 Q 4 0 9 3 S B M P
6 6 9 R % 5 W 8 / 1 K 0 3 3
V 5 9 3
V 4 2
V 2 1
B / S V 4 2
A N E
V 2 1
M I D
B / S
B S V 5 +
S - d d V
B / S
A01 A01
18400_511_090301.eps090619
Adapter
EN 50TPM3.1E LA 10.Circuit Diagrams and PWB Layouts
2009-Jun-26
Power Board Inverter, 42PFL56xx1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
0 1
0 1
1 1
1 1
A A
B B
C C
D D
E E
F F
G G
H H
C N
!
!
!
!
!
!
!
!
l e n a P O U A r e m r o f s n a r t n o f r a D r o f 8 2 8 R l e n a P D G L r e m r o f s n a r t k e t s n a r T r o f 7 2 8 R
l e n a P O U A r e m r o f s n a r t k e t s n a r T r o f 5 2 8 R e t o N
C N
7 D 2 0 8 N C 7 B 3 0 8 N C
4 B 1 0 8 C 5 C 2 0 8 C 4 B 3 0 8 C 4 C 4 0 8 C 7 B 5 0 8 C 7 B 6 0 8 C 7 B 7 0 8 C 7 D 8 0 8 C 7 D 9 0 8 C 7 D 0 1 8 C 2 B 1 1 8 C 2 B 2 1 8 C 2 B 3 1 8 C 2 B 4 1 8 C 2 C 5 1 8 C 2 C 6 1 8 C 4 D 9 1 8 C 6 E 1 2 8 C 5 E 2 2 8 C 2 C 3 2 8 C 5 F 4 2 8 C 7 B 5 2 8 C 7 D 6 2 8 C 7 B 7 2 8 C 8 D 8 2 8 C 7 B 7 0 8 D 7 D 8 0 8 D 8 C 9 0 8 D 3 B 1 0 8 C I 5 D 3 0 8 C I 4 D 4 0 8 C I 4 E 5 0 8 C I 4 E 6 0 8 C I 5 F 8 0 8 C I 5 B 1 0 8 Q 5 B 2 0 8 Q 5 C 6 0 8 Q 5 E 7 0 8 Q 4 B 1 0 8 R 4 C 2 0 8 R 5 C 4 0 8 R 3 B 5 0 8 R 2 C 6 0 8 R 4 D 7 0 8 R 4 C 8 0 8 R 4 D 9 0 8 R 2 C 0 1 8 R 5 C 1 1 8 R 5 D 2 1 8 R 5 D 3 1 8 R 5 D 4 1 8 R 4 F 5 1 8 R 4 E 6 1 8 R 5 E 7 1 8 R 5 F 8 1 8 R 5 E 9 1 8 R 5 E 0 2 8 R 8 D 1 2 8 R 7 C 2 2 8 R 7 C 3 2 8 R 4 E 4 2 8 R 7 C 5 2 8 R 6 E 6 2 8 R 8 C 7 2 8 R 8 C 8 2 8 R 4 C 9 2 8 R 7 C 1 0 8 T 6 A 2 0 8 T 6 B 3 0 8 T 6 C 4 0 8 T 5 C 1 0 8 D Z 6 E 8 0 8 D Z
t r o h s V
d d V
F N
2 S V
1 S V
5 0 8 C I 3 0 1 1 T E C T
1 2
4 3
2 0 8 R % 5 W 8 / 1 R 0 1
9 0 8 R K 9 3
6 0 8 Q C 8 4 8 C B
2 2 8 R K 0 1
1 0 8 T
8 . 9 U U - F R T
1 4
2 3
7 0 8 C V K 6 / F p 5 1
5 2 8 C V 0 5 P 0 2 2
9 1 8 C F u 1 0 . 0
3 2 8 R R 0 1
4 0 8 T
4 2 - U U
1 4
2 3
K 3 3 6 0 8 R
8 0 8 R K 2 6
1 2 8 R K 2 6
3 0 8 T 8 2 U U - F R T
6
5
7
4
1
8
2
3
4 1 8 C V 5 2 N 0 2 2
7 2 8 R % 5 W 8 / 1 R 0 2 2
8 0 8 D 9 9 V A B
3
1 2
1 0 8 C V 0 5 N 0 0 1
8 0 8 D Z B 6 . 5 Z L R
1 2
4 0 8 C V 6 1 U 1
4 1 8 R K 7 . 2
3 0 8 C I 3 0 1 1 T E C T
1 2
4 3
5 1 8 C V 0 5 P 2 2
1 0 8 Q S L 7 9 0 4 K S 2
2
1
3
1 1 8 R K 0 0 1
6 1 8 C V 0 5 J F p 2 8
9 2 8 R M H O 0
5 0 8 C V 0 5 N 1
3 1 8 R R 0 7 4
2 0 8 C V 0 0 5 F N 0 7 4
4 2 8 C V 5 2 U 1
2 0 8 N C N N O C
1 2
1 0 8 C I
1 7 0 2 A B U
1
2
3
4
5
6
7
8
9
2 1 3 1
4 1
5 1
6 1
7 1
9 1
0 2
8 1
0 1
1 1
1 2
2 2
4 2
3 2
B F I
B F I C
B F V
B F V C
P W S C
T C
F C
F E R I
M W P C
d M W P T L U A F , N
a M W P
N E
D D V
D N G P
C N
C N
L G
D N G S
M M O C
C N
H S
H G
S F 1 1 8 C V 0 5 N 7 4
6 0 8 C V 0 5 F N 8 . 1
7 0 8 D 9 9 V A B
3
1 2
5 2 8 R % 5 W 8 / 1 R 2 8
3 2 8 C P 0 7 4
0 1 8 C V 0 5 N 1
8 2 8 C V 0 5 N 1
6 1 8 R K 7 4
7 0 8 Q 4 0 9 3 S B M P
1
3 2
7 2 8 C 7 N 4
9 0 8 D 9 9 V A B
3
1
2
8 1 8 R M H O K 5 1
7 0 8 R K 0 0 1
3 0 8 C V 0 5 4 / F u 1 . 0
8 0 8 C I 1 3 4 L T
0 1 8 R M H O 0
4 0 8 R R 0 7 4
8 2 8 R % 5 W 8 / 1 R 0 0 1
4 2 8 R W 6 / 1 K 0 1
2 1 8 R R 0 7 4
2 1 8 C V 5 2 N 0 2 2
2 2 8 C V 0 5 N 0 0 1
6 2 8 R K 1
1 0 8 D Z B 3 1 Z L R
1 2
2 0 8 T
4 2 - U U
1 4
2 3
9 1 8 R M H O K 0 9 3
0 2 8 R M H O K 0 9 3
1 2 8 C V 0 5 N 0 0 1
5 1 8 R K 7 . 2
6 0 8 C I 3 0 1 1 T E C T
1 2
4 3
9 0 8 C V K 6 / F p 5 1
3 0 8 N C N N O C
1 2
2 0 8 Q S L 7 9 0 4 K S 2
2
1
3
5 0 8 R M H O 0
6 2 8 C P 0 3 3
1 0 8 R % 5 W 8 / 1 R 0 1
8 0 8 C V 0 5 F N 8 . 1
4 0 8 C I 3 0 1 1 T E C T
1 2
4 3
7 1 8 R K 7 . 2
3 1 8 C 7 N 2
V 2 1
V 2 1
A N E
M I D
S - d d V
V 5 9 3
A02 A02
18400_512_090301.eps090619
Inverter
Circuit Diagrams and PWB Layouts EN 51TPM3.1E LA 10.
Circuit Diagrams and PWB Layouts EN 53TPM3.1E LA 10.
2009-Jun-26
SSB: VGA input 32PFL54xx1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
0 1
0 1
1 1
1 1
A A
B B
C C
D D
E E
F F
G G
H H
CI OT ESOLC
OIDUA_CP
4 C 1 0 1 1 N C 2 E 2 0 1 1 N C
5 D 1 0 1 1 C 2 A 2 0 1 1 C 7 B 3 0 1 1 C 8 B 4 0 1 1 C
0 1 B 5 0 1 1 C 2 B 6 0 1 1 C 2 B 7 0 1 1 C 9 C 8 0 1 1 C 9 C 9 0 1 1 C 9 C 0 1 1 1 C 9 C 1 1 1 1 C 7 C 2 1 1 1 C 7 C 3 1 1 1 C 8 C 4 1 1 1 C 9 D 5 1 1 1 C 3 F 6 1 1 1 C 5 F 7 1 1 1 C 3 E 8 1 1 1 C 5 E 9 1 1 1 C 2 A 1 0 1 1 D 7 B 2 0 1 1 D 8 B 3 0 1 1 D 9 B 4 0 1 1 D 5 C 1 0 1 1 B F 7 C 2 0 1 1 B F 7 C 3 0 1 1 B F 7 C 4 0 1 1 B F 3 F 5 0 1 1 B F 3 E 6 0 1 1 B F 4 A 1 0 1 1 R 2 A 3 0 1 1 R 3 A 4 0 1 1 R 7 B 5 0 1 1 R 2 B 6 0 1 1 R 3 B 7 0 1 1 R 4 B 8 0 1 1 R 2 B 9 0 1 1 R 2 B 0 1 1 1 R 8 C 1 1 1 1 R 2 C 2 1 1 1 R 2 C 3 1 1 1 R 8 C 4 1 1 1 R 8 C 5 1 1 1 R 6 C 6 1 1 1 R 6 C 7 1 1 1 R 6 C 8 1 1 1 R 8 D 9 1 1 1 R 4 D 0 2 1 1 R 4 D 1 2 1 1 R 3 D 2 2 1 1 R 4 D 3 2 1 1 R 4 F 4 2 1 1 R 4 F 5 2 1 1 R 4 E 6 2 1 1 R 4 E 7 2 1 1 R 5 C 9 2 1 1 R 7 E 2 3 1 1 R 7 E 3 3 1 1 R 7 E 4 3 1 1 R 7 E 5 3 1 1 R 5 B 7 3 1 1 R 2 A 1 0 1 1 U 3 D 1 0 1 1 D Z 5 D 2 0 1 1 D Z 4 D 3 0 1 1 D Z 3 D 4 0 1 1 D Z 4 D 5 0 1 1 D Z
SH
LCSCDD
R
SV
ADSCDD
B
G
BGR
1XR
1XT
1XT
1XR
21LCS_1PSI
31ADS_AGV
01CP_PWCDD
31NI_G_CP
31NI_B_CP
31GOS_CP
31NI_R_CP31LCS_AGV
21ADS_1PSI
31DNG_CP
81NI_LUA_CP
21CNYSH_CP
21CNYSV_CP
71,31XT0U
71,31XR0U
71,31XR0U
71,31XT0U
81NI_RUA_CP
V5AGV
V5AGV
V5+
DSE_3V3+YBTS_3V3+
6011C
)CN( P33
1011DC45TAB
1
3
2
2211R
W61/1 %5-+ MHOK2.2
1011C
V61 N001
3011D)CN(99VAB
3
12
)CN(W61/1 50R07311R
%5 W61/1 R014311R
6111R
%1 W61/1 R57
2111R)CN(MHO 0
3211RW61/1 %5-+ MHOK2.2
1011BFAm0003/R021
1 2
V61 N019011C
4011C
)CN(N001
V61 N015111C
ZD
1103
BZ
X84
-C5V
6(N
C)
13
3011R
W61/1 %5-+ MHOK01
2011D)CN(99VAB
3
12
Am007/R033011BF1 2
)CN(W61/1 50R09211R
9111RW61/1 %5-+ MHO 001
3111C
V05FP5
V05 Fp00741111C
9111CV05 P033
2011C
V61 N001
1011U
PT6NMW-20C42M
1234 5
6780A
1A2A
ADSSSVLCSPWCCV
Am007/R034011BF1 2
4011D)CN(99VAB
3
12
ZD
1101
BZ
X84
-C5V
6(N
C)
13
ZD
1102
BZ
X84
-C5V
6(N
C)
13
V61 N018011C1111R
%5 W61/1 R86Am007/R032011BF
1 2
6111CV05 P033
2111C
V05FP5
7011C
)CN( P33
)CN(%5 W61/1 R012311R
5011C
)CN(N001
7111R
%1 W61/1 R57
ZD
1104
BZ
X84
-C5V
6(N
C)
13
6011R%5 W61/1 R01
5111R%5 W61/1 R86
8011RW61/1 %5-+ MHOK22
W61/1 %5-+ MHO 0 0211R
V61 N010111C
7111CV05 P033
5011R
)CN(K01
1011RW61/1 %5-+ MHOK01
7011R%5 W61/1 R01
0111RW61/1 %5-+ MHO 0
4111C
V05FP5
2011NC
mm5.3 P3 KCAJ HP
12
3
4011R
W61/1 %5-+ MHOK01
ZD
1105
BZ
X84
-C5V
6(N
C)
13
%5 W61/1 R015311R
9011R)CN(MHO 0
3111RW61/1 %5-+ MHO 0
5211R%5 W61/1 K21
W61/1 %5-+ MHO 0 1211R
3011C
)CN(N001
1011NC51BD
16
27
38
49
5
11
21
31
41
5101
1716
5011BFAm002/R006
1 2
6011BFAm002/R006
1 2
7211R%5 W61/1 K21
8111R
%1 W61/1 R57
)CN(%5 W61/1 R013311R
4111R%5 W61/1 R86
8111CV05 P033
W61/1 %5-+ MHOK01 4211R
W61/1 %5-+ MHOK01 6211R
B01 B01
18400_517_090301.eps090619
VGA input
EN 54TPM3.1E LA 10.Circuit Diagrams and PWB Layouts
2009-Jun-26
SSB: Rear I/O1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
0 1
0 1
1 1
1 1
A A
B B
C C
D D
E E
F F
G G
H H
T U P N I 1 S B V C
T U O F I D P S
C I O T E S O L C
, 3 0 2 1 N C , 1 0 2 1 N C : U E C N 2 3 2 1 C , 1 3 2 1 R
Circuit Diagrams and PWB Layouts EN 55TPM3.1E LA 10.
2009-Jun-26
SSB: SCART1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
0 1
0 1
1 1
1 1
A A
B B
C C
D D
E E
F F
G G
H H
T R A C S L L U F T R A C S F L A H
C N 2 0 3 1 N C , 1 0 3 1 N C : W O R
2 B 1 0 3 1 N C 7 B 2 0 3 1 N C
5 A 1 0 3 1 C 9 A 2 0 3 1 C 4 B 3 0 3 1 C 8 B 5 0 3 1 C 9 B 8 0 3 1 C 9 C 0 1 3 1 C 7 D 1 1 3 1 C 3 D 2 1 3 1 C 2 D 3 1 3 1 C 7 E 5 1 3 1 C 9 E 6 1 3 1 C 7 F 7 1 3 1 C 9 F 8 1 3 1 C 2 F 0 2 3 1 C 3 F 1 2 3 1 C 4 F 2 2 3 1 C 5 F 3 2 3 1 C 4 E 4 2 3 1 C 3 E 5 2 3 1 C 1 F 4 0 3 1 D 2 F 5 0 3 1 D 4 F 6 0 3 1 D 5 F 7 0 3 1 D 4 E 8 0 3 1 D 2 E 9 0 3 1 D 5 E 0 1 3 1 D 3 A 1 0 3 1 B F 8 A 2 0 3 1 B F 8 B 3 0 3 1 B F 7 E 4 0 3 1 B F 7 E 5 0 3 1 B F 4 A 1 0 3 1 R 3 A 2 0 3 1 R 8 A 3 0 3 1 R 8 A 4 0 3 1 R 9 B 5 0 3 1 R 8 C 6 0 3 1 R 3 D 7 0 3 1 R 7 D 8 0 3 1 R 3 D 9 0 3 1 R 7 D 0 1 3 1 R 2 D 1 1 3 1 R 3 D 2 1 3 1 R 8 E 3 1 3 1 R 8 E 4 1 3 1 R 8 E 5 1 3 1 R 8 F 6 1 3 1 R
N I L U A _ 2 T C S
N I R U A _ 2 T C S
N I _ B F _ 1 T C S
N I _ C S _ 2 T C S
N I _ B F _ 1 T C S N I _ B _ 1 T C S N I _ G _ 1 T C S N I _ R _ 1 T C S
N I _ Y S B V C _ 2 T C S
N I R U A _ 2 T C S
N I L U A _ 2 T C S
N I _ C S _ 2 T C S N I _ Y S B V C _ 2 T C S N I S B V C _ 1 T C S
3 1 N I _ S B V C _ 1 T C S
5 N I _ R U A _ 1 T C S
5 N I _ L U A _ 1 T C S
8 T U O _ L U A _ 1 T C S
8 T U O _ R U A _ 1 T C S
8 T U O _ L U A _ 2 T C S
8 T U O _ R U A _ 2 T C S
5 N I _ B _ 1 T C S
5 N I _ R _ 1 T C S
5 N I _ G _ 1 T C S
8 T U O _ S B V C _ 2 T C S
3 1 , 5 1 B F / 1 Y O S
3 1 N I _ S F _ 1 T C S
9 T U O _ S B V C _ 1 T C S
3 1 N I _ S F _ 2 T C S
3 1 N I _ C _ S _ 2 T C S
N I S B V C _ 1 T C S 3 1 N I _ Y _ S B V C _ 2 T C S
8 1 N I _ R U A _ 2 T C S
8 1 N I _ L U A _ 2 T C S D S E _ 3 V 3 +
D S E _ 3 V 3 +
6 0 3 1 R % 1 W 6 1 / 1 R 5 7
4 1 3 1 R % 5 W 6 1 / 1 K 2 1
2 1 3 1 C V 0 5 F p 7 4
4 0 3 1 B F
A m 0 0 2 / R 0 0 6 1 2
8 0 3 1 R % 5 W 6 1 / 1 K 3 3
7 0 3 1 D ) C N ( 9 9 V A B
3
1 2
5 2 3 1 C
) C N ( N 0 0 1
0 1 3 1 R W 6 1 / 1 % 5 - + M H O K 0 1
3 2 3 1 C
) C N ( N 0 0 1
6 1 3 1 C V 0 5 P 0 3 3
1 2 3 1 C
) C N ( N 0 0 1
1 0 3 1 C
V 6 1 N 7 4
7 0 3 1 R W 6 1 / 1 % 5 - + M H O 0
5 0 3 1 D ) C N ( 9 9 V A B
3
1 2
1 1 3 1 C V 0 5 F p 7 4
4 0 3 1 R % 1 W 6 1 / 1 R 5 7
1 0 3 1 N C 1 1 1 0 0 0 - 4 0 5 1 C S 2
1 2
3 4
5 6
7 8
9 0 1
1 1 2 1
3 1 4 1
5 1 6 1
7 1 8 1
9 1 0 2
1 2
22
23
1 0 3 1 B F
A m 0 0 5 / R 0 2 1 1 2
3 0 3 1 C V 0 5 F p 7 4
4 0 3 1 D ) C N ( 9 9 V A B
3
1 2
5 0 3 1 C V 0 5 F p 7 4
2 0 3 1 C
V 6 1 N 7 4
0 1 3 1 C V 0 5 F p 7 4
6 1 3 1 R % 5 W 6 1 / 1 K 2 1
8 0 3 1 D ) C N ( 9 9 V A B
3
1 2
6 0 3 1 D ) C N ( 9 9 V A B
3
1 2
2 0 3 1 B F
A m 0 0 5 / R 0 2 1 1 2
2 1 3 1 R W 6 1 / 1 % 5 - + M H O K 0 1
4 2 3 1 C
) C N ( N 0 0 1
2 0 3 1 N C 1 1 1 0 0 0 - 4 0 5 1 C S 2
1 2
3 4
5 6
7 8
9 0 1
1 1 2 1
3 1 4 1
5 1 6 1
7 1 8 1
9 1 0 2
1 2
22
23
8 0 3 1 C
V 6 1 N 7 4
9 0 3 1 D ) C N ( 9 9 V A B
3
1 2
1 0 3 1 R W 6 1 / 1 % 5 - + M H O 0 0 1
2 2 3 1 C
) C N ( N 0 0 1
5 0 3 1 B F
A m 0 0 2 / R 0 0 6 1 2
3 0 3 1 R W 6 1 / 1 % 5 - + M H O 0 0 1
8 1 3 1 C V 0 5 P 0 3 3
W 6 1 / 1 % 5 - + M H O K 0 1 5 1 3 1 R
5 0 3 1 R W 6 1 / 1 % 5 - + M H O 0 0 1
0 1 3 1 D ) C N ( 9 9 V A B
3 1
2
3 0 3 1 B F
A m 0 0 5 / R 0 2 1 1 2
5 1 3 1 C V 0 5 P 0 3 3
3 1 3 1 C V 0 5 F p 7 4
9 0 3 1 R % 5 W 6 1 / 1 K 3 3
W 6 1 / 1 % 5 - + M H O K 0 1 3 1 3 1 R
2 0 3 1 R % 1 W 6 1 / 1 R 5 7
0 2 3 1 C
) C N ( N 0 0 1
1 1 3 1 R % 1 W 6 1 / 1 R 5 7
7 1 3 1 C V 0 5 P 0 3 3
B03 B03
18400_519_090301.eps090619
Scart
EN 56TPM3.1E LA 10.Circuit Diagrams and PWB Layouts
2009-Jun-26
SSB: Side I/O1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
E E
1 A A 1 0 4 1 N 1 C B 1 0 4 1 N 1 D 2 0 4 1 N C 7 C 3 0 4 1 N C 7 B 4 0 4 1 N C 1 C 5 0 4 1 N C
3 A 1 0 4 1 C 3 B 2 0 4 1 C 3 C 3 0 4 1 C 4 A 4 0 4 1 C 3 D 5 0 4 1 C 3 D 6 0 4 1 C 4 B 7 0 4 1 C 4 B 8 0 4 1 C 4 D 9 0 4 1 C 6 B 3 1 4 1 C 3 C 4 1 4 1 C 2 C 5 1 4 1 C 2 C 6 1 4 1 C 3 C 7 1 4 1 C 5 B 8 1 4 1 C 3 A 1 0 4 1 B F 3 D 2 0 4 1 B F 3 B 3 0 4 1 B F 3 B 4 0 4 1 B F 2 C 5 0 4 1 B F 2 C 6 0 4 1 B F 6 A 7 0 4 1 B F 6 B 8 0 4 1 B F 6 B 9 0 4 1 B F
2 A 1 0 4 1 R 3 A 2 0 4 1 R 2 D 4 0 4 1 R 3 B 5 0 4 1 R 2 B 6 0 4 1 R 3 B 7 0 4 1 R 2 B 8 0 4 1 R 3 C 9 0 4 1 R 3 C 0 1 4 1 R 6 C 1 1 4 1 R 6 C 2 1 4 1 R 6 C 3 1 4 1 R 3 C 4 1 4 1 R 6 C 5 1 4 1 R 3 C 6 1 4 1 R 2 D 7 1 4 1 R 5 B 8 1 4 1 R 6 B 9 1 4 1 R 4 D 1 0 4 1 H T
2 D 1 0 4 1 U
T U O L P H
N I _ 1 Y V S
T E D P R A E
T U O R P H
V 5 _ B S U
N I _ 1 C V S
3 1 N I _ Y V S _ E D I S
T U O L _ P H 9 1
T U O R _ P H 9 1
8 1 N I _ L U A _ S B V C _ E D I S
8 1 N I _ R U A _ S B V C _ E D I S
T E D _ P R A E 3 1
3 1 C O _ B S U
3 1 P D _ B S U 3 1 N D _ B S U
3 1 N I _ C V S _ E D I S
3 1 N I _ S B V C _ E D I S
D P H _ 3 I M D H 1 1 , 0 1
A D S _ C D D _ 3 I M D H 3 1 , 1 1 , 0 1 L C S _ C D D _ 3 I M D H 3 1 , 1 1 , 0 1
C E C 1 1 , 0 1
+ K C _ 3 I M D H 3 1 , 1 1
- 0 D _ 3 I M D H 3 1 , 1 1 + 0 D _ 3 I M D H 3 1 , 1 1
- 1 D _ 3 I M D H 3 1 , 1 1 + 1 D _ 3 I M D H 3 1 , 1 1
- 2 D _ 3 I M D H 3 1 , 1 1 + 2 D _ 3 I M D H 3 1 , 1 1
Circuit Diagrams and PWB Layouts EN 57TPM3.1E LA 10.
2009-Jun-26
SSB: CVBS, Audio out1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
E E
EU: CN1501 n.c.
7 A 1 0 5 1 N C 2 B 1 0 5 1 C 6 A 2 0 5 1 C 5 A 3 0 5 1 C 6 A 4 0 5 1 C 5 A 5 0 5 1 C 2 A 6 0 5 1 C 3 A 7 0 5 1 C 5 A 8 0 5 1 C 5 C 0 1 5 1 C 5 D 1 1 5 1 C 7 B 3 1 5 1 C 5 C 4 1 5 1 C 2 B 6 1 5 1 C 5 C 7 1 5 1 C 5 A 8 1 5 1 C 7 B 9 1 5 1 C 5 C 0 2 5 1 C 4 C 1 2 5 1 C 3 C 2 2 5 1 C 4 E 3 2 5 1 C 4 C 4 2 5 1 C 2 D 5 2 5 1 C 3 C 6 2 5 1 C 4 E 7 2 5 1 C 3 E 8 2 5 1 C 3 E 9 2 5 1 C 7 D 0 3 5 1 C 2 D 3 3 5 1 C 7 D 7 3 5 1 C 6 A 2 0 5 1 Q 3 A 1 0 5 1 R 6 A 2 0 5 1 R 6 A 3 0 5 1 R 7 A 4 0 5 1 R 6 A 5 0 5 1 R 6 A 6 0 5 1 R 4 B 7 0 5 1 R 2 B 8 0 5 1 R 2 B 9 0 5 1 R 3 C 0 1 5 1 R 3 C 1 1 5 1 R 4 D 2 1 5 1 R 3 E 3 1 5 1 R 2 D 4 1 5 1 R 3 E 5 1 5 1 R 2 D 6 1 5 1 R 6 B 7 1 5 1 R 6 B 8 1 5 1 R 6 D 9 1 5 1 R 6 D 0 2 5 1 R 3 B 3 2 5 1 R 3 B 4 2 5 1 R 6 B 5 2 5 1 R 6 B 6 2 5 1 R 6 D 7 2 5 1 R 6 D 8 2 5 1 R 3 D 9 2 5 1 R 3 D 0 3 5 1 R 4 B 1 0 5 1 U 4 C 2 0 5 1 U
2 R A 3 1
2 L A 3 1
3 R A 3 1
3 L A 3 1
6 T U O _ L U A _ 1 T C S
6 T U O _ R U A _ 1 T C S
6 T U O _ S B V C _ 2 T C S T U O _ S B V C 6 1 , 3 1
6 T U O _ L U A _ 2 T C S
6 T U O _ R U A _ 2 T C S
E T U M _ P O P 9 1 , 3 1
E T U M _ P O P 9 1 , 3 1
V 5 _ P O N O _ V 5 +
R E N U T _ V 5 + R E N U T _ V 5 +
V 5 _ P O
V 5 _ P O
9 2 5 1 C V 0 5 8 N 1
0 1 5 1 C 3 V 6 F U 1
3 1 5 1 R W 6 1 / 1 % 5 - + M H O K 0 3
6 0 5 1 C
V 6 1 N 0 0 1
4 0 5 1 R
) C N ( % 1 W 6 1 / 1 M H O 5 7
4 2 5 1 C V 0 5 P 0 8 1
7 2 5 1 R ) C N ( M H O K 7 4
4 1 5 1 R W 6 1 / 1 % 5 - + M H O K 0 1
% 5 W 0 1 / 1 R 0 1 9 1 5 1 R
5 0 5 1 C 3 V 6 F U 1
6 2 5 1 C V 0 5 8 N 1
8 2 5 1 R ) C N ( M H O K 7 4
5 1 5 1 R W 6 1 / 1 % 5 - + M H O K 0 3
7 2 5 1 C V 0 5 P 0 8 1
% 5 W 0 1 / 1 R 0 1 7 0 5 1 R
6 1 5 1 R W 6 1 / 1 % 5 - + M H O K 0 1
0 1 5 1 R W 6 1 / 1 % 5 - + M H O K 0 3
3 2 5 1 C V 0 5 P 0 8 1
+
3 0 5 1 C
) C N ( V 5 2 F u 7 4
2 2 5 1 C V 0 5 8 N 1
9 2 5 1 R W 6 1 / 1 % 5 - + M H O K 0 1
1 1 5 1 R W 6 1 / 1 % 5 - + M H O K 0 3
+ 7 0 5 1 C V 0 1 F U 0 7 4
0 3 5 1 R W 6 1 / 1 % 5 - + M H O K 0 1
1 1 5 1 C 3 V 6 F U 1
% 5 W 0 1 / 1 R 0 1 8 1 5 1 R 8 0 5 1 R W 6 1 / 1 % 5 - + M H O K 0 1
5 2 5 1 R ) C N ( M H O K 7 4
6 0 5 1 R ) C N ( % 1 W 6 1 / 1 M H O 5 7
5 2 5 1 C
3 V 6 F U 1
2 0 5 1 R ) C N ( % 5 W 6 1 / 1 K 0 1
9 0 5 1 R W 6 1 / 1 % 5 - + M H O K 0 1
1 0 5 1 R
W 0 1 / 1 % 5 - + M H O 0
2 0 5 1 Q ) C N ( C 7 4 8 C B
4 1 5 1 C 3 V 6 F U 1
1 0 5 1 N C
) C N ( 8 9 - 3 8 0 - 0 7 8 - 5 0 1 5
2
1
4
3
6
5
3 2 5 1 R W 6 1 / 1 % 5 - + M H O K 0 1
6 1 5 1 C
3 V 6 F U 1
3 1 5 1 C V 0 5 8 N 1
5 0 5 1 R ) C N ( W 6 1 / 1 M H O K 3 3
4 2 5 1 R W 6 1 / 1 % 5 - + M H O K 0 1
3 3 5 1 C
3 V 6 F U 1
1 0 5 1 C
3 V 6 F U 1
0 2 5 1 C V 5 2 U 1
% 5 W 0 1 / 1 R 0 1 7 1 5 1 R
1 0 5 1 U
+ C T E A 8 2 7 9 X A M
4
3
1 1
9 1
7
0 1
5
2 8
2 1
6
s s V P
C1N
L T U O
SV
ssC
1P
SG
ND
R T U O
N D H S
PG
ND
IN
R
D D V
L _ N I
2 0 5 1 U
+ C T E A 8 2 7 9 X A M
4
3
1 1
9 1
7
0 1
5
2 8
2 1
6
s s V P
C1N
L T U O
SV
ssC
1P
SG
ND
R T U O
N D H S
PG
ND
IN
R
D D V
L _ N I
+
4 0 5 1 C ) C N ( V 0 1 F U 0 7 4
% 5 W 0 1 / 1 R 0 1 2 1 5 1 R
6 2 5 1 R ) C N ( M H O K 7 4
8 0 5 1 C
V 0 1 U 0 1
7 1 5 1 C
V 0 1 U 0 1
3 0 5 1 R ) C N ( % 5 W 6 1 / 1 R 0 1
9 1 5 1 C V 0 5 8 N 1
% 5 W 0 1 / 1 R 0 1 0 2 5 1 R
8 2 5 1 C V 0 5 8 N 1
0 3 5 1 C V 0 5 8 N 1
2 0 5 1 C
) C N ( V 6 1 N 0 0 1
7 3 5 1 C V 0 5 8 N 1
8 1 5 1 C V 5 2 U 1
1 2 5 1 C V 0 5 P 0 8 1
B05 B05
18400_521_090301.eps090619
CVBS, Audio out
EN 58TPM3.1E LA 10.Circuit Diagrams and PWB Layouts
2009-Jun-26
SSB: Tuner1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
E E
T F I H S L E V E L C I I
T U O 1 T R A C S U E R O F
2 A 1 0 6 1 C 6 B 6 0 3 1 C 4 A 3 0 6 1 C 3 D 2 0 6 1 C 3 B 9 0 6 1 C 3 A 4 0 6 1 C 2 D 1 1 6 1 C 6 B 0 1 6 1 C 7 C 3 1 6 1 C 5 B 2 1 6 1 C 7 C 6 1 6 1 C 4 C 5 1 6 1 C 6 C 8 1 6 1 C 3 C 7 1 6 1 C 4 C 0 2 6 1 C 6 C 9 1 6 1 C 5 D 2 2 6 1 C 5 D 1 2 6 1 C 5 A 1 0 6 1 L 4 A 4 2 6 1 C 4 B 2 0 6 1 Q 6 D 1 0 6 1 Q 7 D 4 0 6 1 Q 7 C 3 0 6 1 Q 7 E 6 0 6 1 Q 6 E 5 0 6 1 Q 3 B 2 0 6 1 R 3 A 1 0 6 1 R 3 B 6 0 6 1 R 4 B 5 0 6 1 R 5 B 9 0 6 1 R 5 B 8 0 6 1 R 3 B 1 1 6 1 R 5 B 0 1 6 1 R 5 C 3 1 6 1 R 4 B 2 1 6 1 R 7 C 6 1 6 1 R 3 C 5 1 6 1 R 7 C 8 1 6 1 R 3 C 7 1 6 1 R 5 C 0 2 6 1 R 3 C 9 1 6 1 R 3 C 2 2 6 1 R 7 C 1 2 6 1 R 5 D 4 2 6 1 R 6 D 3 2 6 1 R 6 E 6 2 6 1 R 5 D 5 2 6 1 R 1 A 1 0 6 1 U T 6 D 7 2 6 1 R 6 C 1 0 6 1 U 1 C 2 0 6 1 U T
I V A _ U T
C G A _ U T
R E N U T _ S V F I S _ U T
R E N U T _ S V
C G A _ U T
S A _ U T
T F A _ U T
S B V C _ U T
A D S _ U T L C S _ U T
L C S _ U T A D S _ U T
F I S _ U T
A D S _ U T L C S _ U T
S B V C _ U T
S A _ U T
3 1 S B V C _ V T
3 1 P _ F I S
3 1 N _ F I S
3 1 , 2 1 L C S _ T M
3 1 , 2 1 A D S _ T M
3 1 D N G _ S B V C _ r e n u T
3 1 # L T C _ T U O _ S B V C _ 1 T C S
6 T U O _ S B V C _ 1 T C S
R E N U T _ V 5 + N O _ V 5 +
N O _ V 5 +
N O _ V 5 +
R E N U T _ V 5 +
3 V 3 +
3 V 3 +
R E N U T _ V 5 +
R E N U T _ V 5 +
4 0 6 1 C V 6 1 N 0 0 1
5 1 6 1 R W 6 1 / 1 % 5 - + M H O 0
2 2 6 1 C
V 0 5 P 3 3
4 0 6 1 Q 2 0 0 7 N 2
2 0 6 1 Q C 7 4 8 C B
8 1 6 1 C V 6 1 N 0 0 1
V 6 1 N 0 0 1 0 2 6 1 C
8 1 6 1 R % 1 W 6 1 / 1 R 5 7
6 2 6 1 R % 5 W 6 1 / 1 7 K 4
6 0 6 1 R W 6 1 / 1 % 5 - + M H O 0
0 1 6 1 C
V 6 1 N 7 4
+ 3 0 6 1 C V 0 1 F u 0 0 0 1
+
6 1 6 1 C
V 0 1 F U 0 7 4
1 0 6 1 Q 2 0 0 7 N 2
1 1 6 1 R W 6 1 / 1 % 5 - + M H O K 3 3
9 0 6 1 R W 6 1 / 1 % 5 - + M H O 0 0 1
2 0 6 1 R W 6 1 / 1 % 5 - + M H O K 0 1
4 2 6 1 C
V 0 1 U 0 1
V 6 1 N 0 0 1 5 1 6 1 C
5 0 6 1 R
% 5 W 6 1 / 1 R 0 1
0 2 6 1 R W 6 1 / 1 % 5 - + M H O K 3 3
7 1 6 1 C
V 0 5 P 2 2
% 5 W 6 1 / 1 R 0 1 5 2 6 1 R
) C N ( R 0 7 2 6 1 R
1 0 6 1 U
X 6 P 7 5 1 3 B S 7 C N
1 2 3 4
5 6 1 B
D N G A 0 B C C V S
1 2 6 1 C
V 0 5 P 3 3
6 0 3 1 C
3 V 6 F U 1
8 0 6 1 R
% 1 W 6 1 / 1 R 5 7
2 2 6 1 R W 6 1 / 1 % 5 - + M H O 0
3 1 6 1 C
V 6 1 N 0 0 1
0 1 6 1 R % 1 W 6 1 / 1 R 5 7
% 5 W 6 1 / 1 R 0 1 4 2 6 1 R
9 1 6 1 R ) C N ( 2 K 2
2 1 6 1 C V 0 5 F p 7 4
1 1 6 1 C ) C N ( V 6 1 N 0 3 3
2 0 6 1 U T ) C N ( 5 3 2 / 3 C 6 - M T S
1 2 3 4 5 6 7 8 9 0 1 1 1 2 1
13
14
15
16
) P T ( T B ) P T ( F I
C N S A A D S L C S V 5 + F I S C G A T F A O I D U A O E D I V
TH
1 T
H2
TH
3 T
H4
3 1 6 1 R W 6 1 / 1 % 5 - + M H O K 0 1
+
9 0 6 1 C
V 5 2 F u 7 4
1 0 6 1 U T R E N U T
1 2 3 4 5 6 7 8 9 0 1 1 1 2 1 3 1 4 1 5 1 6 1
17
18
19
20
C N C N D N G ) V 5 ( B +
C G A F R D N G A D S L C S S A U T C N C N C N F I S C N O I D U A O E D I V T
H1
TH
2 T
H3
TH
4
9 1 6 1 C V 5 2 U 1
3 0 6 1 Q C 7 4 8 C B
3 2 6 1 R % 5 W 6 1 / 1 7 K 4
2 0 6 1 C V 6 1 N 0 0 1
6 0 6 1 Q 2 0 0 7 N 2
1 2 6 1 R % 1 W 6 1 / 1 R 5 7
1 0 6 1 R ) C N ( R 0
2 1 6 1 R % 1 W 6 1 / 1 R 5 7
7 1 6 1 R
W 6 1 / 1 % 5 - + M H O 0
5 0 6 1 Q 2 0 0 7 N 2
1 0 6 1 C
) C N ( V 6 1 2 U 2
1 0 6 1 L H u 0 5 1
6 1 6 1 R
% 5 W 6 1 / 1 R 0 1
B06 B06
18400_522_090301.eps090619
Tuner
Circuit Diagrams and PWB Layouts EN 59TPM3.1E LA 10.
2009-Jun-26
SSB: HDMI Input1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
E E
5 D 3 0 7 1 C 5 B 2 0 7 1 C 5 A 1 0 7 1 C 1 D 2 0 7 1 N C 1 A 1 0 7 1 N C 5 A 5 0 7 1 D 7 B 4 0 7 1 D 7 A 3 0 7 1 D 7 A 2 0 7 1 D 7 A 1 0 7 1 D 2 C 3 0 7 1 Q 7 B 2 0 7 1 Q 7 A 1 0 7 1 Q 5 D 7 0 7 1 D 5 B 6 0 7 1 D 2 E 8 0 7 1 Q 2 E 7 0 7 1 Q 7 C 6 0 7 1 Q 7 C 5 0 7 1 Q 2 C 4 0 7 1 Q
5 A 6 0 7 1 R 4 A 5 0 7 1 R 4 A 4 0 7 1 R 2 A 3 0 7 1 R 2 A 1 0 7 1 R 7 B 1 1 7 1 R 7 B 0 1 7 1 R 5 B 9 0 7 1 R 2 A 8 0 7 1 R 2 A 7 0 7 1 R 7 C 6 1 7 1 R 7 C 5 1 7 1 R 5 C 4 1 7 1 R 4 C 3 1 7 1 R 4 C 2 1 7 1 R 7 C 1 2 7 1 R 5 C 0 2 7 1 R 7 C 9 1 7 1 R 2 C 8 1 7 1 R 2 C 7 1 7 1 R 4 D 6 2 7 1 R 2 D 5 2 7 1 R 2 D 4 2 7 1 R 2 D 3 2 7 1 R 2 D 2 2 7 1 R 2 E 1 3 7 1 R 2 E 0 3 7 1 R 5 D 9 2 7 1 R 5 D 8 2 7 1 R 4 D 7 2 7 1 R 5 D 4 0 7 1 U 5 C 3 0 7 1 U 5 A 2 0 7 1 U 1 C 1 0 7 1 U 7 A 2 3 7 1 R
1 1 D P H _ 1 I M D H
3 1 , 1 1 A D S _ C D D _ 1 I M D H 3 1 , 1 1 L C S _ C D D _ 1 I M D H
3 1 P W _ C D D
A D S _ C D D _ 1 I M D H 3 1 , 1 1 L C S _ C D D _ 1 I M D H 3 1 , 1 1
3 1 , 1 1 + K C _ 1 I M D H
3 1 , 1 1 - 0 D _ 1 I M D H 3 1 , 1 1 + 0 D _ 1 I M D H
3 1 , 1 1 - 1 D _ 1 I M D H 3 1 , 1 1 + 1 D _ 1 I M D H
3 1 , 1 1 - 2 D _ 1 I M D H 3 1 , 1 1 + 2 D _ 1 I M D H
3 1 , 1 1 - K C _ 1 I M D H
C P _ P W C D D 4
L C S _ C D D _ 2 I M D H 3 1 , 1 1 A D S _ C D D _ 2 I M D H 3 1 , 1 1
2 I M D H _ P W C D D
D P H _ 2 I M D H 1 1
D P H _ 1 I M D H 1 1
D P H _ 3 I M D H 1 1 , 7
3 1 L T C _ D P H _ 1 I M D H
2 I M D H _ P W C D D
3 I M D H _ P W C D D
1 I M D H _ P W C D D 1 I M D H _ P W C D D
1 1 D P H _ 2 I M D H
3 1 , 1 1 A D S _ C D D _ 2 I M D H 3 1 , 1 1 L C S _ C D D _ 2 I M D H
3 1 C E C _ T M C E C 1 1 , 7
2 1 C E C _ U C M
3 1 , 1 1 + K C _ 2 I M D H
3 1 , 1 1 - 0 D _ 2 I M D H 3 1 , 1 1 + 0 D _ 2 I M D H
3 1 , 1 1 - 1 D _ 2 I M D H 3 1 , 1 1 + 1 D _ 2 I M D H
3 1 , 1 1 - 2 D _ 2 I M D H 3 1 , 1 1 + 2 D _ 2 I M D H
3 1 , 1 1 - K C _ 2 I M D H
L C S _ C D D _ 3 I M D H 3 1 , 1 1 , 7 A D S _ C D D _ 3 I M D H 3 1 , 1 1 , 7
+ 2 D d l e i h S 2 D - 2 D + 1 D d l e i h S 1 D - 1 D + 0 D d l e i h S 0 D - 0 D + K C d l e i h S K C - K C e t o m e R E C C N K L C C D D A T A D C D D D N G V 5 + T E D P H
+ 2 D d l e i h S 2 D - 2 D + 1 D d l e i h S 1 D - 1 D + 0 D d l e i h S 0 D - 0 D + K C d l e i h S K C - K C e t o m e R E C C N K L C C D D A T A D C D D D N G V 5 + T E D P H
3 H T 4 H T 5 H T
8 4 1 4 S L 3 0 7 1 D
0 2 7 1 R ) C N ( K 0 0 1
% 5 W 6 1 / 1 R 0 1 1 1 7 1 R
B07 B07
18400_523_090301.eps090619
HDMI Input
EN 60TPM3.1E LA 10.Circuit Diagrams and PWB Layouts
2009-Jun-26
SSB: HDMI ESD protection1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
E E
3 B 1 0 1 2 R 2 A 1 0 1 2 U 2 B 2 0 1 2 U 2 B 3 0 1 2 U 6 B 4 0 1 2 U 6 B 5 0 1 2 U 6 C 6 0 1 2 U 2 C 7 0 1 2 U 2 D 8 0 1 2 U 2 E 9 0 1 2 U
L C S _ C D D _ 1 I M D H
A D S _ C D D _ 1 I M D H D P H _ 1 I M D H
L C S _ C D D _ 3 I M D H
A D S _ C D D _ 3 I M D H D P H _ 3 I M D H
- 2 D _ 1 I M D H
- K C _ 3 I M D H + K C _ 3 I M D H
- 0 D _ 3 I M D H + 0 D _ 3 I M D H
E _ C E C
- 1 D _ 3 I M D H + 1 D _ 3 I M D H
- 2 D _ 3 I M D H + 2 D _ 3 I M D H
+ 2 D _ 1 I M D H
E _ C E C
+ 1 D _ 1 I M D H
L C S _ C D D _ 2 I M D H
- K C _ 2 I M D H + K C _ 2 I M D H
- 0 D _ 2 I M D H + 0 D _ 2 I M D H
+ 0 D _ 1 I M D H
- 1 D _ 2 I M D H + 1 D _ 2 I M D H
- 0 D _ 1 I M D H - 2 D _ 2 I M D H
+ K C _ 1 I M D H
+ 2 D _ 2 I M D H
A D S _ C D D _ 2 I M D H
- K C _ 1 I M D H
D P H _ 2 I M D H
- 1 D _ 1 I M D H
3 1 , 0 1 - 0 D _ 1 I M D H
3 1 , 7 - K C _ 3 I M D H
3 1 , 0 1 + 2 D _ 1 I M D H
3 1 , 0 1 - 0 D _ 2 I M D H
3 1 , 0 1 + 2 D _ 2 I M D H
3 1 , 0 1 + K C _ 2 I M D H
0 1 D P H _ 2 I M D H
3 1 , 0 1 L C S _ C D D _ 2 I M D H
3 1 , 0 1 - 1 D _ 2 I M D H
3 1 , 0 1 - 2 D _ 2 I M D H
3 1 , 0 1 + 1 D _ 2 I M D H
3 1 , 0 1 A D S _ C D D _ 2 I M D H
3 1 , 0 1 + 0 D _ 2 I M D H
3 1 , 0 1 + K C _ 1 I M D H 3 1 , 0 1 - K C _ 1 I M D H
0 1 , 7 C E C
0 1 D P H _ 1 I M D H
3 1 , 0 1 L C S _ C D D _ 1 I M D H
3 1 , 0 1 - 1 D _ 1 I M D H
3 1 , 0 1 - 2 D _ 1 I M D H
3 1 , 0 1 + 1 D _ 1 I M D H
3 1 , 0 1 A D S _ C D D _ 1 I M D H
3 1 , 7 - 0 D _ 3 I M D H
3 1 , 7 + 2 D _ 3 I M D H
3 1 , 7 + K C _ 3 I M D H
3 1 , 0 1 - K C _ 2 I M D H
0 1 , 7 D P H _ 3 I M D H
3 1 , 0 1 , 7 L C S _ C D D _ 3 I M D H
3 1 , 7 - 1 D _ 3 I M D H
3 1 , 7 - 2 D _ 3 I M D H
3 1 , 7 + 1 D _ 3 I M D H
3 1 , 0 1 , 7 A D S _ C D D _ 3 I M D H
3 1 , 7 + 0 D _ 3 I M D H
3 1 , 0 1 + 0 D _ 1 I M D H
) C N ( T C T . P 4 2 5 0 p m a l C R 7 0 1 2 U
1 2
3
4 5 6
7
8
9 0 1 1 N I
2 N I
GN
D
3 N I 4 N I 4 T U O
3 T U O
GN
D
2 T U O 1 T U O
) C N ( T C T . P 4 2 5 0 p m a l C R 1 0 1 2 U
1 2
3
4 5 6
7
8
9 0 1 1 N I
2 N I
GN
D
3 N I 4 N I 4 T U O
3 T U O
GN
D
2 T U O 1 T U O
) C N ( T C T . P 4 2 5 0 p m a l C R 8 0 1 2 U
1 2
3
4 5 6
7
8
9 0 1 1 N I
2 N I
GN
D
3 N I 4 N I 4 T U O
3 T U O
GN
D
2 T U O 1 T U O
) C N ( T C T . P 4 2 5 0 p m a l C R 4 0 1 2 U
1 2
3
4 5 6
7
8
9 0 1 1 N I
2 N I
GN
D
3 N I 4 N I 4 T U O
3 T U O
GN
D
2 T U O 1 T U O
) C N ( W 6 1 / 1 5 0 R 0 1 0 1 2 R ) C N ( T C T . P 4 2 5 0 p m a l C R 3 0 1 2 U
1 2
3
4 5 6
7
8 9 0 1 1 N I
2 N I
GN
D
3 N I 4 N I 4 T U O
3 T U O
GN
D
2 T U O 1 T U O
) C N ( T C T . P 4 2 5 0 p m a l C R 6 0 1 2 U
1 2
3
4 5 6
7
8
9 0 1 1 N I
2 N I
GN
D
3 N I 4 N I 4 T U O
3 T U O
GN
D
2 T U O 1 T U O
) C N ( T C T . P 4 2 5 0 p m a l C R 2 0 1 2 U
1 2
3
4 5 6
7
8
9 0 1 1 N I
2 N I
GN
D
3 N I 4 N I 4 T U O
3 T U O
GN
D
2 T U O 1 T U O
) C N ( T C T . P 4 2 5 0 p m a l C R 9 0 1 2 U
1 2
3
4 5 6
7
8
9 0 1 1 N I
2 N I
GN
D
3 N I 4 N I 4 T U O
3 T U O
GN
D
2 T U O 1 T U O
) C N ( T C T . P 4 2 5 0 p m a l C R 5 0 1 2 U
1 2
3
4 5 6
7
8
9 0 1 1 N I
2 N I
GN
D
3 N I 4 N I 4 T U O
3 T U O
GN
D
2 T U O 1 T U O
B08 B08
18400_524_090301.eps090619
HDMI ESD protection
Circuit Diagrams and PWB Layouts EN 61TPM3.1E LA 10.
Circuit Diagrams and PWB Layouts EN 63TPM3.1E LA 10.
2009-Jun-26
SSB: DDR1 Memory1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
E E
3 B 1 0 1 5 C 4 A 2 0 1 5 C 5 A 3 0 1 5 C 5 A 4 0 1 5 C 5 B 5 0 1 5 C 5 B 6 0 1 5 C 5 B 7 0 1 5 C 4 B 8 0 1 5 C 5 B 9 0 1 5 C 5 C 0 1 1 5 C 1 C 1 1 1 5 C 2 C 2 1 1 5 C 2 C 3 1 1 5 C 2 C 4 1 1 5 C 3 C 5 1 1 5 C 3 C 6 1 1 5 C 1 C 7 1 1 5 C 3 C 8 1 1 5 C 3 C 9 1 1 5 C 3 C 0 2 1 5 C 5 C 1 2 1 5 C 2 C 2 2 1 5 C 5 C 3 2 1 5 C 1 C 4 2 1 5 C 2 C 5 2 1 5 C 5 D 6 2 1 5 C 2 D 7 2 1 5 C 3 D 8 2 1 5 C 3 D 9 2 1 5 C 4 D 0 3 1 5 C 5 D 1 3 1 5 C 5 A 1 0 1 5 P R 6 A 2 0 1 5 P R 5 A 3 0 1 5 P R 6 A 4 0 1 5 P R 5 B 5 0 1 5 P R 6 B 6 0 1 5 P R 5 B 7 0 1 5 P R 6 B 8 0 1 5 P R 5 C 9 0 1 5 P R 6 C 0 1 1 5 P R 5 C 1 1 1 5 P R 6 C 2 1 1 5 P R 5 C 3 1 1 5 P R 6 C 4 1 1 5 P R 5 D 5 1 1 5 P R 6 D 6 1 1 5 P R 5 D 7 1 1 5 P R 6 D 8 1 1 5 P R
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6 R D D A _ M E M 5 R D D A _ M E M 4 R D D A _ M E M
0 Q D _ M E M
F E R V _ M E M
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0 Q D R 1 Q D R 2 Q D R 3 Q D R
4 Q D R 5 Q D R 6 Q D R 7 Q D R
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4 A R 5 A R 6 A R 7 A R
9 A R 1 1 A R 2 1 A R
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7 R D D A _ M E M
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B11 B11
18400_527_090301.eps090619
DDR1 Memory
EN 64TPM3.1E LA 10.Circuit Diagrams and PWB Layouts
2009-Jun-26
SSB: Panel Interface1
1
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2
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3
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5
6
6
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0 1
0 1
1 1
1 1
A A
B B
C C
D D
E E
F F
G G
H H
D H " 2 3 D H F " 7 2
4 E 1 0 2 5 N C 1 B 2 0 2 5 N C 8 B 3 0 2 5 N C 6 B 4 0 2 5 N C 2 B 5 0 2 5 N C
4 A 1 0 2 5 C 5 B 6 0 4 5 C 4 A 1 0 2 5 R 4 B 2 0 2 5 R 9 B 3 0 2 5 R 9 B 4 0 2 5 R 9 B 5 0 2 5 R 3 D 6 0 2 5 R 3 D 7 0 2 5 R 3 C 8 0 2 5 R 3 C 9 0 2 5 R 5 E 0 1 2 5 R
0 1 C 1 1 2 5 R 0 1 C 2 1 2 5 R 0 1 C 3 1 2 5 R
5 E 4 1 2 5 R 5 E 5 1 2 5 R 9 D 7 1 2 5 R 9 D 8 1 2 5 R 9 E 9 1 2 5 R 9 E 0 2 2 5 R 9 E 1 2 2 5 R 9 E 2 2 2 5 R 9 E 3 2 2 5 R 9 E 4 2 2 5 R 9 E 5 2 2 5 R 8 E 6 2 2 5 R
H G I H _ L E N A P
H G I H _ L E N A P
H G I H _ L E N A P
- 1 O X R - 0 O X R
- 2 O X R
+ 3 E X R
+ 2 E X R + C E X R
+ C O X R
+ 0 O X R + 1 O X R + 2 O X R
+ 3 O X R + 0 E X R + 1 E X R
- 3 E X R
- 1 E X R
- 3 O X R - C O X R
- C E X R - 2 E X R
- 0 E X R
C D O
H G I H _ L E N A P
H G I H _ L E N A P
C D O
H G I H _ L E N A P
H G I H _ L E N A P
- 4 O X R + 4 O X R
- 3 O X R + 3 O X R
- 3 E X R + 3 E X R - 4 E X R + 4 E X R
+ C O X R - C O X R
- C E X R + C E X R
- 0 O X R + 0 O X R - 1 O X R + 1 O X R - 2 O X R + 2 O X R
- 1 E X R
- 0 E X R + 0 E X R
- 2 E X R + 2 E X R
+ 1 E X R
3 1 - 0 O X R
3 1 + 2 O X R
3 1 + 1 O X R
3 1 - 2 O X R
3 1 - 1 O X R
3 1 + 3 O X R 3 1 - 3 O X R
3 1 - C O X R 3 1 + C O X R
3 1 + 0 O X R
3 1 L E S D O
3 1 + 3 E X R 3 1 - 3 E X R 3 1 + C E X R 3 1 - C E X R
3 1 + 1 E X R 3 1 - 1 E X R
3 1 + 0 E X R 3 1 - 0 E X R
3 1 + 2 E X R 3 1 - 2 E X R
3 1 - 0 O X R
3 1 + 2 O X R
3 1 + 1 O X R 3 1 - 2 O X R
3 1 - 1 O X R
3 1 + 3 O X R 3 1 - 3 O X R
3 1 - C O X R 3 1 + C O X R
3 1 + 0 O X R
3 1 L E S D O
3 1 + 3 O X R 3 1 - 3 O X R
3 1 - 4 O X R 3 1 + 4 O X R
3 1 + 3 E X R 3 1 - 3 E X R
3 1 + 4 E X R 3 1 - 4 E X R
3 1 - C O X R 3 1 + C O X R
3 1 + C E X R 3 1 - C E X R
3 1 + 2 O X R 3 1 - 2 O X R 3 1 + 1 O X R 3 1 - 1 O X R 3 1 + 0 O X R 3 1 - 0 O X R
3 1 + 1 E X R 3 1 - 1 E X R 3 1 + 0 E X R 3 1 - 0 E X R
Circuit Diagrams and PWB Layouts EN 65TPM3.1E LA 10.
2009-Jun-26
SSB: iTV Interface and AOC Hotel1
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0 1
0 1
1 1
1 1
A A
B B
C C
D D
E E
F F
G G
H H
) 2 l e v e L V T i( F / I M E T S Y S D R A O B i-
L E T O H C O A
)2 leveL VTi( F/I NI OIDUA MOORHTAB
) 2 l e v e L V T i( D R A O B - i ) 2 l e v e L V T i( F / I K C O L C D C L
1 l e v e L V Ti r o f T R O P
7 A 1 0 3 5 N C 6 C 2 0 3 5 N C 4 C 3 0 3 5 N C 1 C 4 0 3 5 N C 7 D 5 0 3 5 N C 6 E 6 0 3 5 N C 6 F 7 0 3 5 N C
7 A 8 0 3 5 C 7 A 9 0 3 5 C 5 B 2 1 3 5 C 6 B 3 1 3 5 C 2 C 3 2 3 5 C 3 C 4 2 3 5 C 2 C 5 2 3 5 C 2 D 6 2 3 5 C 2 D 7 2 3 5 C 3 D 8 2 3 5 C 9 E 9 2 3 5 C 8 E 0 3 3 5 C 8 E 1 3 3 5 C 8 E 2 3 3 5 C 4 F 3 3 3 5 C 8 F 4 3 3 5 C 7 E 1 0 3 5 B F 3 C 2 0 3 5 B F 3 D 3 0 3 5 B F 3 E 3 0 3 5 Q 9 E 4 0 3 5 Q 9 F 5 0 3 5 Q 3 A 5 0 3 5 R 3 A 6 0 3 5 R 6 B 1 1 3 5 R 6 B 2 1 3 5 R 9 D 2 2 3 5 R 3 E 3 2 3 5 R 0 1 E 4 2 3 5 R
9 E 5 2 3 5 R 3 E 6 2 3 5 R 3 E 7 2 3 5 R 8 E 8 2 3 5 R
0 1 E 9 2 3 5 R 3 E 0 3 3 5 R 5 F 1 3 3 5 R 5 F 2 3 3 5 R 8 F 3 3 3 5 R 8 F 4 3 3 5 R
0 1 F 5 3 3 5 R 2 E 6 3 3 5 R 5 E 1 0 3 5 H T 4 F 1 0 3 5 D Z 4 F 2 0 3 5 D Z 5 F 3 0 3 5 D Z 5 F 4 0 3 5 D Z
T U O _ R I _ C R
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18400_529_090301.eps090919
iTV Interface and AOC Hotel
EN 66TPM3.1E LA 10.Circuit Diagrams and PWB Layouts
2009-Jun-26
SSB: Keyboard, IR & ComPair interface1
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A A
B B
C C
D D
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D R A O B y e K r o F F / I r i a Pm o C r o F
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4 A 1 0 4 5 N C 7 A 2 0 4 5 N C 6 C 3 0 4 5 N C 6 D 4 0 4 5 N C
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1 D X R _ T M 3 1 , 2 1
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Y B T S _ V 5 +
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18400_530_090301.eps090619
Keyboard, IR & ComPair interface
Circuit Diagrams and PWB Layouts EN 67TPM3.1E LA 10.
2009-Jun-26
SSB: Audio Switch1
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A A
B B
C C
D D
E E
4 L E S _ N I D U A 3 L E S _ N I D U A 2 L E S _ N I D U A 1 L E S _ N I D U A
N I _ U A _ C P
N I _ U A _ 1 P M O C
N I _ U A _ 2 P M O C
N I _ U A _ 2 T C S
N I _ U A _ 1 S B V C
N I _ U A _ E D I S
t u p n i o i d u A
0 1 1 1
1 x x 0
1 1 0 0
1 1 1 0
1 x x
1 1 1 1
0
2 A 2 0 1 6 C 4 A 1 0 1 6 C 2 A 4 0 1 6 C 2 A 3 0 1 6 C 2 A 6 0 1 6 C 7 A 5 0 1 6 C 2 B 8 0 1 6 C 2 A 7 0 1 6 C 2 B 0 1 1 6 C 2 B 9 0 1 6 C 5 A 3 1 1 6 C 5 A 2 1 1 6 C 5 B 6 1 1 6 C 5 A 4 1 1 6 C 5 B 8 1 1 6 C 5 B 7 1 1 6 C 6 C 1 2 1 6 C 2 C 9 1 1 6 C 2 C 3 2 1 6 C 6 C 2 2 1 6 C 7 B 5 2 1 6 C 7 B 4 2 1 6 C 5 C 2 0 1 6 Q 1 C 1 0 1 6 Q 5 C 5 0 1 6 Q 1 C 3 0 1 6 Q 7 A 2 0 1 6 R 4 A 1 0 1 6 R 7 A 4 0 1 6 R 4 A 3 0 1 6 R 7 B 2 1 1 6 R 7 B 1 1 1 6 R 2 A 4 1 1 6 R 3 A 3 1 1 6 R 2 A 8 1 1 6 R 3 A 5 1 1 6 R 2 A 0 2 1 6 R 2 A 9 1 1 6 R 6 A 2 2 1 6 R 6 A 1 2 1 6 R 1 C 5 2 1 6 R 6 A 3 2 1 6 R 1 C 7 2 1 6 R 5 C 6 2 1 6 R 2 A 9 2 1 6 R 5 C 8 2 1 6 R 2 B 1 3 1 6 R 2 B 0 3 1 6 R 6 B 4 3 1 6 R 2 B 2 3 1 6 R 6 B 6 3 1 6 R 6 B 5 3 1 6 R 8 B 8 3 1 6 R 8 B 7 3 1 6 R 6 B 2 0 1 6 U 3 B 1 0 1 6 U
2 L E S _ N I D U A 3 1
N I _ R U A _ 2 T C S 6
N I _ R U A _ S B V C _ E D I S 7
R _ X U M _ D U A
N I _ L U A _ S B V C _ E D I S 7
L _ X U M _ D U A
1 L E S _ N I D U A 3 1
N I _ L U A _ C P 4
N I _ R U A _ C P 4
N I _ L U A _ 2 T C S 6
N I _ L U A _ 2 P M O C 5
N I _ R U A _ 2 P M O C 5
4 L E S _ N I D U A 3 1
3 1 R _ D U A
3 1 L _ D U A
3 L E S _ N I D U A 3 1
N I _ R U A _ 1 P M O C 5
N I _ L U A _ 1 P M O C 5
L _ X U M _ D U A
R _ X U M _ D U A
N I _ R U A _ N I _ 1 S B V C 5
N I _ L U A _ N I _ 1 S B V C 5
N O _ V 5 +
N O _ V 5 +
N O _ V 5 +
N O _ V 5 +
N O _ V 5 +
N O _ V 5 +
N O _ V 5 +
N O _ V 5 +
% 5 W 6 1 / 1 K 0 7 4 4 1 1 6 R
1 0 1 6 R W 6 1 / 1 % 5 - + M H O K 2 . 2
3 V 6 F U 1 4 1 1 6 C
% 5 W 6 1 / 1 K 0 7 4 1 3 1 6 R
3 V 6 F U 1 3 1 1 6 C
3 V 6 F U 1 2 1 1 6 C
2 0 1 6 Q
G I T 1 1 2 2 N U M
2 2 1 6 C
V 6 1 N 0 0 1
3 V 6 F U 1 6 1 1 6 C
3 V 6 U 0 1 4 2 1 6 C
3 V 6 F U 1 8 1 1 6 C
% 5 W 6 1 / 1 K 0 7 4 2 2 1 6 R
% 5 W 6 1 / 1 K 0 7 4 0 2 1 6 R
% 5 W 6 1 / 1 K 0 7 4 5 3 1 6 R 3 V 6 F U 1 7 1 1 6 C
1 0 1 6 U D 2 5 0 4 C H 4 7
2 1 4 1 5 1 1 1
1 5 2 4
6
0 1 9
3 1
3
6 1
8
7
0 X 1 X 2 X 3 X
0 Y 1 Y 2 Y 3 Y
N E
A B
X
Y
D D V GN
D
E E V
3 V 6 F U 1 0 1 1 6 C
3 V 6 F U 1 9 0 1 6 C
W 6 1 / 1 % 5 - + M H O K 0 1 8 2 1 6 R
3 V 6 F U 1 8 0 1 6 C
3 V 6 U 0 1 5 2 1 6 C
3 V 6 F U 1 7 0 1 6 C
3 2 1 6 C
V 6 1 N 0 0 1
3 V 6 F U 1 6 0 1 6 C
3 V 6 F U 1 4 0 1 6 C
3 V 6 F U 1 3 0 1 6 C
8 3 1 6 R W 6 1 / 1 M H O K 0 2
W 6 1 / 1 % 5 - + M H O K 0 1 5 2 1 6 R
5 0 1 6 Q
G I T 1 1 2 2 N U M
% 5 W 6 1 / 1 K 0 7 4 1 2 1 6 R
% 5 W 6 1 / 1 K 0 7 4 9 1 1 6 R
% 5 W 6 1 / 1 K 0 7 4 0 3 1 6 R
2 0 1 6 R W 6 1 / 1 % 5 - + M H O K 2 . 2
3 1 1 6 R % 5 W 6 1 / 1 K 0 7 4 1 1 1 6 R
% 5 W 6 1 / 1 K 0 7 4
3 0 1 6 R
W 6 1 / 1 % 5 - + M H O K 2 . 2
3 V 6 F U 1 2 0 1 6 C
9 1 1 6 C
V 0 1 U 2 2
% 5 W 6 1 / 1 K 0 7 4 2 3 1 6 R
5 1 1 6 R % 5 W 6 1 / 1 K 0 7 4
4 0 1 6 R W 6 1 / 1 % 5 - + M H O K 2 . 2
W 6 1 / 1 % 5 - + M H O K 0 1 6 2 1 6 R
2 0 1 6 U D 2 5 0 4 C H 4 7
2 1 4 1 5 1 1 1
1 5 2 4
6
0 1 9
3 1
3
6 1
8
7
0 X 1 X 2 X 3 X
0 Y 1 Y 2 Y 3 Y
N E
A B
X
Y
D D V GN
D
E E V
7 3 1 6 R W 6 1 / 1 M H O K 0 2
W 6 1 / 1 % 5 - + M H O K 0 1 7 2 1 6 R
% 5 W 6 1 / 1 K 0 7 4 4 3 1 6 R
1 2 1 6 C
V 0 1 U 2 2
% 5 W 6 1 / 1 K 0 7 4 6 3 1 6 R
2 1 1 6 R % 5 W 6 1 / 1 K 0 7 4
1 0 1 6 Q
G I T 1 1 2 2 N U M
1 0 1 6 C
3 V 6 F U 1 5 0 1 6 C
3 V 6 F U 1
% 5 W 6 1 / 1 K 0 7 4 8 1 1 6 R
% 5 W 6 1 / 1 K 0 7 4 3 2 1 6 R
% 5 W 6 1 / 1 K 0 7 4 9 2 1 6 R
3 0 1 6 Q
G I T 1 1 2 2 N U M
B15 B15
18400_531_090301.eps090619
Audio Switch
EN 68TPM3.1E LA 10.Circuit Diagrams and PWB Layouts
2009-Jun-26
SSB: Audio Preamplifier1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
E E
3 A 1 0 2 6 C 6 B 3 0 2 6 C 4 B 4 0 2 6 C 5 C 5 0 2 6 C 4 C 6 0 2 6 C 2 C 7 0 2 6 C 4 D 8 0 2 6 C 5 C 9 0 2 6 C 3 C 0 1 2 6 C 3 D 1 1 2 6 C 4 D 2 1 2 6 C 4 D 3 1 2 6 C 2 A 4 1 2 6 C 2 D 5 1 2 6 C 5 B 1 0 2 6 D 5 B 2 0 2 6 D 2 A 1 0 2 6 B F 4 B 1 0 2 6 Q 6 B 2 0 2 6 Q 4 A 2 0 2 6 R 4 A 3 0 2 6 R 5 B 4 0 2 6 R 4 B 5 0 2 6 R 5 A 7 0 2 6 R 2 C 9 0 2 6 R 2 C 0 1 2 6 R 6 C 1 1 2 6 R 2 D 2 1 2 6 R 4 D 3 1 2 6 R 6 C 4 1 2 6 R 4 E 5 1 2 6 R 6 A 6 1 2 6 R 3 C 7 1 2 6 R 3 D 8 1 2 6 R 2 A 1 0 2 6 U 4 C 2 0 2 6 U 4 B 1 0 2 6 D Z
E T U M _ P O P
R O A _ N I A M 3 1
L O A _ N I A M 3 1
0 2 T U O L _ D U A
0 2 T U O R _ D U A
7 T U O L _ P H
7 T U O R _ P H
E T U M _ P O 3 1 3 1 , 8 E T U M _ P O P
N O _ V 5 +
V 5 _ S P O
V 5 _ S P O W S _ V 4 2 +
1 1 2 6 C V 0 5 8 N 1
W 6 1 / 1 % 5 - + M H O K 0 3 5 1 2 6 R
V 0 5 P 0 8 1 2 1 2 6 C
2 0 2 6 Q C 7 4 8 C B
9 0 2 6 C
V 5 2 U 1
0 1 2 6 C V 0 5 8 N 1
5 0 2 6 C
V 0 1 U 0 1
1 0 2 6 U R T - U C A 5 0 L 8 7 L
3 1
2
T U O N I
GN
D
8 4 1 4 S L 1 0 2 6 D
6 0 2 6 C 3 V 6 F U 1
3 V 6 F U 1 7 0 2 6 C
8 4 1 4 S L 2 0 2 6 D
3 0 2 6 R % 5 W 0 1 / 1 8 K 1
0 1 2 6 R W 6 1 / 1 % 5 - + M H O K 0 1
5 0 2 6 R % 5 W 0 1 / 1 R 0 7 4
3 0 2 6 C
) C N ( N 0 0 1
2 0 2 6 R % 5 W 0 1 / 1 R 0 0 1
1 0 2 6 B F
A m 0 0 0 3 / R 0 2 1 1 2
% 5 W 0 1 / 1 R 0 1 4 1 2 6 R
1 0 2 6 Q C 7 4 8 C B
V 0 5 P 0 8 1 3 1 2 6 C
6 1 2 6 R W 6 1 / 1 % 5 - + M H O K 0 1
4 0 2 6 C
V 0 1 U 0 1
1 0 2 6 D Z 6 V 3 C 4 8 X Z B
1 3
4 1 2 6 C
V 0 1 U 0 1
W 6 1 / 1 % 5 - + M H O K 0 3 3 1 2 6 R
7 1 2 6 R W 6 1 / 1 % 5 - + M H O K 0 1
4 0 2 6 R % 5 W 0 1 / 1 R 0 0 1
7 0 2 6 R % 5 W 0 1 / 1 8 K 1
2 0 2 6 U + C T E A 8 2 7 9 X A M
4
3
1 1
9 1
7
0 1
5
2 8
2 1
6
s s V P
C1N
L T U O
SV
ssC
1P
SG
ND
R T U O
N D H S
PG
ND
IN
R
D D V
L _ N I
8 0 2 6 C 3 V 6 F U 1
3 V 6 F U 1 5 1 2 6 C
+ 1 0 2 6 C V 0 1 F U 0 7 4
2 1 2 6 R W 6 1 / 1 % 5 - + M H O K 0 1
% 5 W 0 1 / 1 R 0 1 9 0 2 6 R
% 5 W 0 1 / 1 R 0 1 1 1 2 6 R
8 1 2 6 R W 6 1 / 1 % 5 - + M H O K 0 1
B16 B16
18400_532_090301.eps090619
Audio Preamplifier
Circuit Diagrams and PWB Layouts EN 69TPM3.1E LA 10.
2009-Jun-26
SSB: Audio Amplifier1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
E E
Subwoofer
7 C 1 0 3 6 N C 3 D 2 0 3 6 N C
4 A 1 0 3 6 C 5 A 2 0 3 6 C 5 A 3 0 3 6 C 4 C 4 0 3 6 C 4 C 5 0 3 6 C 2 D 6 0 3 6 C 4 C 7 0 3 6 C 6 B 8 0 3 6 C 6 C 9 0 3 6 C 5 C 0 1 3 6 C 6 C 1 1 3 6 C 5 C 2 1 3 6 C 3 C 3 1 3 6 C 3 C 4 1 3 6 C 5 D 5 1 3 6 C 3 D 6 1 3 6 C 3 D 7 1 3 6 C 6 D 8 1 3 6 C 6 D 9 1 3 6 C 2 B 0 2 3 6 C 2 D 1 2 3 6 C 3 C 3 0 2 6 D 5 A 1 0 3 6 D 4 A 1 0 3 6 B F 3 B 3 0 3 6 B F
5 B 1 0 3 6 L 5 D 2 0 3 6 L 4 A 1 0 3 6 Q 3 A 2 0 3 6 Q 3 B 3 0 3 6 Q 3 C 4 0 3 6 Q 2 C 6 0 3 6 Q 4 A 1 0 3 6 R 4 A 2 0 3 6 R 3 A 3 0 3 6 R 4 A 4 0 3 6 R 5 A 5 0 3 6 R 5 C 6 0 3 6 R 6 C 7 0 3 6 R 3 C 2 1 3 6 R 2 C 3 1 3 6 R 2 C 4 1 3 6 R 2 C 5 1 3 6 R 2 C 6 1 3 6 R 6 D 7 1 3 6 R 6 C 8 1 3 6 R 6 C 9 1 3 6 R 6 D 0 2 3 6 R 5 D 1 2 3 6 R 6 D 2 2 3 6 R 2 C 3 2 3 6 R 3 C 4 2 3 6 R 3 C 5 2 3 6 R 4 C 1 0 3 6 U 2 C 2 0 3 6 D Z
+ T U O L
+ T U O R
3 1 0 N I A G _ P M A 3 1 1 N I A G _ P M A
E T U M _ P M A 3 1
W S _ R W P _ D U A 3 1 , 2 1
T U O L _ D U A 9 1 T U O R _ D U A 9 1
N E _ P M A 3 1
P M A _ V 4 2 +
P M A _ V 4 2 +
W S _ V 4 2 +
V 4 2 +
3 V 3 +
W S _ V 4 2 +
N O _ V 5 +
3 V 3 +
2 0 3 6 C V 0 5 N 0 0 1
7 1 3 6 C V 5 2 U 1
2 0 3 6 R ) C N ( % 5 W 6 1 / 1 K 0 7 4
+ 7 0 3 6 C
V 5 3 F u 0 7 4
1 0 3 6 Q
) C N ( Y D D 5 3 8 4 I S
2 3 4 5
7 6
8 1
R63
200R
(NC
)
3 0 3 6 B F A m 0 0 0 6 / R 0 2 1
1 2
2 0 3 6 D Z 0 2 C - 4 8 X Z B
1 3
R63
170R
(NC
)
2 0 3 6 L H u 5 3
6 0 3 6 Q C 7 4 8 C B
1 0 3 6 D
D 3 S
4 0 3 6 Q C 7 4 8 C B
7 0 3 6 R % 5 W 4 / 1 2 K 2
+ 0 2 3 6 C
V 5 3 F u 0 7 4
% 5 W 6 1 / 1 R 0 1 3 1 3 6 R
6 0 3 6 R % 5 W 4 / 1 2 K 2
1 0 3 6 R ) C N ( % 5 W 0 1 / 1 K 6 5
3 0 3 6 Q ) C N ( G I T 1 1 2 2 N U M
+
8 1 3 6 C V 5 2 F u 0 7 4
% 5 W 6 1 / 1 R 0 1 4 2 3 6 R
5 1 3 6 R % 5 W 0 1 / 1 R 0 7 4
6 1 3 6 C V 5 2 U 1
V 5 2 U 1 3 1 3 6 C
5 1 3 6 C V 5 2 N 0 2 2
2 2 3 6 R % 5 W 4 / 1 2 K 2
2 0 3 6 N C
) C N ( N N O C
1 2 3
+ 3 0 3 6 C
V 0 5 / F U 0 1
5 2 3 6 R % 5 W 0 1 / 1 8 K 1
3 0 3 6 R ) C N ( % 5 W 0 1 / 1 K 7 4
5 0 3 6 C V 0 5 N 0 0 1
1 0 3 6 L H u 5 3
1 0 3 6 U R P W P 2 D 3 2 1 3 A P T
1 2 3
5 6
4
7 8 9 0 1 1 1 2 1
4 2 3 2 2 2 1 2 0 2 9 1 8 1
6 1 7 1
5 1 4 1 3 1
25
L C C V P D S
L C C V P
N I L N I R
E T U M
S S A P Y B D N G A D N G A
R C C V P P M A L C V
R C C V P
L D N G P L D N G P T U O L L S B C C V A C C V A 0 N I A G
R S B 1 N I A G
T U O R R D N G P R D N G P T
H1
V 5 2 U 1 4 1 3 6 C 1 0 3 6 N C
N N O C
1 2 3 4
9 0 3 6 C V 0 5 N 0 7 4
5 0 3 6 R ) C N ( % 5 W 6 1 / 1 K 0 1
6 0 3 6 C
V 0 5 P 0 0 1
+
8 0 3 6 C V 5 2 F u 0 7 4
4 0 3 6 C V 0 5 N 0 0 1 3 0 2 6 D
8 4 1 4 S L
R63
18
10K
(NC
)
6 1 3 6 R % 5 W 0 1 / 1 K 7 4
2 0 3 6 Q ) C N ( G I T 1 1 2 2 N U M
2 1 3 6 R % 5 W 6 1 / 1 R 0 1
4 0 3 6 R ) C N ( % 5 W 0 1 / 1 K 8 1
0 1 3 6 C V 6 1 N 0 0 1
% 5 W 6 1 / 1 R 0 1 4 1 3 6 R
1 0 3 6 C ) C N ( V 0 5 N 0 7 4
9 1 3 6 C V 0 5 N 0 7 4
2 1 3 6 C V 5 2 N 0 2 2
1 2 3 6 C
V 0 5 P 0 0 1
+
1 1 3 6 C ) C N ( V 0 5 / F U 0 1
1 2 3 6 R % 5 W 4 / 1 2 K 2
R63
19
10K
(NC
)
3 2 3 6 R % 5 W 0 1 / 1 R 0 3 3
1 0 3 6 B F
A m 0 0 0 6 / R 0 2 1 1 2
B17 B17
18400_533_090301.eps090619
Audio Amplifier
EN 70TPM3.1E LA 10.Circuit Diagrams and PWB Layouts
2009-Jun-26
SSB: DC-DC Power1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
0 1
0 1
1 1
1 1
A A
B B
C C
D D
E E
F F
G G
H H
DC-DC Power
1 A 2 0 1 7 N C 2 A 1 0 1 7 N C 2 A 2 0 1 7 C 1 A 1 0 1 7 C 5 A 4 0 1 7 C 5 A 3 0 1 7 C 7 A 6 0 1 7 C 6 A 5 0 1 7 C 3 B 8 0 1 7 C 3 B 7 0 1 7 C 3 B 0 1 1 7 C 0 1 B 9 0 1 7 C
4 B 2 1 1 7 C 9 B 1 1 1 7 C 3 C 5 1 1 7 C 4 B 3 1 1 7 C 7 C 8 1 1 7 C 6 C 7 1 1 7 C 6 C 0 2 1 7 C 8 C 9 1 1 7 C 1 C 3 2 1 7 C 9 C 1 2 1 7 C 3 C 5 2 1 7 C 1 C 4 2 1 7 C 4 D 7 2 1 7 C 3 D 6 2 1 7 C 3 D 9 2 1 7 C 4 C 8 2 1 7 C 6 D 8 3 1 7 C 3 E 7 3 1 7 C 6 D 0 4 1 7 C 8 D 9 3 1 7 C 3 C 2 4 1 7 C 7 D 1 4 1 7 C 9 C 4 4 1 7 C 6 E 3 4 1 7 C 9 E 7 4 1 7 C 9 E 6 4 1 7 C 6 C 2 5 1 7 C 2 F 9 4 1 7 C 7 F 4 5 1 7 C 1 F 3 5 1 7 C 8 F 6 5 1 7 C 7 F 5 5 1 7 C 5 F 8 5 1 7 C 9 F 7 5 1 7 C 2 F 0 6 1 7 C 4 F 9 5 1 7 C
5 A 2 0 1 7 B F 2 B 1 0 1 7 B F 9 A 4 0 1 7 B F 8 A 3 0 1 7 B F 3 B 6 0 1 7 B F 0 1 B 5 0 1 7 B F
6 B 8 0 1 7 B F 2 B 7 0 1 7 B F 7 E 1 1 1 7 B F 9 C 9 0 1 7 B F 4 E 3 1 1 7 B F 4 D 2 1 1 7 B F 9 D 5 1 1 7 B F 5 D 4 1 1 7 B F
3 C 1 0 1 7 L 1 F 6 1 1 7 B F 8 D 4 0 1 7 L 8 C 2 0 1 7 L 9 A 2 0 1 7 Q 3 A 1 0 1 7 Q 6 C 4 0 1 7 Q 8 B 3 0 1 7 Q 3 E 6 0 1 7 Q 6 C 5 0 1 7 Q 2 E 8 0 1 7 Q 2 E 7 0 1 7 Q 3 A 3 0 1 7 R 1 A 2 0 1 7 R 8 A 5 0 1 7 R 3 A 4 0 1 7 R 6 B 7 0 1 7 R 8 B 6 0 1 7 R 9 B 9 0 1 7 R 6 B 8 0 1 7 R 6 C 2 1 1 7 R 8 C 1 1 1 7 R 7 C 4 1 1 7 R 7 C 3 1 1 7 R 0 1 C 6 1 1 7 R 6 C 5 1 1 7 R
7 C 8 1 1 7 R 4 C 7 1 1 7 R 3 D 0 2 1 7 R 3 C 9 1 1 7 R 3 D 5 2 1 7 R 3 A 1 2 1 7 R 2 E 9 2 1 7 R 2 D 6 2 1 7 R 4 E 1 3 1 7 R 3 E 0 3 1 7 R 6 D 3 3 1 7 R 6 D 2 3 1 7 R 8 D 5 3 1 7 R 7 D 4 3 1 7 R 0 1 E 8 3 1 7 R 7 E 7 3 1 7 R
2 F 0 4 1 7 R 2 F 9 3 1 7 R 4 F 2 4 1 7 R 4 F 1 4 1 7 R 3 A 5 4 1 7 R 2 F 4 4 1 7 R 2 C 1 0 1 7 U 3 A 6 4 1 7 R 8 C 3 0 1 7 U 6 A 2 0 1 7 U 8 D 5 0 1 7 U 8 E 4 0 1 7 U 8 C 1 0 1 7 D Z 3 F 6 0 1 7 U 3 E 4 0 1 7 D Z 8 E 3 0 1 7 D Z
8 B 5 0 1 7 D Z
3 1 , 2 1 Y B D N A T S
L T C _ R W P _ L E N A P 3 1
W S _ R W P _ V 5 3 1 , 2 1
L T C _ R W P _ L E N A P 3 1
3 1 M W P _ S S E N T H G I R B
3 1 F F O _ N O _ R E T R E V N I
3 1 M W P _ S S E N T H G I R B
V 4 2 +
V 2 1 +
V R D D
0 1 V D
V 5 +
Y B T S _ V 5 +
N O _ V 5 +
V 5 + Y B T S _ V 5 +
N O _ V 5 +
C C V _ L E N A P
V 2 1 +
Y B T S _ 3 V 3 +
Y B T S _ 3 V 3 + Y B T S _ V 5 +
V 2 1 +
C C V _ L E N A P
Y B T S _ V 5 +
3 V 3 +
3 V 3 +
2 1 V A 3 V 3 +
N O _ V 5 +
V 5 +
3 V 3 +
Y B T S _ V 5 +
0 2 1 7 C
) C N ( N 0 0 1
6 0 1 7 B F
A m 0 0 0 6 / R 0 2 1 1 2
2 0 1 7 Q
Y D D 5 3 8 4 I S
2 3 4 5
7 6
8 1
9 0 1 7 C V 0 5 N 0 0 1
+ 8 5 1 7 C
V 5 2 F u 7 4
4 0 1 7 B F ) C N ( R 0 2 1
1 2
9 4 1 7 C V 6 1 N 0 0 1
9 0 1 7 B F
) C N ( R 0 2 1 1 2
+ 7 4 1 7 C V 0 1 F u 0 7 4
3 4 1 7 C
V 0 5 N 0 0 1
5 3 1 7 R % 5 W 0 1 / 1 1 K 5
1 1 1 7 B F
A m 0 0 0 6 / R 0 2 1 1 2
6 2 1 7 R % 5 W 0 1 / 1 K 1
8 1 1 7 C
) C N ( N 0 0 1
+ 2 4 1 7 C V 0 1 F U 0 7 4
1 0 1 7 Q
C 7 4 8 C B
0 3 1 7 R % 5 W 0 1 / 1 K 0 0 1
% 5 W 0 1 / 1 K 0 1 4 4 1 7 R
2 1 1 7 B F A m 0 0 0 6 / R 0 2 1
1 2
+ 8 3 1 7 C
V 0 1 F U 0 7 4
1 4 1 7 C
V 0 5 N 0 0 1
9 3 1 7 C V 0 5 N 0 0 1
7 3 1 7 C V 0 1 N 0 7 4
3 0 1 7 R % 5 W 0 1 / 1 K 7 4
1 0 1 7 N C
N N O C
1 2 3 4 5 6 7 8 9
0 1 1 1 2 1
5 2 1 7 C
) C N ( P 3 3
2 1 1 7 R ) C N ( K 0 0 1
4 1 1 7 B F
A m 0 0 0 6 / R 0 2 1 1 2
3 0 1 7 D Z 4 3 A S S
1 2
+ 3 5 1 7 C
V 5 2 F u 7 4
1 2 1 7 R % 5 W 0 1 / 1 K 1
8 0 1 7 R % 1 W 0 1 / 1 R 0 1 1
+ 6 0 1 7 C
V 0 1 F U 0 7 4
3 0 1 7 U
) C N ( Z J D A A H I A 6 0 1 5 E M A
1 2 3 4 5
6 7 8 B F
N E T E S C O
W S N I W S D N G D N G
6 0 1 7 Q Y D D 5 3 8 4 I S
2 3 4 5
7 6
8 1
4 2 1 7 C
V 0 1 7 U 4
4 0 1 7 Q
) C N ( G I T 1 1 2 2 N U M
2 0 1 7 U Z S C C D 4 8 0 1 E M A
1
2 3
AD
J
t u o V n i V
6 0 1 7 U
U 1 1 F J D A 0 2 1 - 3 7 9 G
1 2 3 4
8 7 6 5
9
D N G J D A
O V O V
N E V K O P P P V
N I V TH
1
1 2 1 7 C ) C N ( N 0 0 1
1 1 1 7 R ) C N ( 1 K 5
) C N ( K 1 2 0 1 7 R
+ 2 5 1 7 C ) C N ( V 5 2 F u 7 4
3 0 1 7 B F A m 0 0 0 6 / R 0 2 1
1 2
2 3 1 7 R % 5 W 0 1 / 1 K 0 0 1
8 3 1 7 R % 1 W 0 1 / 1 5 K 1
6 5 1 7 C
V 0 5 N 0 0 1
7 2 1 7 C
V 6 1 N 0 0 1
9 1 1 7 R W 6 1 / 1 % 5 - + M H O 0
1 0 1 7 C ) C N ( 7 U 4
5 1 1 7 B F
A m 0 0 0 6 / R 0 2 1 1 2
2 1 1 7 C
V 0 5 N 0 0 1
9 2 1 7 R % 5 W 0 1 / 1 K 5 1
2 0 1 7 L ) C N ( H u 5 3
9 1 1 7 C ) C N ( N 0 0 1
1 0 1 7 B F
A m 0 0 0 6 / R 0 2 1
1 2
6 4 1 7 R % 5 W 0 1 / 1 K 2
6 1 1 7 B F
A m 0 0 0 6 / R 0 2 1 1 2
3 1 1 7 R
) C N ( K 3
0 6 1 7 C V 6 1 U 0 1
2 0 1 7 N C
) C N ( N N O C
1 2 3 4
5 0 1 7 U
Z J D A A H I A 6 0 1 5 E M A
1 2 3 4 5
6 7 8 B F
N E T E S C O
W S N I W S D N G D N G
+ 4 4 1 7 C ) C N ( V 0 1 F U 0 7 4
4 1 1 7 R ) C N ( % 1 W 0 1 / 1 K 2 1
7 0 1 7 Q
G I T 1 1 2 2 N U M
9 0 1 7 R % 5 W 0 1 / 1 K 0 1
+ 3 1 1 7 C
V 5 3 F u 0 7 4
0 1 1 7 C
V 0 5 N 0 0 1
8 1 1 7 R ) C N ( % 1 W 0 1 / 1 2 K 2
% 5 W 0 1 / 1 R 0 1 4 0 1 7 R
3 0 1 7 Q
G I T 1 1 2 2 N U M
6 1 1 7 R ) C N ( % 5 W 0 1 / 1 K 0 1
+
3 0 1 7 C V 0 1 F u 0 0 1
6 4 1 7 C V 0 5 N 0 0 1
7 1 1 7 R ) C N ( R 0
5 2 1 7 R ) C N ( W 4 / 1 R 0
1 3 1 7 R W 0 1 / 1 % 5 - + M H O K 0 1
4 5 1 7 C
V 0 5 N 0 0 1
+ 8 0 1 7 C
V 5 2 F u 0 7 4
4 0 1 7 L H u 5 3
5 0 1 7 Q ) C N ( G I T 1 1 2 2 N U M
3 1 1 7 B F
A m 0 0 0 6 / R 0 2 1 1 2
9 5 1 7 C V 6 1 N 0 0 1
8 0 1 7 B F
) C N ( A m 0 0 0 6 / R 0 2 1 1 2
7 0 1 7 R % 1 W 0 1 / 1 R 0 0 1
0 4 1 7 R W 0 1 / 1 % 5 - + M H O K 0 1
1 1 1 7 C V 0 5 N 0 0 1
+ 5 5 1 7 C
V 0 1 F u 0 0 1
3 3 1 7 R % 5 W 0 1 / 1 K 3
5 1 1 7 C V 0 5 N 0 0 1
1 0 1 7 U 4 G R V B D 3 0 2 2 6 S P T
1 2 3 4
5 N I D N G
B F N E
W S
+ 7 5 1 7 C
V 0 1 F u 0 0 1
7 3 1 7 R % 1 W 0 1 / 1 2 K 2
6 0 1 7 R % 5 W 0 1 / 1 K 0 0 1
1 0 1 7 D Z ) C N ( 4 3 A S S
1 2
1 4 1 7 R % 1 W 0 1 / 1 5 K 1
2 0 1 7 C V 0 5 N 0 0 1
5 0 1 7 D Z
) C N ( 4 5 T A B
1 3
1 0 1 7 L H u 5 3
5 0 1 7 R % 5 W 0 1 / 1 3 K 3
2 0 1 7 B F
A m 0 0 0 6 / R 0 2 1 1 2
6 2 1 7 C
V 0 1 U 0 1
5 0 1 7 C
V 0 5 N 0 0 1
4 3 1 7 R % 1 W 0 1 / 1 R 0 2 8
8 0 1 7 Q
G I T 1 1 2 2 N U M
% 5 W 0 1 / 1 K 0 1 9 3 1 7 R
+ 3 2 1 7 C
V 5 2 F u 7 4
4 0 1 7 U E 2 2 1 1 P A
1
3 2
4
GN
D
T U O N I
4
4 0 1 7 D Z
4 5 T A B
1 3
7 0 1 7 C ) C N ( 7 U 4
5 0 1 7 B F
A m 0 0 0 6 / R 0 2 1 1 2
7 1 1 7 C ) C N ( N 0 0 1
4 0 1 7 C
V 0 5 N 0 0 1
9 2 1 7 C V 0 5 P 0 8 1
7 0 1 7 B F A m 0 0 0 6 / R 0 2 1
1 2
5 1 1 7 R
) C N ( K 5 1
% 1 W 0 1 / 1 M H O 7 K 4 2 4 1 7 R
+ 8 2 1 7 C V 5 2 F u 7 4
5 4 1 7 R
% 5 W 0 1 / 1 R 0 7 4
0 2 1 7 R ) C N ( K 0 0 1
0 4 1 7 C V 0 5 N 0 0 1
B18 B18
18400_534_090301.eps090619
Circuit Diagrams and PWB Layouts EN 71TPM3.1E LA 10.
Circuit Diagrams and PWB Layouts EN 77TPM3.1E LA 10.
2009-Jun-26
SSB Layout: Part 1 Bottom side
18400_558a_090301.eps090619
EN 78TPM3.1E LA 10.Circuit Diagrams and PWB Layouts
2009-Jun-26
SSB Layout: Part 2 Bottom side
18400_558b_090301.eps090619
Circuit Diagrams and PWB Layouts EN 79TPM3.1E LA 10.
2009-Jun-26
SSB Layout: Part 3 Bottom side
18400_558c_090301.eps090619
EN 80TPM3.1E LA 10.Circuit Diagrams and PWB Layouts
2009-Jun-26
SSB Layout: Part 4 Bottom side
18400_558d_090301.eps090619
Circuit Diagrams and PWB Layouts EN 81TPM3.1E LA 10.
2009-Jun-26
IR Board1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
E E
W R
N O _ C D
F F O _ C D
Y B T S _ C C V
V 5
V 7 . 3
1 C 1 0 2 0 N C 1 C 2 0 2 0 N C
2 B 1 0 2 0 C 5 B 2 0 2 0 C 2 C 3 0 2 0 C 2 C 4 0 2 0 C 3 C 5 0 2 0 C 3 C 6 0 2 0 C 2 B 1 0 2 0 B F 2 B 2 0 2 0 B F 2 B 3 0 2 0 B F 2 C 4 0 2 0 B F 2 C 5 0 2 0 B F 3 A 1 0 2 0 D E
2 A 1 0 2 0 Q 3 B 2 0 2 0 Q 3 B 3 0 2 0 Q 2 A 4 0 2 0 Q 3 A 1 0 2 0 R 3 A 2 0 2 0 R 2 B 3 0 2 0 R 3 B 4 0 2 0 R 3 B 5 0 2 0 R 4 B 6 0 2 0 R 4 B 7 0 2 0 R 4 B 8 0 2 0 R 5 B 9 0 2 0 R 2 A 0 1 2 0 R 2 A 1 1 2 0 R 5 B 1 0 2 0 U 5 C 1 0 2 0 D Z
Y B T S _ 2 D E L
N O _ D E L
R O S N E S _ T H G I L
L T C _ R O S N E S _ T H G I L
L T C _ R O S N E S _ T H G I L
Y B T S _ C C V
Y B T S _ C C V
D N G _ I M E
Y B T S _ C C V Y B T S _ C C V
7 0 2 0 R % 5 W 6 1 / 1 7 K 4
4 0 2 0 R % 5 W 6 1 / 1 7 K 4
1 0 2 0 D Z 1 V 5 C - 4 8 X Z B
1 3
1 0 2 0 Q 1 0 X 0 0 0 6 T M E T
1 3
2
2 0 2 0 B F A m 0 0 2 / R 0 0 6
1 2
3 0 2 0 B F A m 0 0 2 / R 0 0 6
1 2
4 0 2 0 B F A m 0 0 2 / R 0 0 6
1 2
5 0 2 0 B F A m 0 0 2 / R 0 0 6
1 2
2 0 2 0 N C K - 2 0 S - B V S 7 0 - 5 1 3 1 S
1 2 3 4
9 8
5 6 7
9 0 2 0 R % 5 W 6 1 / 1 R 0 2 2
3 0 2 0 R % 5 W 6 1 / 1 M H O K 0 0 2
2 0 2 0 Q C 7 4 8 C B
4 0 2 0 Q C 7 5 8 C B
1 0 2 0 D E L F A W P K R U S 5 2 0 3 - B P K
1 3
2 4
6 0 2 0 C V 0 5 P 0 0 1
0 1 2 0 R % 5 W 6 1 / 1 K 3 3
2 0 2 0 C V 0 1 F U 1
2 0 2 0 R % 5 W 6 1 / 1 5 K 1
1 0 2 0 B F A m 0 0 2 / R 0 0 6
1 2
1 0 2 0 C V 0 1 F U 1
1 0 2 0 R % 5 W 6 1 / 1 5 K 1
8 0 2 0 R
% 5 W 6 1 / 1 M H O 7 K 2
5 0 2 0 C V 6 1 N 0 0 1
4 0 2 0 C V 6 1 N 0 0 1
3 0 2 0 C V 6 1 N 0 0 1
1 1 2 0 R % 5 W 6 1 / 1 K 8 1
1 0 2 0 U
1 B S 6 3 3 4 3 P O S T
3
1
2
S V
T U O
D N G
6 0 2 0 R % 5 W 6 1 / 1 K 0 1
1 0 2 0 N C K - 1 0 S - B V R 7 0 - 5 1 3 1 S
1 2 3 4
9 8
5 6 7
5 0 2 0 R % 5 W 6 1 / 1 K 0 1
3 0 2 0 Q C 7 4 8 C B
JJ
18400_515_090301.eps090619
IR Board
EN 82TPM3.1E LA 10.Circuit Diagrams and PWB Layouts