Phase Locked Loop - Python Power Electronics...Phase Locked Loop Shivkumar .V. Iyer 1 Abstract Any grid connected inverter requires accurate information of the phase angle and frequency

Phase Locked Loop

Shivkumar .V. Iyer

1 Abstract

Any grid connected inverter requires accurate information of the phase angle and frequency of the

grid through a Phase Locked Loop (PLL). The report will describe through simulations, every aspect

of the implementation of a PLL in software which in hardware would be through a Digital Signal

Processor (DSP) or an equivalent embedded processor. The outline of the report is as follows:

1. The need for a PLL and the basic concept behind a software PLL.

2. The concept of transformation that forms the basis of a software PLL with a single-phase sys-

tem.

3. The closed loop to generate the synchronization.

4. Transformation applied to a three-phase system.

5. The effect of unbalance with respect to oscillations in the phase angle and the need for a notch

filter.

6. The design of a notch filter.

7. The working of a PLL in practical conditions.

This tutorial is accompanied by a number of simulation cases. It is recommended to try out the

simulation cases while reading the tutorial.

About the software: Python Power Electronics is a free and open source circuit simulator for

power electronics and power systems professionals. It is available under the BSD 3.0 license agree-

ment which is available with this tutorial and in every case as a LICENSE.txt file. Users of this

tutorial are advised to read the license file. It should be noted that this tutorial is for learning and edu-

cational purposes. Implementation of the examples cited in this tutorial directly in a prototype cannot

1

be guaranteed to work and the readers are responsible for taking precautions to prevent damage to

their equipments and injury to themselves. For any queries, feel free to contact me at pythonpower-

[email protected] or visit the project website http://www.pythonpowerelectronics.com/.

The purpose of this tutorial and others that will be released is to provide education through simu-

lation to engineers on several aspects of power systems. Starting from simple concepts, the tutorials

will progress to advanced control in power systems and understanding practical problems in present

day electrical systems. The tutorials are not mathematically intense and this is intentional as the ob-

jective is to help engineers who are busy with their day jobs to advance their knowledge. The reports

are written with figures and visuals as far as possible to make understanding easier. The report in its

style is similar to a presentation where each page has a figure and a description accompanying it. This

is to facilitate easier reading as opposed to an academic paper. Readers are encouraged to follow the

project on the website, social media and go through the examples and documents provided.

2

Grid

f1f2

vg vc

PLL

PLL

θ

θθvg/20

Voltage

Figure 1: Phase synchronization with a grid

2 The need for a PLL

The above figure shows a power electronic converter connected to an ac grid. At present, the topology

of the converter and the nature of the coupling is not relevant. In order to function, the converter

needs the accurate information of the frequency f1 and the phase angle information (θ ) of the grid

from which it can regulate its own output frequency f2 to be equal to f1 and its phase angle to be in

sync with the grid phase angle. The desired output of the PLL is therefore the phase angle information

of the grid which is then used to regulate the output of the converter. The reason why this is essential

is that the grid frequency is likely to drift from its nominal value by around 1% under even normal

operating conditions. This is because the frequency of the grid is related to the state of loading of a

power system - power generated versus power demanded. During peak load demand, the frequency

tends to drop below nominal while during light load periods, the frequency could be closely regulated

to the nominal value. For all these frequency drifts, the PLL should continue to generate the accurate

phase angle information of the grid so that the converter output voltage phase angle remains in sync

with the changing grid. The next figure shows what happens if converter frequency is not equal to

grid frequency.

3

Figure 2: Operation with and without a PLL

The figure above shows the difference between the operation when the converter frequency is

exactly the same as the grid frequency (both are 60 Hz) and when the converter frequency is 60.5 Hz.

This can be found in the spreadsheet need for pll.csv and the associated control file vconv openloop

.py. The parameters of the circuit is in the spreadsheet need for pll params.csv while the variables for

the control file can be found in vconv openloop desc.csv. You can change the frequency of either the

grid in the circuit parameters section or the converter in the file vconv openloop.py . In the first case,

when frequencies are equal, a stable operation is observed. In the second case, the current has a low

frequency envelope besides very high peaks. Typically, when two voltage with different frequencies

f1 and f2 are connected together, the current that flows through them will have two componentsf 1+ f 2

2

andf 1− f 2

2. The second component results in a low frequency envelope. Quite obviously, the second

case is not a permissible mode of operation. To explain this in simple terms, if two objects were to

have different speeds, with time the distance between them would be huge. If two sinusoids were to

have different frequencies, at some point of time, they would be out of phase with each other and at

another point of time, they would be exactly in phase with each other.

4

Reference

V , t1

V , t2

Vm cos(ωt1)Vm cos(ωt2)

ω

Vm

Figure 3: A sinsuoid in a stationary reference frame

3 Concept of phasors and reference frames

In order to explain what a PLL is, let us first examine the concept of phasors, transformations and ref-

erence frames. The above figure shows a co-sinusoid of frequency ω and magnitude Vm. To represent

this as a phasor, examine the figure on the right. The co-sinusoid is a vector of magnitude Vm rotating

at an angular frequency ω . The instantaneous value of the co-sinusoid is the projection of the vector

on the x-axis which is the reference frame. At different points of time, the vector will occupy different

positions in the two-dimensional plane as shown at time t1 and t2. The projection on the x-axis will

result in different instantaneous values which as can be seen are Vm cos(ωt1) and Vm cos(ωt2). As

expected from a co-sinousoid of magnitude Vm, the instantaneous value from the projection is also

restricted between −Vm and +Vm. In this manner, a voltage can be represented in the above manner in

which it is called a phasor (similar to vector). The phasor has two properties - magnitude and angular

frequency of rotation. In the above figure, the reference frame is the x-axis and is stationary. With

respect to this stationary axis, the phasor V is rotating with an angular frequency ω . In simple terms,

this is similar to standing on a platform watching a train go by without stopping. You see all the

compartments of the train with their passengers one after the other until the train is gone.

5

Reference Reference

Reference

Reference

V , t1V , t1

V , t2V , t2

ω

ω

ω

ω

ω

ω

ωr

ωr

φ1φ1φ1

φ2

Figure 4: A sinsuoid in a rotating reference frame

Let us now examine the concept of a rotating reference frame rather than the stationary x-axis

reference frame. In the above figure, the first case is of a reference frame rotating at an angular

frequency of ωr which is different from the angular frequency of rotation of the voltage phasor. With

respect to this rotating reference frame, the instantaneous value of the voltage is Vm cos(ω −ωr)t. Two

instances have been shown at time t1 and t2. Since ωr and ω are different, at different times, the phase

angle difference between them may be different as shown to be φ1 and φ2. With respect to this rotating

reference frame, the voltage vector now appears to be a low frequency co-sinusoid. This is seen as

similar to sitting in a moving train and watching a faster train go by in the same direction. The faster

train will appear to be a slow moving train just because you are sitting in a train that is almost as fast.

On the right is shown a special case of the rotating reference frame - the angular frequency of the

reference frame is the same as that of the voltage vector (ω). The result is that they always maintain

the same phase angle difference φ1 between them at all time instants. And therefore, the instantaneous

value of the voltage with respect to this reference frame is Vm cosφ1. In this special case, with respect

to the reference frame rotating at angular frequency ω , a phasor of the same angular frequency appears

as a constant or a dc signal. In simple terms, this is like sitting in a moving train and watching another

moving train appear stationary just because it is moving at the same speed.

This is the concept of the PLL. In order to synchronize with the grid, we generate a rotating

reference frame and through closed loop control, adjust the angular frequency of this rotating reference

frame such that the grid voltage phasor appears as a dc signal. This is when the rotating reference

frame has the same angular frequency as that of the grid and has locked on to the grid.

6

To achieve phase locking, we use a trigonometric relation that will be described. As with the

previous figures, let us assume that the grid voltage is a co-sinusoid:

V g =Vm cos(ωt)

Suppose, we could generate a sinusoid from the above signal - basically a signal that is 90◦ lagging to

it:

Vgsin =Vm sin(ωt)

How this will be done will be described in the later sections. Suppose, the rotating reference frame

was also a co-sinuoid:

Vr = cos(ωrt)

And suppose, we could generate a signal 90◦ lagging to the above signal:

Vrsin = sin(ωrt)

This is much easier as the reference frame is something we generate but it will be described later

anyway. We now have two sets of quadrature signals:

Vm cos(ωt),Vm sin(ωt) and cos(ωrt),sin(ωrt)

There are two combinations of trigonometric equations that are particularly interesting:

1 : Vm cos(ωt)cos(ωrt)+Vm sin(ωt)sin(ωrt)

2 :−Vm cos(ωt)sin(ωrt)+Vm sin(ωt)cos(ωrt)

Simplify these to:

1 :Vm

2[cos(ωt −ωrt)+ cos(ωt +ωrt)+ cos(ωt −ωrt)− cos(ωt +ωrt)]

2 :Vm

2[sin(ωt −ωrt)− sin(ωt +ωrt)+ sin(ωt −ωrt)+ sin(ωt +ωrt)]

After deleting terms:

Vm cos(ωt −ωrt) (1)

Vmsin(ωt −ωrt) (2)

The most important is the relation 2. We are going to try to control the angular frequency ωr of the

rotating reference frame. When ωr is equal to ω , the second term is equal to zero. This is the condition

for a successful phase-locking with respect to the grid and this will be used in the closed loop control

as will be described next.

7

Vm cos ωt

Vm sin ωt

cos

sin -1

*

*

+

+

+

+

∫

∫

Ki

Kp

ωr

ωnom

ωrt

Figure 5: Closed loop strategy of a PLL

4 Concept of a PLL

The block diagram above shows the closed loop control of a PLL. The top-left part is the expression

2 described in the previous page. As stated, that expression which is Vm sin(ωt −ωrt) should be zero

when the PLL has locked on. Therefore, we use this expression and feed it to a Proportional Integral

(PI) controller. By doing so, we use the nature of a PI controller such that by designing the closed loop

appropriately, the input to the PI controller is forced to zero. The output of the PI controller becomes

the angular frequency of the rotational reference frame. Since we know that drifts in frequency of the

grid are typically very small in the range of 1-2%, we add the nominal frequency ωnom to the output of

the PI controller to speed-up the closed loop tracking. For a 60 Hz system, ωnom would 377 rad/s while

for a 50 Hz system, ωnom would be 314 rad/s. To briefly describe how it works, refer to the previous

figure on rotational reference frames. When Vm sin(ωt−ωrt) is positive, it means the reference frame

angular frequency is lower than the grid angular frequency. The output of the PI controller when

fed this positive signal will also be positive causing the angular frequency of the reference frame to

increase. This in turn will decrease Vm sin(ωt −ωrt) and force it to zero. The angular frequency is

integrated to get the phase angle of the rotating reference frame.

With this basic description, we will now describe how we obtain from the grid voltage, a signal

that lags behind it by 90◦.

8

Figure 6: Integration of the grid voltage signal

Given any co-sinusoid or sinusoid, the simplest process to generate a signal that lags behind by

90◦ is by integrating it. As an example,

∫

Vm sin(ωt)dt =−Vm cos(ωt)/ω +C∫

Vm cos(ωt) =Vm sin(ωt)/ω +C

There are two problems with the above integration - one simple and the other a little more difficult.

The first is that integration produces a signal that is attenuated by the factor ω . This means if you

integrate the grid voltage, the result is a signal that is 377 times smaller if the grid is 60 Hz. This is

fairly simple to solve because the angular frequency of the rotational reference frame will be equal

to the angular frequency of the grid in steady state. Even if the desired signal is not exactly equal in

magnitude to the input grid voltage, that is good enough. This will be described in the next section.

The next problem is that of offsets. If the input grid voltage has any measurement offsets caused

due to temperature, aging of the measurement devices or any other noise, the integration will result in

a continuously increasing or decreasing signal. Over time, this will disrupt the control loop. As for

the integration offset C, this may result in a signal with an offset, purely based on the initial value of

the grid voltage. To examine this, check out the simulation file vgrid integration.csv with parameters

vgrid integration params.csv. A single voltage source of 120 V rms is measured. The control file

signal integral.py with variables in signal integral desc.csv contains the integration. The file also

contains a low pass filter which will be describe later. Use it without the low pass filter. The results in

the figure above show the performance of the integral. The first one shows the dc offset when the grid

voltage is a sinusoid. The second one shows the integral to be continuously increasing when a 0.1 V

dc offset is added to the grid voltage.

9

-

+∫

LPF

vgrid

vinteg

|LPF|ωω f = 20 rad/s

ω f

s+ω f

Figure 7: Implementation of low pass filter

To prevent the problems shown in the previous page, we use a Low Pass Filter (LPF). Since, it is

dc offsets in the measured grid voltage that are a problem, we need a LPF with a low cut-off frequency

that lets the dc offset pass through but will attenuate the fundamental 60 Hz component of the grid

voltage. This dc offset is now fed back to the input of the integrator as shown. The figure on the right

shows how the low pass filter is designed as a first order filter. In order to implement it digitally, the

filter is discretized as follows:

LPF(s) =ω f

s+ω f

LPF(z) =ω f

2T

z−1z+1

+ω f

=ω f T (z+1)

2(z−1)+ω f T (z+1)

LPF(z−1) =ω f T (1+ z−1)

2(1− z−1)+ω f T (1+ z−1)=

Y (z−1)

U(z−1)

(2+ω f T )y(n)− (2−ω f T )y(n−1) = ω f T [u(n)+u(n−1)]

y(n) =(2−ω f T )y(n−1)+ω f T (u(n)+u(n−1))

2+ω f T

Here, the bilinear transformation s = 2T

z−1z+1

is used to perform the discretization. T is the sampling

period of the LPF. In the example chosen, T = 100 microseconds. Substitute T = 0.0001 and ω f = 20

rad/s to get the filter co-efficients.

10

Figure 8: Effect of a low pass filter on integration offsets

The figure above shows the integration with the low pass filter. As can be seen both problems have

disappeared. There is no offset even though the grid voltage remains a sinusoid as in the previous case.

The integrated signal is stable even though the grid voltage has a 0.1 V dc offset. You could also try

to change the filter cut-off frequency or the sampling period to check out how the low pass filter

performs. As you increase the cut-off frequency, the LPF lets through not just the dc offset and very

low frequency signals if there are any but also lets through the fundamental 60 Hz component. There

will be a frequency ω f for which distortions may begin to creep in. As for the sampling period, as

you increase the period, you reduce the resolution of the filter. As you decrease the sampling period,

you begin to get quantization errors that will result in instability. The theory behind signal processing

is vast if you care to read. However, this simulation allows you to play around with values.

11

Figure 9: Single phase PLL - frequency and phase angle

5 Simulation of a single phase PLL

To try out the single phase PLL with all the blocks mentioned above, try out the circuit file sin-

gle phase pll.csv with parameters single phase pll params.csv and the control file single phase pll.py

with control variables single phase pll desc.csv. The above figures show the performance of the PLL.

The figure on the left shows how the angular frequency gradually settles to 377 rad/s. The initial os-

cillations can be attributed to various reasons - tuning of PI controller gains, the time taken to generate

a signal that lags behind the grid voltage by 90◦ etc. The figure on the right shows the phase angle

generated during steady state when compared to the grid voltage attenuated by a factor of 20. The

phase angle increases from 0 to 2π over a cycle of the grid voltage. The phase angle can be seen to be

a smooth sawtooth waveform despite minor oscillations in the angular frequency in the left plot due

to the smoothing action of the integrator.

Try out variations in the PI controller gains to check how the response changes and when it be-

comes completely unstable. Also, try out changing the frequency and phase angle of the grid voltage.

12

Figure 10: Single phase PLL - transformed voltages

The above figures show how the PLL performs in the closed loop control. As stated before, the

objective is to force Vm sin(ω −ωr)t to zero. The figure on the left shows this expression over time.

In steady state, the quantity is indeed forced close to zero. There are oscillations on the quantity even

in steady state which is the reason why there are oscillations in the angular frequency in steady state

(see the previous figure on the left). The initial oscillations in the expression Vm sin(ω −ωr)t show

how they are related to the excursions in the angular frequency. As stated before when Vm sin(ω −ωr)t is positive, it means ωr is less than ω and therefore ωr needs to increase and vice versa. The

other expression Vm cos(ω − ωr)t is plotted on the right. In steady state, when ωr is equal to ω ,

this expression gives the peak value of the grid voltage. This can be particularly useful in control

algorithms that require the grid peak voltage. The only problem is that it has oscillations. To use it in

control, it is advisable to pass it through another LPF as described in the previous section.

We can now look the operation of a three-phase PLL. As before we start with the concept of a

three-phase PLL.

13

V a

V b

V c

ω

ω

ω

Figure 11: Three phase voltages

6 Three phase PLL

The figure above shows a three-phase system of voltages va, vb, vc with vb lagging behind va by 120◦

and vc lagging behind vb by 120◦ as follows:

va =Vm cos(ωt)

vb =Vm cos(ωt −2π/3)

vc =Vm cos(ωt −4π/3)

As with the case of a single phase voltage, these three-phase voltages can be represented as vectors

rotating at an angular frequency of ω and the instantaneous values of the voltages are the projection

of the vectors shown on a stationary x-axis as shown. As with the case of a single-phase PLL, the

objective of a three-phase PLL is to generate a rotating reference frame that rotates with the same

angular frequency ω such that the projections of the vectors on the rotating reference frame are con-

stants. Since there are three vectors, let us suppose that we want this rotating reference frame to be

aligned with vector V a or phase a.

A simple and instinctive solution would be apply a single-phase PLL on phase a or for that matter

on all three phases thereby having accurate phase angle information of all phases. There is a simpler

solution due to the three-phase nature of the system. To begin with, it is possible for the voltages to

be unbalanced. As a worst case, it could be possible that one phase is opened and this phase could

be phase a. So applying a single-phase PLL to just one phase may not be a good solution. Applying

three single-phase PLLs to all three phases would work but we will soon see that is unnecessary.

14

V aV a

V b

V b

V cV c

ω

ω

ωω

ω

ω−0.5V b−0.5V b

−0.5V c−0.5V c

√3

2V b −

√3

2V c

V α

V β

Figure 12: Primary voltage and quadrature signal

In a single-phase PLL, in order to apply the trigonometric relation that results in Vm sin(ω−ωr)t, it

was necessary to generate a signal that was 90◦ lagging to the grid voltage. This we did by integrating

and passing it through a low pass filter. In a three-phase system, this is not necessary. Suppose, we

keep voltage va separate and want to generate a signal that is 90◦ lagging to it. We can do so by using

the voltages vb and vc as follows:

vb − vc =Vm cos(ωt −2π/3)−Vm cos(ωt −4π/3)

=Vm(−0.5cos ωt +0.866∗ sin ωt +0.5cos ωt +0.866sin ωt)

= 2Vm(0.866sin ωt) = 1.7321Vm cos(ωt −π/2)

So, by simply performing vb − vc, we have achieved a signal that lags behind va by 90◦. We have a

factor 1.7321 but we perform another calculation so that this is not a problem.

va −0.5vb −0.5vc =Vm[cosωt −0.5cos(ωt −2π/3)−0.5cos(ωt −4π/3)]

=Vm[cosωt −0.25cos ωt −0.5∗0.866sin ωt −0.25cos ωt +0.5∗0.866sin ωt]

= 1.5Vm cosωt

And, in the previous calculation, we perform:

0.866vb −0.866vc = 0.866∗1.7321Vm cos(ωt −π/2) = 1.5Vm cos(ωt −π/2)

The two transformed voltages are now of equal magnitude. And this is Clarke’s transformation, where

vα and vβ are the transformed voltages from the three-phase voltages expressed as:

vα =√

2/3(va −0.5vb −0.5vc)

vβ =√

2/3(0.866vb −0.866vc)

15

vα

vβ

cos

sin -1

*

*

+

+

+

+

∫

∫

Ki

Kp

ωr

ωnom

ωrt

Figure 13: Three phase PLL

After performing Clarke’s transformation, the voltages vα and vβ can be transformed to the ro-

tating reference frame as before and as shown in the above figure. It should be noted that the two

expressions for the single-phase PLL are called Park’s transformation and are written as follows:

vd = vα cosωt + vβ sin ωt

vq =−vα sinωt + vβ cosωt

(3)

The expression for vq is fed to the PI controller to adjust the angular frequency of the rotating reference

frame. The next figure shows the performance of a three-phase PLL. However, there is another issue

which will be addressed later - unbalance in the voltages.

16

Figure 14: Three phase PLL - frequency and phase angle

7 Simulation of a three phase PLL

The three phase PLL example can be found in the spreadsheet three phase pll.csv with parameters in

three phase pll params.csv and the PLL control file in three phase pll.py with the control variables

in three phase pll desc.csv. The figure above shows the performance of the three-phase PLL for a

voltage set that is perfectly balanced i.e the magnitudes of the three phase voltages are exactly equal

and phase b lags behind phase a by 120◦ and phase c lags behind phase b by 120◦. The performance

is quite similar to the single phase PLL shown before. One major difference - none of the oscillations

that are present in the single phase PLL can be seen above. The reason is that the voltages are perfectly

balanced. This will be discussed shortly. The figure on the left shows the angular frequency settle to

377 rads/s in steady state. The figure on the right shows how the phase angle changes from 0 to 2π

over one cycle of grid voltage phase a.

17

Figure 15: Three phase PLL - transformed voltages

The figure above shows the transformed voltages in the rotating reference frame. The figure on the

left shows vd which has a value equal to the line-to-line RMS value of the three-phase voltages. The

figure on the right shows vq which is forced to zero to synchronize the PLL by aligning the rotating

reference frame with the phase a vector.

A perfectly balanced three-phase source is quite rare. Some amount of unbalance is always present

in a three-phase source. The unbalance is typically in the magnitude of the voltages with all three

voltages not having the same magnitude. As a three-phase source is usually broken up into sepa-

rate single-phase systems to feed customers, the most common cause of unbalance is unbalance in

the loading between phases. The next simulation will describe what happens when the voltages are

unbalanced.

18

Figure 16: Unbalanced three-phase voltages - PLL frequency

8 Unbalanced three phase grid

In this example, we consider a small unbalance in the grid voltages. Phase b is given a peak of 160

V while phase a and c have peaks of 170 V. The figure on the left shows the waveforms of the grid

voltages and it can be seen that phase b (green) has a slightly smaller magnitude as compared to phase

a (blue) and phase c (red). This is a very small unbalance but from the figure on the right can be seen

to produce oscillations in the angular frequency of the rotating reference frame.

Unbalances can be minor like the one above caused by mere overloading in one phase or can be

major like a phase being opened (and that voltage being 0). Even under extreme unbalances, it would

be desirable that the PLL function. It may happen that a grid connected converter is forced to discon-

nect from the grid during extreme unbalances but then again it may be possible that a grid connected

converter is specially designed to operate in a particular manner during unbalanced conditions of the

grid. Let’s look at how the rest of the PLL performs.

19

Figure 17: Unbalanced PLL - phase angle and transformed voltage

The figure on the left shows the phase angle over a cycle of phase a grid voltage. The phase angle

can be seen to be fairly smooth despite the oscillations in angular frequency due to the smoothing

action of the integrator that generates the phase angle from the angular frequency. The figure on the

right shows the transformed voltage vq on the rotating reference frame. Even though this is forced to

zero, it contains oscillations. These oscillations appear in the angular frequency in the previous plot.

In the above case, the PLL still functions in a manner that is acceptable. However, the question is

how much unbalance can this PLL handle? Before, dealing with control, let us examine the concept

of unbalance and the effect it has.

20

V aV a

V b

V b V c

V c

ω

ω

ω

ω

ω

ω

Figure 18: Negative sequence voltages

The figure on the left above shows a balanced three-phase system. The figure on the left shows

a three-phase system in which phase b and phase c are interchanged. The sequence of phases is now

a-c-b instead of a-b-c. The magnitude of the voltages is the same in all phases. Such a three-phase

system is considered to be an most extreme form of unbalanced three-phase systems. The reader is

encouraged to read separately on unbalanced three-phase systems. This document will describe what

is necessary to design PLLs. This extreme unbalance condition is called a negative sequence. The

reason is as follows. If the balanced three-phase system on the left were applied to an induction motor,

the motor would rotate in a particular direction. However, if the unbalanced three-phase system on the

right were applied to an induction motor, it would rotate in the reverse direction. This is because the

magnetic flux now rotates in the reverse direction in the air-gap. It should be noted that if the phase

sequence in reversed but the magnitude remains the same in all phases, the torque is constant and the

speed of rotation in the reverse direction is constant. This is precisely the reason why this particular

case of unbalance is called the negative sequence.

21

V a

V aV b

V b

V c

V c

ω

ω

ω

ω

Figure 19: Zero sequence voltages

Unbalanced voltages also have another extreme. In the figure above on the left is shown the bal-

anced three-phase voltage set. On the right are shown the three phase voltages without any phase angle

difference between them. These three voltages also form an unbalanced set even if their magnitudes

are equal since phase b does not lag behind phase a by 120◦ and phase c does not lag behind phase b by

120◦. These unbalanced voltages are called zero sequence voltages. When the balanced three-phase

voltages on the left are applied to an induction motor, the result is a rotating magnetic field in the air

gap. The reason is that the three phases in an induction motor are wound with a displacement around

the stator which causes the net magnetic field produced in the air gap to be a rotating one. However,

when the zero sequence is applied to the same windings, the net magnetic field in the air gap is zero

as the magnetic fields due to the three phases cancel out. The result - no magnetic field, no torque, no

rotation. And thus the name zero sequence voltages.

22

V a

V b

V c

V a1

V b1

V c1

V a2

V b2

V c2

V a0

V b0

V c0

ω

ω

ωω

ω

ω ω

ω

ω

ω

Figure 20: Decomposition into sequence components

So, to repeat. Three-phase voltages can be perfectly balanced which means the magnitude of all

three phase voltages are equal and phase b lags behind phase a by 120◦ while phase c lags behind

phase b by 120◦. Or there can be two cases of extreme unbalance - the negative sequence where the

magnitudes of voltages in all three phases are the same but now phase c lags behind phase a by 120◦

and phase b lags behind phase c by 120◦ and the zero sequence where all three phase voltages have the

same magnitude but have no phase angle difference. Quite often, three phase voltages have a small

amount of unbalance like the simulated case where the magnitudes of the phase voltages may differ

by around 10% of the rated magnitude. In cases of short-circuits or faults, one or two phase voltages

may becomes zero or very low. The figure above shows on the left an arbitrary set of unbalanced

three phase voltages. Any unbalanced set of voltages can be decomposed into a positive sequence

(subscript 1) which are balanced three phase voltages, a negative sequence component (subscript 2)

and a zero sequence component (subscript 0) as shown on the right. The theory behind this will not be

included here and the interested reader is recommended to read any power system book or just search

on the internet “Sequence components”.

23

Of particular interest is the negative sequence component and the reason with respect to trans-

formations and the PLL will be shown below. Let us consider a negative sequence component of

three-phase voltages:

va2 =Vm2 cos(ωt)

vb2 =Vm2 cos(ωt −4π/3)

vc2 =Vm2 cos(ωt −2π/3)

As can be seen, vc2 lags behind va2 by 120◦ and vb2 lags behind vc2 by 120◦ so that the phase sequence

is a-c-b and not a-b-c. The component vα will not change as shown below:

vα =√

2/3 (va2 −0.5vb2 −0.5vc2)

=√

2/3 Vm2[cos(ωt)+0.5cos(ωt)+0.866sin(ωt)−0.5cos(ωt)−0.866sin(ωt)]

= 1.5√

2/3 Vm2 cos(ωt)

However, vβ changes:

vβ =√

2/3 (0.866vb2 −0.866vc2)

=√

2/3 Vm2[−0.433cos(ωt)−0.75sin(ωt)+0.433cos(ωt)−0.75sin(ωt)]

=−1.5√

2/3 Vm2 sin(ωt) = 1.5√

2/3 Vm2 cos(ωt +π/2)

vβ should lag behind vα by 90◦ but now it leads by 90◦. Now, let’s see how this impacts the voltages

in the rotating reference frame:

vd = vα cos(ωrt)+ vβ sin(ωrt)

= 1.5√

2/3 Vm2[cos(ωt)cos(ωrt)− sin(ωt)sin(ωrt)]

= 0.75√

2/3 Vm2[cos(ω −ωr)t + cos(ω +ωr)t − cos(ω −ωr)t + cos(ω +ωr)t]

= 1.5√

2/3 Vm2 cos(ω +ωr)t

Instead of the cos(ω − ωr)t term that would have meant that vd would be a constant value when

ω = ωr, we now have a cos(ω +ωr)t which will not be a constant as long as ωr is a positive number

which it has to be. Let’s look at vq:

vq =−vα sin(ωrt)+ vβ cos(ωrt)

= 1.5√

2/3 Vm2[−cos(ωt)sin(ωrt)− sin(ωt)cos(ωrt)]

= 0.75√

2/3 Vm2[sin(ω −ωr)t − sin(ω +ωr)t − sin(ω −ωr)t − sin(ω +ωr)t]

=−1.5√

2/3 Vm2 sin(ω +ωr)t

24

So now vq has a sin(ω +ωr)t term. So, even if the PLL has locked and ω = ωr, vq will not be zero

due to the negative sequence component. Quite often, you will hear about how unbalance in the three

phase voltages results in a double frequency component in the transformed voltages.

So how does this cause a problem? Look at the simulation results for a single phase PLL and the

three phase PLL with unbalance. Double frequency components exist in the transformed voltages. If

vα and vbeta or vgrid and vinteg do not have the same magnitude, a double frequency results in vd and vq.

These double frequency components when fed to the PI controller appear in the angular frequency ωr

of the rotational reference frame. The reason is that a double frequency component is tough to remove

with just a PI controller. A PI controller is a first-order controller with a single pole. This results in an

attenuation of 20 decibel per decade from the frequency of the pole. This means if the pole of the PI

controller is chosen to be ω f and at this frequency the gain is K, at a frequency of 10ω f , the gain is

0.1K. We try to choose the pole ω f to be as close to the origin as possible to be able to attenuate noise

and harmonics in the input. Basically, by decreasing ω f , for frequencies that are present in the grid,

the attenuation will be greater. After all, we are interested only in constant values as once the PLL

locks, the input to the PLL should be zero. But ω f can’t be made very low because in that case, the

settling time of the PLL increases. And this is why the double frequency component causes a serious

problem.

The double frequency component is quite often too low a frequency to be attenuated sufficiently

when ω f is chosen for a reasonably fast settling time of the PLL. As the unbalance in the system

increases, the negative sequence component increases. For very small unbalances as shown in the

previous simulation, even if there is a double frequency component, the PLL performance is still ac-

ceptable as the cumulative effect of the PI controller and the integrator results in a smooth phase angle

waveform. As will be shown next, for severe unbalances, the PLL performance will be unacceptable.

25

Figure 21: PLL with unbalanced voltages - Frequency

Let us repeat the simulation of a three phase PLL with circuit file three phase pll.csv and control

file three phase pll.py. The circuit parameters in three phase pll params.csv can be altered to make

the three phase source unbalanced. Let us increase the system frequency on all three phase voltages

to be 64 Hz to test how the PLL works when frequency drifts. Let us retain phase a voltage magnitude

peak to be 170V but reduce phase b and c magnitude peaks to 40V. This would be the case if a double

line to ground fault had occurred on phases b and c. The figure above shows the three phase voltages

with phase b and c significantly diminished. The PLL frequency output can be seen to have significant

oscillations of close to 10%. The problem is this frequency signal generated by the PLL cannot be

directly used in any other part of control due to the oscillations without filtering it.

26

Figure 22: PLL with unbalanced voltages - phase angle

The figure above shows the phase angle output of the PLL which is synchronized to phase a of

the three phase source. The phase angle is not distorted due to the action of the integrator on the PLL

frequency generated in the previous page. However, the voltage vq can be seen to have significant

double frequency oscillations.

If the phase angle has not become distorted, the PLL is still functional. However, quite often, the

PLL is also used to generate information of system frequency and voltage magnitude. These signals

will have double frequency oscillations and will need to be filtered to be of any use. Filtering is also

a tricky business with a double frequency component as a simple low pass filter will not be effective.

The implementation of a notch filter will be described next.

27

vq

N1N2

Notch

Filter

PI

ωr

ω f ω|NF|

Figure 23: Notch filter

The notch filter is inserted before the PI controller as shown in the figure above. The signal vq is

fed to the notch filter to remove the double frequency harmonic component shown in the simulation

results above. The output of the notch filter is then fed to the PI controller to generate the angular

frequency. The notch filter in the discrete domain is as below:

N(z) = 0.03z2 −1.996z+1

(z2 −1.93613z+0.9409)(z−0.97)

In the PLL control file three phase pll.py, the above notch filter is implemented in stages.

N1(z−1) =

1−1.996z−1 + z−2

1−1.93613z−1 +0.9409z−2

y1(n) = 1.93613y1(n−1)−0.9409y1(n−2)+u1(n)−1.996u1(n−1)+u1(n−2)

N2(z−1) =

0.03

1−0.97z−1

y2(n) = 0.97y2(n−1)+0.03u2(n)

The output of the first stage y1(n) is the input to the second stage u2(n). The output of the second

stage y2(n) is fed to the PI controller. The next simulation result will describe the performance of the

PLL under the same unbalanced condition with the notch filter.

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Figure 24: PLL with notch filter

The figure above shows the results of the same unbalanced system with a notch filter. The fre-

quency output of the PLL can be seen to be with significantly lower oscillations. The notch filter has

attenuated the double frequency component by a factor of around 8. Moreover, it should be noted

that the frequency of the three phase source is 64 Hz. Therefore, the PLL continues to work with

unbalance even when frequency drifts from the nominal. It is possible to widen the band of operation

of the notch filter. However, in that case the settling time of the PLL will increase. Such a trade-off

can be considered if some part of the control uses the angular frequency output of the PLL and needs

a smooth signal.

29

Figure 25: PLL with notch filter

The above figure shows the phase angle generated by the PLL synchronized with the phase a

voltage. Also shown is the transformed voltage vq. As can be seen vq continues to have very large

double frequency component. The notch filter has attenuated this double frequency component before

feeding it to the PI controller.

These simulation results show the performance of the PLL when the grid voltages are unbalanced.

However, quite often, the grid voltages have distortions and contain harmonics because of non-linear

load connected to the grid. The next simulation will describe the case.

30

Figure 26: PLL with distortions

To check how the PLL performs with distortions in the grid voltage, use the simulation files

three phase distorted.csv with parameters in three phase distorted params.csv and nonlinear load.csv

with parameters in nonlinear load params.csv. The PLL remains the same as three phase pll.py with

control variables in three phase pll desc.csv. The file nonlinear load.csv has a diode rectifier with a

large dc capacitor. The input current is extremely non-linear. Since the grid has an impedance, this

results in the measured grid voltage being distorted. The figure above shows the grid voltages to have

a considerable amount of harmonics. However, the angular frequency output of the PLL is a fairly

smooth signal showing the PLL still functions. The PI controller therefore performs a good job of

removing the harmonics in the transformed voltage vq.

31

Figure 27: PLL with distortions

The figure above shows the phase angle generated by the PLL synchronized with phase a of the

grid. The transformed voltage vq contains high frequency harmonics. These are largely removed by

the PI controller and the subsequent integrator.

This simulation shows how even though the grid has significant distortions, the PLL continues to

function. This PLL is therefore a very robust solution for grid connected converters that expect the

grid to be non-ideal.

32

9 Conclusions

This report describes the concept and implementation of a PLL through simulation cases. A reader

needs only a basic understanding of three phase systems and PI controllers to be able to understand this

report. The reader is stronly encouraged to make changes to the circuit files and associated control files

particularly with respect to control gains, filter cut-off frequencies and sampling periods to understand

how they impact the performance of the PLL. To get a deeper and rigorous understanding of different

aspects of PLL, the reader is encouraged to read the publications [1–5] in the reference list.

33

References

[1] V. Kaura and V. Blasko, “Operation of a phase locked loop system under distorted utility condi-

tions,” IEEE Transactions on Industry Applications, vol. 33, no. 1, pp. 58–63, Jan 1997.

[2] A. Timbus, M. Liserre, R. Teodorescu, and F. Blaabjerg, “Synchronization methods for three

phase distributed power generation systems - an overview and evaluation,” in 2005 IEEE 36th

Power Electronics Specialists Conference, June 2005, pp. 2474–2481.

[3] R. M. S. Filho, P. F. Seixas, P. C. Cortizo, L. A. B. Torres, and A. F. Souza, “Comparison of three

single-phase PLL algorithms for ups applications,” IEEE Transactions on Industrial Electronics,

vol. 55, no. 8, pp. 2923–2932, Aug 2008.

[4] S.-J. Lee, J.-K. Kang, and S.-K. Sul, “A new phase detecting method for power conversion systems

considering distorted conditions in power system,” in Conference Record of the 1999 IEEE In-

dustry Applications Conference. Thirty-Forth IAS Annual Meeting (Cat. No.99CH36370), vol. 4,

1999, pp. 2167–2172 vol.4.

[5] L. G. B. Rolim, D. R. da Costa, and M. Aredes, “Analysis and software implementation of a robust

synchronizing PLL circuit based on the pq theory,” IEEE Transactions on Industrial Electronics,

vol. 53, no. 6, pp. 1919–1926, Dec 2006.

34