Phase-2 pixel “V0” Proposal of a straw-man geometry May 20, 2014 Phase-2 Pixel Electronics Meeting 1
Jan 12, 2016
1Phase-2 Pixel Electronics Meeting
Phase-2 pixel “V0”Proposal of a straw-man geometry
May 20, 2014
Phase-2 Pixel Electronics Meeting 2
G. Sguazzoni in the Tracker Upgrade Session @ KIT https://indico.cern.ch/event/307600/contribution/12/material/slides/0.pdf
Recall some highlights: Assume large chips of 21×23 mm2 active, 23×23 mm2 physical Use 4×1 modules in barrel layers 1-2, 4×2 modules in layers 3-4
The first layer has 10 modules in φ
Several options considered for the forward “Flower” geometry and “tile” geometry
o The tile geometry reduces overlaps
Pixel sizes considered: Inner parts: 50×50 μm2 or 25×100 μm2
Outer part: 100×100 μm2 or 50×200 μm2
First ideas presented in April
May 20, 2014
Implemented over 4 different surfaces
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Large pixel chip may create issues for bump-bonding Bump-bonding of FE-I4 was not straightforward Even larger area should not be taken as starting point
R&D needed!
The mechanics for the “flower” geometry is a priori not more complicated than the “tile” geometry, if the surfaces are flat
In the tile geometry, services come out at some specific φ locations Redistribution is most likely needed, but might be difficult
Cannot be taken for granted, requires some engineering studies
A pixel of 25×100 μm2 is significantly more difficult than 50×50 μm2
For planar silicon, and even more for 3D
The best b-tagging algorithms use tracking in 3d Better performance and higher robustness wrt high pile-up The performance to first order depends on the pixel area, not the aspect ratio
A square pixel a priori gives higher robustness wrt high pile-upo Possibility to go beyond 140 <PU> is being discussed more and more…
In the forward the main requirement is pile-up mitigation Requires good z0 resolution on tracks Some momentum resolution is certainly also desirable
Maybe a square pixel is a simple good balance?
Constructive feedback received
May 20, 2014
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Next steps Define a “Version 0” with reasonably safe assumptions,
that can be defended on some solid basis In future, compare different options in terms of potential
performance, risks, cost…
Implement the “pixel V0” in tkLayout and derive basic properties (ongoing)
Translate geometry to CMSSW for full simulation In parallel: develop toy model for the electronics, to start
building a first guess of the detector material
May 20, 2014
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The Pixel V0 Fall back to smaller chips: 17×19 mm2 active, 19×19 mm2
physical Active width of 17 mm is the next “useful” value, as it corresponds to a 12-
faces 1st barrel layer (as opposed to 10-faces, discussed @ KIT) N.B. 2 mm for the end-of-column is a guess; a square chip is a starting point, not a necessity
Such dimensions are slightly smaller than the ATLAS FE-I4: likely doable (although we are still increasing the bump density)
A larger chip can be reconsidered after some successful R&D on bump-bonding
Take square pixels as starting point 50×50 μm2 in the inner region, 100×100 μm2 in the outer region Good combination of all different requirements
I.e. it may not be the optimum, but it’s certainly not a useless configuration to study
Good ground to compare planar silicon and 3D silicon Benchmark to evaluate possible improvements with different (more
complicated) options
May 20, 2014
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The Pixel V0 Barrel
Still consider 1×4 modules in layers 1-2 and 2×4 modules in layers 3-4 Layer 1 with 12 faces: mechanics could be very similar to the existing one!
All layers have ×4 multiplicity in φ Length similar to present BPIX obtained with 7 modules
Avoids the annoying feature of the projective hole at z = 0
May 20, 2014
Layer avg R (mm) DR Nphi W_active Overlap (mm)1 30 3 12 17 0.942 62 3 24 17 0.693 105 3 20 34 0.744 147 3 28 34 0.88
1×42×4
0 100 200
0 0.2 0.4 0.6 0.8 1.0 1.2
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The Pixel V0 Forward
Start with the better-understood “flower” geometry, with flat surfaces Simplest option “Tile” geometry can be reconsidered later and compared
o Requires some understanding of the services
More complicated 3-d geometries (e.g. turbine) can be studied and comparedo Advantages vs complication, amount of material, surface of silicon, etc…
Take inspiration from the double-disk geometry adopted for the Outer Endcap But with split on the vertical axis!
Cover radial range 32 mm – 160 mm Hermeticity achievable in a clash-free geometry with ½-size modules wrt the barrel Use same 50×50 μm2 and 100×100 μm2 pixel size as in the barrel
May 20, 2014
1×2
2×2
Ring # W_active L_active N_phi1 17 38 202 17 38 323 34 38 244 34 38 30
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Active surfaces
May 20, 2014
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Back diskFront disk
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Phase-2 Pixel Electronics Meeting
Active/physical front disk (2 mm for end-of-column)
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Active/physical back disk (2 mm for end-of-column)
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All together
May 20, 2014
Outer Tracker Pixel Total
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All together
May 20, 2014
Outer Tracker Pixel Total
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Some performance “numbers” Pessimistic assumptions on resolutions
10×10 for 50×50 μm2 pixel size, 25×25 for 100×100 μm2 pixel size We should be able to do better than that!
The amount of material is not under control We do not have a sufficiently detailed concept, yet
Still, what we have in tkLayout is certainly pessimistic, at least in some regions
Let’s look at some numbers nonetheless:
Gives a first hint that what we are doing makes some sense!
May 20, 2014
eta= 3 eta = 3.4 eta = 3.710 GeV 100 GeV 15 GeV 150 GeV 20 GeV 200 GeV
σ(d0) [mm] 0.15 0.03 0.15 0.03 0.15 0.04σ(z0) [mm] 1 0.2 1.5 0.2 2 0.4σ(p)/p [%] 4 4 5 9 6 15
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Thank you!Feedback, as usual, most welcome…
May 20, 2014