Phase-1 Design. i PHC Phase 1 [email protected] 2 03/04/2008 System Overview Clock, JTAG, sync marker and power supply connections Digital output.

Phase-1 Design

Phase 1 [email protected] 203/04/2008

iPHC

System Overview

Clock, JTAG, sync marker and power supply connections Digital output only 4 data outputs per chip at 160 MHz 40 LVDS pairs to drive 1 m cable connection

Low-mass system 10 chips per ladder Directly bonded on

n-layers flex capton LVDS drivers on chip

Phase 1 [email protected] 303/04/2008

iPHC

Preliminary specifications

Process 0.35 µm (AMS c35b4/opto) (3.3 V ± 0.3 V) Matrix of 640 x 640 pixels with 30 µm pitch Raw digital output without zero suppression JTAG control for configuration and testing Internal bias DACs 2 levels of multiplexer:

Low speed (40 MHz for test) and High speed (160 MHz)

Bonding pad location at the bottom edge Analog test pads (~ 100µm x 100µm) on the top edge

Area estimation 19.5 mm x 21.0 mm

Phase 1 [email protected] 403/04/2008

iPHC

Chip floor-plan

Ex. FRDO = 160 MHz Discriminator frequency = 1 MHz In pixel frequency = 16 MHz Integration time = 640 µs

Integration time = 160 / FRDO x 640Phase 1 [email protected] 523/11/2007

iPHC

Preliminary floor-plan

Ex. FRDO = 160 MHz Discriminator frequency = 1 MHz In pixel frequency = 16 MHz Integration time = 640 µs

Integration time = 160 / FRDO x 640

640 Discriminators

Pixel array 640x640

MUX41 LVDS FRDO

FRDO / 160

FRDO / 10(16 CK)

401 401 401 401

MUX41 LVDS MUX 41 LVDS MUX 41 LVDS

401 401 401 401 401 401 401 401 401 401 401 401 FRDO / 4

Shift Row Reg 640bits

Pixel sequencer+

Buffer tree

Simple digital pattern generator for data transfer test purpose

Disable discriminator Register

Selectable analog outputs ~ 200 µm for Pads + Electronics

Pads

19500 µm

210

00

µm

Phase 1 [email protected] 503/04/2008

iPHC

Mimosa22 background

Best suitable pixel to be chosen from M22 test Digital control logic

Pixel scan => resized to 640 rows Pattern generator => OK

JTAG interface => markers for synchronizations Output multiplexer with fast/slow outputs

not present in M22 -- NEW DESIGN

Improved Testability for digital and analog blocks 2 registers for test patterns at the discriminator level characterization of pixel matrix

Reuse the experience and building blocks of M22

Phase 1 [email protected] 603/04/2008

iPHC

Critical points and chip testability

High speed output @160 MHz Synchronization among the chips in the ladder

Internal generation of markers + frame counter How to recovery if chips are out of sync (adding more pins)

LVDS pads drive 1m of flex cable Power consumption

Static: ~ 400 mW Dynamic: ~60mW (serializ.); 110 mW (6 x LVDS TX);

8 mW (LVDS RX);

Testability based on M22: Digital: + additional synchronization markers Analog information from groups of 8 columns of pixels

Phase 1 [email protected] 703/04/2008

iPHC

Phase-1: I/O

~ 50 signals (7 LVDS pads included)

Standard CMOS pads for low speed outputs

~ 50 power supply lines Two bonding per I/O to

facilitate probe testing Analog outputs (8 pads)

on top edge for testing purpose

More detailed list later…

Phase 1 [email protected] 803/04/2008

iPHC

640 Discriminators

Pixel array 640x640

Shift Register (80 bits)

Analog Multiplexer 180 (8640)

8 Analog Outputs

8

8

88

80

In normal mode the shift register is

disabled. The first 8 columns are read

continuously.

In scan mode the shift register is

enabled: groups of 8 columns are read

after the read of 640 lines.

Analog Test for Pixel Matrix

Phase 1 [email protected] 903/04/2008

iPHC

Serializer

Mux 160:1 4 intermediate outputs at low-speed for test Scrambled data at the fast output Latency

25.0 ns for low speed output 6.25 ns for high speed output