Pertemuan 18 Control Unit 1

1

Pertemuan 18Control Unit 1

Matakuliah : H0344/Organisasi dan Arsitektur Komputer

Tahun : 2005

Versi : 1/1

2

Learning Outcomes

Pada akhir pertemuan ini, diharapkan mahasiswa

akan mampu :

• Menjelaskan prinsip kerja control unit dalam mengeksekusi beberapa instruction

3

Outline Materi

• Micro-Operations

• Control of Processor

• Hardwired Implementation

4

Micro-operation

Constituent elements of a program execution

Instructioncycle

Instructioncycle

Instructioncycle

IndirectFetch Execute Interrupt

OP OP OP OP OP

5

Micro-operationThe fetch cycle

t1 : MAR PC

t2 : MBR Memory

PC PC + 1

t3 : IR MBR

0000.0000.0110.0100

0000.0000.0110.0100

0000.0000.0110.0100

0000.0000.0110.0100

0000.0000.0110.0100

0001.0000.0010.0000

0000.0000.0110.0100

0000.0000.0110.0100

0001.0000.0010.0000

0001.0000.0010.0000

MAR

MBR

PC

IR

AC

(a) Beginning

MAR

MBR

PC

IR

AC

(b) First step

MAR

MBR

PC

IR

AC

MAR

MBR

PC

IR

AC

(c) Second step

(d) Third step

6

Micro-operationThe indirect cycle

t1 : MAR IR(address)

t2 : MBR Memory

t3 : IR(address) MBR(address)

The interrupt cycle

t1 : MBR PC

t2 : MAR Save_address

PC Routine_address

t3 : Memory MBR

7

The execute cyclet1 : MAR IR(address)

t2 : MBR Memory

t3 : R1 R1 + MBR

Micro-operation

t1 : MAR IR(address)

t2 : MBR Memory

t3 : MBR MBR + 1

t4 : Memory MBR

If (MBR = 0) then (PC PC + 1)

t1 : MAR IR(address)

MBR PC

t2 : PC IR(address)

Memory MBR

t3 : PC PC + 1

Add R1, X

Isz X

Bsa X

8

Micro-operationFlowchart for instruction cycle

Setupinterrupt

Readaddress

Opcode?

Interruptfor enabledinterrupt?

ICC?

ICC = 00 ICC = 10

ICC = 11 ICC = 00

Indirectaddress?

Fetchinstruction

ICC = 10 ICC = 01

00 : Fetch11 : Interrupt

10 : Execute 01 : Indirect

No

No

Yes

Yes

ICC =00 : Fetch01 : Indirect10 : Execute11 : Interrupt

9

Model of the control unit

Control of The processor

Control unit

Instructionregister

Flag

Clock

Control signalswithin CPU

Control signalsfrom system bus

Control signalsto system bus

Controlbus

10

Data paths and control signals

Control of The processor

MBR

PC

MAR

IR

Controlunit

Clock

ALU

AC

C1

C2

C3 C4

C5

C6 C7

C8

C0 C9

C10

C11

C12

C13

Flags

Controlsignals

11

Micro-operations and control signals

Control of The processor

Micro-operation Timing Active Control Signals

Fetch t1 : MAR PCt2 : MBR Memory PC PC + 1t3 : IR MBR

C2C5, CR

C4

Indirect t1 : MAR IR(address)t2 : MBR Memoryt3 : IR(address) MBR (address)

C8C5C4

Interrupt t1 : MAR PCt2 : MBR Save address PC Routine addresst3 : Memory MBR

C2

C12, CW

12

Internal Processor Organization

Control of the processor

Control unit

IR

PC

MAR

MBR

AC

Y

ALU

Y

Address lines

Data lines

13

Hardwired implementation

I1 I2I0 Ik

Decoder

T1

T2

T3

Tn

Control unitTiming

generatorClock

C1 C2C0 Cm

Flags

Instruction register