1 Pertemuan 15 Organisasi I/O: I Matakuliah : T0324 / Arsitektur dan Organisasi Komputer Tahun : 2005 Versi : 1
Welcome message from author
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
1
Pertemuan 15Organisasi I/O: I
Matakuliah : T0324 / Arsitektur dan Organisasi Komputer
Tahun : 2005
Versi : 1
2
Learning Outcomes
Pada akhir pertemuan ini, diharapkan mahasiswa
akan mampu :
• Mahasiswa dapat membandingkan beberapa metode pengaksesan peralatan I/O dalam sistem komputer ( C4 ) ( No TIK : 7 )
3
Chapter 4.
Input/OutputOrganization: I
4
Processor Memory
I/O device 1 I/O device n
Bus
Figure 4.1. A single-bus structure.
5
I/O
Bus
Address lines
Data lines
Control lines
Figure 4.2. I/O interface for an input device.
interfacedecoderAddress Data and
status registersControlcircuits
Input device
6
KEN
SOUT
CONTROL
DATAIN
Figure 4.3. Registers in keyboard and display interfaces.
DEN
DATAOUT
7
KIRQ SINSTATUS
6 5 4 3 2 1 0
DIRQ
7
Move #LINE,R0 Initializememorypointer.WAITK TestBit #0,STATUS Test SIN.
Branch=0 WAITK Wait for charactertobeentered.Move DATAIN,R1 Readcharacter.
WAITD TestBit #1,STATUS Test SOUT.Branch=0 WAITD Wait fordisplay to becomeready.Move R1,DATAOUT Sendcharactertodisplay.Move R1,(R0)+ Storecharacterandadvancepointer.Compare #$0D,R1 Check if CarriageReturn.Branch0 WAITK If not,getanothercharacter.Move #$0A,DATAOUT Otherwise,sendLine Feed.Call PROCESS Call asubroutineto process
theinputline.
Figure 4.4 A program that reads one line from the keyboard stores it in memory buffer, and echoes it back to the display.
8
Figure 4.5. Transfer of control through the use of interrupts.
here
Interruptoccurs
M
i
2
1
PRINT routine
Program 2Program 1
COMPUTE routine
i 1+
9
Processor
INTR
R
Figure 4.6. An equivalent circuit for an open-drain bus usedto implement a common interrupt-request line.
INTR1 INTR2 INTR n
Vdd
INTR
10
Priority arbitration
Device 1 Device 2 Device p
circuit
Pro
cess
or
Figure 4.7. Implementation of interrupt priority using individual
INTA1
INTR1 INTRp
INTA p
interrupt-request and acknowledge lines.
Figure 4.7. Implementation of interrupt priority using individual interrupt-request and acknowledge lines.
11
Figure 4.8. Interrupt priority schemes.
(b) Arrangement of priority groups
Device Device
circuitPriority arbitration
Pro
cesso
r
Device Device
(a) Daisy chain
Pro
cesso
r
Device 2
INTR
INTA
INTR1
INTR p
INTA1
INTA p
Device nDevice 1
12
MainProgram
Move #LINE,PNTR Initializebufferpointer.Clear EOL Clearend-of-lineindicator.BitSet #2,CONTROL Enablekeyboard interrupts.BitSet #9,PS Setinterrupt-enablebit in the PS....
Interrupt-serviceroutine
READ MoveMultiple R0-R1, (SP) SaveregistersR0 andR1onstack.Move PNTR,R0 Loadaddresspointer.MoveByte DATAIN,R1 GetinputcharacterandMoveByte R1,(R0)+ storeit inmemory.Move R0,PNTR Updatepointer.
CompareByte #$0D,R1 Check ifCarriageReturn.Branch0 RTRNMove #1,EOL Indicateendof line.BitClear #2,CONTROL Disablekeyboardinterrupts.
RTRN MoveMultiple (SP)+,R0-R1 RestoreregistersR0and R1.Return-from-interrupt
Figure 4.9. Using interrupts to read a line of characters from a keyboard via the registers in Figure 4.3.
–
13
OSINIT Set interrupt vectors:Time-slice clo ck SCHEDULERSoft ware interrupt OSSER VICESKeyb oard interrupts IOData
...OSSER VICES Examine stack to determine requested operation.
Call appropriate routine.SCHEDULER Save program state.
Select a runnable process.Restore saved context of new pro cess.Push new values for PS and PC on stac k.Return from interrupt.
(a) OS initialization, services, and scheduler
IOINIT Set pro cess status to Blo cked.Initialize memory buffer address poin ter and coun ter.Call device driv er to initialize device
and enable interrupts in the device interface.Return from subroutine.
IOD ATA Poll devices to determine source of interrupt.Call appropriate driv er.If END = 1, then set process status to Runnable.Return from interrupt.
(b) I/O routines
KBDINIT Enable interrupts.Return from subroutine.
KBDD A TA Chec k device status.If ready , then transfer character.If character = CR, then {set END = 1; Disable interrupts }
else set END = 0.Return from subroutine.
(c) Keyboard driver
Figure 4.10. A few operating system routines.
14
Figure 4.11. Low-order byte of the ARM processor status register.
7 6 5 4 3 2 1 0
M4 M0M1M2M3I F
15
Figure 4.12. Accessible registers in different modes of the ARM processor.
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
User FIQ Supervisor Abort UndefinedIRQ
R15 R15 R15 R15 R15
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R0
R1
R2
R3
R4
R5
R6
R7
General-purpose registers and program counter
Processor status register
CPSR CPSR CPSR CPSR CPSR CPSR
SPSR_fiq SPSR_irq SPSR_svc SPSR_abt SPSR_und
R8_fiq
R9_fiq
R10_fiq
R11_fiq
R12_fiq
R13_fiq
R14_fiq
R13-svc
R14_svc
R13_abt
R14_abt
R13_und
R14_und
R13_irq
R14_irq
16
Main program
MO V R0,#0STR R0,EOL Clear EOL flag.ADR R1,D A TAIN Load address of Register D A T AIN.LDRB R0,[R1,#3] Get contents of CONTROL register.ORR R0,R0,#4 Set bit KEN in register CONTR OLSTRB R0,[R1,#3] to enable keyboard interrupts.MO V R0,#&50 Enable IR Q interrupts in processorMSR CPSR,R0 and switc h to user mo de....
IR Q Interrupt-service routine
READ STMFD R13!, { R0 R2,R14 irq } Sav e R0, R1, and R14 irq on the stack.ADR R1,DATAIN Load address of register DA TAIN.LDRB R0,[R1] Get input character.LDR R2,PNTR Load pointer value.STRB R0,[R2],#1 Store character and increment pointer.STR R2,PNTR Up date poin ter value in the memory .CMPB R0,#&0D Chec k if Carriage Return.LDMNEFD R13!, { R0 R2,R14 irq } If not, restore registersSUBNES PC,R14 irq,#4 and return.LDRB R0,[R1,#3] Otherwise get CONTROL register.AND R0,R0,#&FB Clear bit KENSTRB R0,[R1,#3] to disable keyboard interrupts.MO V R0,#1 Set EOL flag.STR R0,EOLLDMFD R13!, { R0-R2,R14 } Restore registersSUBS PC,R14 irq,#4 and return.
Figure 4.13. An ARM interrupt-service routine to read an input line from a keyboard based on Figure 4.9.
17
ConditionCodesInterrupt
PrioritySupervisor
Trace
T S X N Z V C
012348101315
Figure 4.14. Processor status register in the 68000 processor.
18
Mainprogram
MOVE.L #LINE,PNTR Initializebufferpointer.CLR EOL Clearend-of-lineindicator.ORI.B #4,CONTROL Setbit KEN.MOVE #$100,SR Setprocessorpriority to1....
Interrupt-serviceroutine
READ MOVEM.L A0/D0, (A7) SaveregistersA0,D0 onstack.MOVEA.L PNTR,A0 Loadaddresspointer.MOVE.B DATAIN,D0 Getinput character.MOVE.B D0,(A0)+ Storeit inmemorybuffer.MOVE.L A0,PNTR Updatepointer.CMPI.B #$0D,D0 Check ifCarriageReturn.BNE RTRNMOVE #1,EOL Indicateendofline.ANDI.B #$FB,CONTROL Clearbit KEN.
RTRN MOVEM.L (A7)+,A0/D0 RestoreregistersD0, A0.RTE
Figure 4.15. A 68000 interrupt-service routine to read an input line from a keyboard based on Figure 4.9.
–
19
Figure 4.16. Part of the Pentium's processor status register.
15 14 13 12 11 10 9 8
TFIFIOPL
20
Mainprogram
MOV EOL,0MOV BL,4OR CONTROL,BL SetKEN toenablekeyboard interrupts.STI Set interruptflagin processorregister....
Interrupt-serviceroutine
READ PUSH EAX SaveregisterEAX onstack.PUSH EBX SaveregisterEBX onstack.MOV EAX,PNTR Loadaddresspointer.MOV BL,DATAIN Get inputcharacter.MOV [EAX],BL Storecharacter.INC DWORDPTR[EAX] Increment PNTR.CMP BL,0DH Check if characteris CR.JNE RTRNMOV BL,4XOR CONTROL,BL Clearbit KEN.MOV EOL,1 Set EOLflag.
RTRN POP EBX RestoreregisterEBX.POP EAX RestoreregisterEAX.IRET
Figure 4.17. An interrupt-servicing routine to read one line from a keyboard using interrupts on IA-32 processors.
21
Done
IE
IRQ
Status and control
Starting address
Word count
WR/
31 30 1 0
Figure 4.18. Registers in a DMA interface.
22
Figure 4.19. Use of DMA controllers in a computer system.
memoryProcessor
Keyboard
System bus
Main
InterfaceNetwork
Disk/DMAcontroller Printer
DMAcontroller
DiskDisk
Figure 4.19. Use of DMA controllers in a computer system.
23
Processor
DMAcontroller
1
DMAcontroller
2BG1 BG2
BR
BBSY
Figure 4.20. A simple arrangement for bus arbitration using a daisy chain.
24
BBSY
BG1
BG2
Busmaster
BR
Processor DMA controller 2 Processor
Figure 4.21. Sequence of signals during transfer of b us mastership
for the devices in Figure 4.20.
Time
Figure 4.21. Sequence of signals during transfer of bus mastership for the devices in Figure 4.20.
25
Figure 4.22. A distributed arbitration scheme.
Interface circuitfor device A
0 1 0 1 0 1 1 1
O.C.
Vcc
Start-Arbitration
ARB0
ARB1
ARB2
ARB3
26
Pertemuan 16Organisasi I/O: II
Matakuliah : T0324 / Arsitektur dan Organisasi Komputer
Tahun : 2005
Versi : 1
27
Learning Outcomes
Pada akhir pertemuan ini, diharapkan mahasiswa
akan mampu :
• Membandingkan beberapa metode pengaksesan peralatan I/O dalam sistem komputer ( C4 ) ( No TIK : 7 )
28
Chapter 4.
Input/OutputOrganization: II
29
Figure 4.23. Timing of an input transfer on a synchronous bus.
Bus cycle
Data
Bus clock
commandAddress and
t0 t1 t2
Time
30
Figure 4.24. A detailed timing diagram for the input transfer of Figure 4.23.
Data
Bus clock
commandAddress and
t0 t1t2
commandAddress and
Data
Seen by master
Seen by slave
tAM
tAS
tDS
tDM
Time
31
Figure 4.25. An input transfer using multiple clock cycles.
1 2 3 4
Clock
Address
Command
Data
Slave-ready
Time
32
Figure 4.26. Handshake control of data transfer during an input operation.
Slave-ready
Data
Master-ready
and commandAddress
Bus cycle
t1 t2 t3 t4 t5t0
Time
33
Figure 4.27. Handshake control of data transfer during an output operation.
Bus cycle
Data
Master-ready
Slave-ready
and commandAddress
t1 t2 t3 t4 t5t0
Time
34
Valid
Data
Keyboardswitches
Encoderand
debouncingcircuit
SIN
Inputinterface
Data
Address
R /
Master-ready
Slave-ready
W
DATAIN
Processor
Figure 4.28. Keyboard to processor connection.
35
DATAIN
Keyboarddata
ValidStatusflag
Read-
1Slave-
Read-
SIN
ready
A31
A1
A0
Addressdecoder
Q7 D7
Q0 D0
D7
D0
R/ W
Figure 4.29. Input interface circuit.
data
status
ready
Master-
36
37
CPU SOUT
Outputinterface
Data
Address
R /
Master-eady
Slave-ready
ValidW
DataDATAOUT
Figure 4.31. Printer to processor connection.
PrinterProcessor
Idle
38
39
D A TAIN
1
SIN
Ready
A31
A1
A0
Addressdecoder
D7
D0
R / W
Figure 4.33. Combined input/output interface circuit.
A2
D A TA OUT
Inputstatus
BusPA7
PA0
CA
PB7
PB0
CB1CB2
SOUT
D1
RS1
RS0
My-address
Handshak econtrol
Master -
ReadySla v e-
40
DATAIN
DATAOUT
DataDirectionRegister
Register
select
Statusand
control
Accept
ReadyR/W
RS0
RS1RS2
My-address
INTR
C1
C2
P7
P0
D7
D0
Figure 4.34. A general 8-bit parallel interface.
41
Handshak econtrol
D ATA OUT
Printerdata
Idle
ValidRead Load
SOUT
ready
A31
A1
A0
Addressdecoder
D 7 Q 7
D 0 Q 0
D7
D0
Figure 4.35. A parallel point interface for the bus of Figure 4.25,with a state-diagram for the timing logic.
status data
D 1 Q 1D0
T imingLogic
Clock
My-address
R/ W
Sla v e-
Idle Respond
My-address
Go
Go=1
42
Figure 4.36. T iming for the output interf ace in Figure 4.35.
1 2 3
Clock
Address
R/W
Data
Slave-ready
Go
Time
43
INTR
Chip andregisterselect
Statusand
control
Accept
Ready
R/W
RS0
RS1
My-address
Receiving clock
Transmission clock
Figure 4.37. A serial interface.
D7
D0
Output shift register
DATAOUT
DATAIN
Input shift register
Serialoutput
Serialinput
44
memoryProcessor
Bridge
Processor b us
PCI b us
Main
memoryAdditional
controllerCD-R OM
controllerDisk
Disk 1 Disk 2 R OMCD-
SCSIcontroller
USBcontroller
V ideo
K eyboard Game
diskIDE
SCSI b us
Figure 4.38. An example of a computer system using different interface standards.
ISAinterf ace
Ethernetinterf ace
45
Figure 4.39. Use of a PCI bus in a computer system.
memory
Host
PCI bridge
EthernetPrinterDisk
interface
PCI bus
Main
46
1 2 3 4 5 6 7
CLK
Frame#
AD
C/BE#
IRDY#
TRDY#
DEVSEL#
Adress #1 #4
Cmnd Byte enable
Figure 4.40. A read operation on the PCI bus.
#2 #3
47
1 2 3 4 5 6 7 8 9
CLK
Frame#
AD
C/BE#
IRDY#
TRDY#
DEVSEL#
Adress #1 #2 #3 #4
Cmnd Byte enable
Figure 4.41. A read operation showing the role of IRDY#/TRDY#.
48
Free Arbitration Selection
Tar gets examine ID
DB2
DB5
DB6
BSY
SEL
Figure 4.42. Arbitration and selection on the SCSI bus.Device 6 wins arbitration and selects device2.
49
Host computer
Roothub
Hub
Figure 4.43. Universal Serial Bus tree structure.
I/Ode vice
Hub I/Ode vice
I/Ode vice
Hub
I/Ode vice
I/Ode vice
I/Ode vice
50
Host computer
RootHub
Hub A
De vice
Figure 4.44. Split bus operation
D
F/LS
HS HS
HSHS - High speedF/LS - Full/Lo w speed
Hub B
De viceC
51
PID 0 PID 1 PID 2 PID 3 PID 0PID 0 PID 1 PID 2 PID 3
(a) Packet identifier field
PID ADDR ENDP CRC16
8 7 4 5Bits
(b) Token packet, IN or OUT
PID DA TA CRC16
8 0 to 8192 16Bits
(c) Data packet
Figure 4.45. USB packet format.
52
ACK
Token
Data0
Token
Data1
Figure 4.46. An output transfer.
Host Hub I/O Device
Token
Data0
ACK
ACK
Token
Data1
ACK
Time
53
PID Frame number CRC5
8 11 5Bits
(a) SOF Packet
Figure 4.47. USB frames.
S T3 D S
1-ms frame
T7 D T3 D
S - Start-of-frame pack etT n - T ok en pack et, address = nD - Data pack etA - A CK pack et
(b) Frame example
54
BG1 BG2 BGn
BRnBR2BR1
Figure P4.1. A decentralized bus assignment scheme.
55
Table 4.1. Interrupt vector addresses for ARM processor
Address Exception Modeentered(hex)
0 Reset Supervisor
4 Undefinedinstruction Undefined
8 Softwareinterrupt Supervisor
C Abortduringprefetch Abort
10 Abortduringdata Abort
14 Reserved
18 IRQ IRQ
1C FIQ FIQ
56
Table 4.2. Address correction during return from exception.
Exception Savedaddress* Desired Returninstructionreturnaddress
Undefinedinstruction PC+4 PC+4 MOVS PC,R14und
Softwareinterrupt PC+4 PC+4 MOVS PC,R14svc
PrefetchAbort PC+4 PC SUBS PC,R14abt,#4
DataAbort PC+8 PC SUBS PC,R14abt,#8
IRQ PC+4 PC SUBS PC,R14irq,#4
FIQ PC+4 PC SUBS PC,R14fiq,#4
* PC istheaddressoftheinstructionthatcausedtheexception.For IRQandFIQ,it istheaddressofthefirstinstructionnotexecutedbecauseof theinterrupt.
57
Table 4.3. Data transfer signals on the PCI bus.
Name Function
CLK A 33-MHzor66-MHzclock.
FRAME# Sent by theinitiatortoindicatethedurationof atransaction.
AD 32address/datalines,which may beoptionallyincreasedto 64.
C/BE# 4command/byte-enablelines(8 for a64-bitbus).
IRDY#, TRDY# Initiator-readyandTarget-readysignals.
DEVSEL# A responsefromthedeviceindicatingthat it hasrecognizeditsaddressand is ready for a datatransfertransaction.
IDSEL# InitializationDeviceSelect.
58
Table 4.4 The SCSI bus signals.
Category Name F unction
Data DB(0) toDB(7)
Data lines: Carry one byte of informationduring the information transfer phase and
iden tify device during arbitration,selection andreselection phases
DB(P) Parity bit for the data busPhase BSY Busy: Asserted when the bus is not free
SEL Selection: Asserted during selection andreselection
Informationtype
C/D Control/Data: Asserted during transfer ofcontrol information (command,status ormessage)
MSG Message: indicates that the information beingtransferredis a message
Handshake REQ Request: Asserted by a target to request a datatransfer cycle
A CK Ackno wledge: Asserted by the initiator when ithas completeda data transferoperation
Directionoftransfer
I/O Input/Output: Asserted to indicate an inputoperation (relative to the initiator)
Other A TN Attention: Asserted by an initiator when itwishes to send a message to a target
RST Reset: Causes all device controls to disconnectfrom the bus and assume their start-upstate
–
–
–
–
–
–
–
–
–
–
–
–
Related Documents
