Performance analysis of Microcontroller and FPGA based Signal Processing - A case study on FIR Filter Design and Implementation

2015 International Conference on Industrial Instrumentation and Control (ICIC) Col/ege of Engineering Pune, India. May 28-30,2015

Performance analysis of Microcontroller and FPGA

based Signal Processing A case study on FIR Filter Design and Implementation

Visiting Prof. Shashank Pujari Department of Technology

Savitribai Phule University of Pune

Abstract-Embedded Computing platforms based on Microcontroller, Field Programmable Gate Array (FPGA) and Digital Signal Processor (DSP) are subjects of interest at Under Graduate(UG) and Post Graduate(PG) levels in Electronics and Communication Engineering. Real Time Signal Processing algorithms are generally implemented on any one of these platforms. The paper presents a comparative performance analysis between Microcontroller and FPGA based signal processing by way of a case study on Finite Impulse Response (FIR) fIlter implementation. Microcontrollers are basically sequential and FPGAs are parallel computing platforms. This paper highlights the parallelism feature of FPGA to prove its efficiency against Microcontroller for signal processing applications.

Keywords- Microcontroller;FPGA; Signal Processing;FIR Filter

I. INTRODUCTION

Embedded system design is a subject of interest at Under

Graduate (UG) and Post Graduate (PG) level in Electronics and Conununication Engineering. Embedded systems can be categorized into three major domains of Computing, Control and Conununication. These three domains can be implemented

on any one of the three major hardware platforms namely Microcontroller, Digital Signal Processor (DSP) and Field Progranunable Gate Array (FPGA) in Lab environment. Model

Based Design approach using PROTEUS modeling tool is a convenient approach to implement experimental projects at initial stages before testing on any of the above three hardware target. The paper presents a step by step learning methodology

for Microcontroller based DSP design methodology by way of a case study on FIR filter design. This approach can be extended for other complex projects.

Embedded computing is the key thrust area of Electronics

Course Curriculum and software skill development on three major hardware platforms, namely Microcontroller, FPGA and

DSP processors, is essential. Microcontrollers and DSP processors have evolved from Microprocessor, where as FPGA have evolved from progranunable logic such as Progranunable

Array Logic (PAL) and Complex Progranunable Logic Device (CPLD). These platforms have their respective suite of

*Post Graduate Students at Department of Technology,SPUP,Pune-4 I I 007,India

978-1-4799-7165-7/15/$31.00 ©2015 IEEE 252

Ms. Ashwini Yeotkar* Ms. Vrushali Shingare*

Ms. Sana Momin * Mr. Bapu Kokare*

Integrated Development Environment (IDE) facilitating in easy software and hardware development. Among many tools, PROTEUS is a Model Based Design tool popular among learners of Embedded Computing. On the language front, 'C'

Software Progranuning Language (SPL) and VHDLNERILOG Hardware Description Language (HDL) are used for writing software code for MicrocontrollerlDSP and FPGA respectively. Among many compilers 'KEIL' is a compiler for compiling Embedded 'C' program for many Microcontrollers families. Similarly Xilinx's ISE tool and Altera's Quartus tool are IDE tools for FPGA devices of respective manufacturers. Texas "Code composer" IDE tool is used for developing program for Texas DSP processor.

The present work is focused on the comparative study of implementation of a DSP algorithm on a sequential processor

architecture i.e. Microcontroller and parallel logic architecture i.e. FPGA. The work has been carried out using MATLAB,

SIMULINK and PROTEUS modeling tools and KEIL compiler. The ARM7 LPC2138 Microcontroller hardware platform and ALTERA CYCLONE-II FPGA platform [1] have been used to carry out experiments. An 8 order FIR filter for Low Pass (LP), High Pass (HP), Band Pass (HP) and Band Stop (BS) filter have been designed on both ARM7 and FPGA KITs. The experimental result presented, shows the limitation of Microcontroller architecture over the FPGA architecture.

A. Types of Filters

II. DIGITAL FILTERS

A digital filter performs filtering function on data by attenuating certain bands of frequencies. Filters are often

classified into one of following four types as shown in Fig-I.

• A low pass filter to remove high frequency noise from a speech signal

• A High pass filter to remove low frequency signal • A band stop filters to remove 50Hz mains hum from an

ECG (heartbeat) signal. • A band pass (BP) filter to extract a digitized band

limited intermediate frequency (IF) modulated signal for mobile radio.

Figure I . Types of Filters.

B. Digital Filters

There are four types of Digital filters.

• Finite Impulse Response (FIR): Non-recursive linear filter (i.e. no feedback present)

• Infinite Impulse Response (IIR): Recursive linear filter (i.e. with feedback)

• Adaptive Digital Filter: A self learning filter that adapts itself to a desired signal.

• Non-Linear Filter: A filter that can perform non-linear operations (median filter, minimax filters). In a median filter, the last N samples are stored in an array, they are then ordered from largest to smallest and the output is the middle value in the array. This type of filter can be useful for removing some forms of impulsive noise (scratches on an audio track), and is also used in a 2-D form for image processing.

C. Digital FIR Filters

A FIR filter performs a weighted average (convolution) on a

window of N data samples. For a discrete-time FIR filter, the output is a weighted sum of the current and a finite number of previous values of the input. The operation is described by the equation (1), which defines the output sequence y[k] in terms of its input sequence x[ n].

y[k] = wO x[n] + wI x[n-l] + . .... + wn xenoN]

N-l y(k) = I wnx(k-n)

n=O

Where:

x[n] is the input signal, y[k] is the output signal, Wn are the filter coefficients, known as tap weights.

(1)

N is the filter order; Nth-order filter has (N+ 1) terms on the right-hand side, which are also referred as taps. Fig-2 shows a

7th order/8-tap filter.

253

Figure 2. 8 order FIR Filter with coefficients.

0. 122

Y [k]

D. Filter design & generation of coefficients using MATLAB

FDATOOL in MATLAB provided by Mathworks is a

Graphical User Interface (GUI) that allows designing digital

filter. By typing fdatool in MATLAB command window, filter

design window appears as shown in Fig-3. User can select type of filter, filter order, design method FIR or IIR filter, frequency specification, quantizing option, rounding mode, and overflow mode etc, according to the need of filter application. For e.g. in this project, Low Pass filter, 7 order, 1 KHz Fpass and S KHz Fstop, quantizing option as fixed point arithmetic,

rounding mode as floor and overflow mode as saturate is specified. Then clicking on 'design filter' option, the required filter is designed. The filter coefficients can be taken by

exporting them to work space by specifying a default variable name 'Num'. Then by writing the command num2hex(q,

variable name), the coefficients in hexadecimal format are obtained as given here.

E. Command window opearations in MA TLAB

> > q=quantizer

q = DataMode = fixed

RoundMode = floor OverflowMode = saturate

Format = [16 IS]

» Num Num =

Columns 1 through 8 0.1228, 0.0887, 0.1072, 0.1172, 0.1172, 0.1072, 0.0887, 0.1228

» nl=num2hex(q,Num) nl = OxOFB8, OxOBSB, OxODB8, OxOFOO, OxOFOO, OxODB8, OxOBSB, OxOFB8

.... -.-' .... -- ..... C(j:g.� ........ .:.0 0 II �1Ii1 i1 11'1-W r . i.1 . I5I� 1(1

Figure 3. FDA TOOL window.

.-·1 -, , - .�:-

III. MODEL BASED DESIGN APPROACH OF FIR

FILTER DESIGN USING SIMULINK TOOL

Fig-4 shows the SIMULINK model of the Filter design. There are four main stages of the SIMULINK model. They are Audio source file:-Reads multi-media files containing audio file in 'wav' format. Audio filter: it is a filter design tool which can design and operate different types of filter. Spectrum

analyzer: it is the equipment in which frequency spectrum of signal can be observed. Headphone and speaker: the headphone block is used to listen to the unprocessed or processed audio

output on Computer Headphone. Here different filters such as LP, HP, BP, BS filters are designed and changes are observed

at the headphone output of the computer as well as on the spectrum analyzer as shown in Fig-5, Fig-6, Fig-7 and Fig-8.

Figure 4. SIMULINK MODEL OF FIR FILTER.

�or-------���------�------���----�

I======�

II -- fllt.,ed

-.\0 � +- -- o"g,nal

10 15 20 Fr�m8: 7'Z2 Fr8qu9ncy (kHl)

Figure 5. Low Pass Fpass= I Khz, Fstop = 5 Khz, Order = 7

254

-30 +-

-40

-60

� -60

�. -70 � " = U> �

� -80

" .� �

-90 =

� -100

-110

-120

10 15 20 Fr�m8: 248 Fr8qu9ncy (kHl)

Figure 6. High Pass, Fpass= 5 Khz, Fstop = I Khz, Order = 7

-30r-----------------------�+�----r=======�

�

-6[] �-

� -7[]

t -80

� -90

-100

-110

-120 '

F"m8: 448

+

+

10 15 Fr8qu oncy (kH l)

Figure 7. Band Pass, Fstop 1= 500 Hz, Fpassl = 3.8 Khz, Fpass2= 3.0 KHz , Fstop2= 7.00 KHz, Order = 40

�o

-.\0 +

-60

� -60 -"

., '"

-70 � " =

� -80 -g .� -90 :!i'

-100

1 -11D

-120

10 15 20 Fr�m8: 246 Fr8qu9ncy (kHl)

Figure 8. Band Stop, Fpassl= 500 Hz, Fstopl = 3.0 Khz, Fstop2= 3.9 KHz, Fpass2= 7.00 KHz, Order = 35

IV. MODEL BASED DESIGN APPROACH FOR

MICRO CONTROLLER HARDW ARE AND SOFTWARE

Model based design approach is an ideal approach for

Embedded System Design. There are many system modeling tools available from various vendors. These tools facilitate the

design of hardware and software before actual physical implementation of the system. PROTEUS tool is used for this

project. The PROTEUS tool also provides virtual instruments like Waveform generator to generate various types of signals, Oscilloscope and Logic analyzer to monitor analog and digital signals. Familiarization of the PROTEUS tool is facilitated by

host of readymade examples, which comes free with the tool.

KEIL compiler is used for coding in 'C' language. The generated hex code by the KEIL compiler is used to configure

the virtual Microcontroller in PROTEUS tool.

Fig-9 shows the hardware schematic of the system having ARM7 LPC2138 Microcontroller from NXP semiconductor. The Microcontroller is interfaced with Key board, LCD,

Virtual Hyper Terminal for serial communication, Signal generator and Oscilloscope. Sine wave source at different frequencies i.e., 1 KHz, 3 KHz, 5 KHz and 10 KHz is selected by switches and applied to the ADC input of the Microcontroller. The filtered response at the DAC output of the Microcontroller is observed on the Oscilloscope. Fig-IO, Fig-

11 and Fig-12 shows the Low Pass filter response at 1 KHz, 3

KHz and 5 KHz respectively. A 4x4 Matrix keyboard is used to

select different filter types such as LP, HP, BP and BS filter. The LCD displays the current filter type selected. Virtual

terminal shows filter coefficients.

Figure 9. SCHEMATIC OF MICROCONTROLLER SYSTEM

Figure 10. TOP = 1 KHz ADC INPUT, BOTTOM= 1 KHz DAC OUTPUT

255

Figure I I. TOP = 3 KHz ADC INPUT, BOTTOM= 3 KHz DAC OUTPUT

Figure 12. TOP = 5 KHz ADC INPUT, BOTTOM= 5 KHz DAC OUTPUT

The software flow chart is shown in Fig-l3. Device driver

for Keypad, LCD display, Serial communication, ADC and DAC are coded, compiled and debugged individually and then integrated in Main program. Like in every embedded system design, the first step is to initialize all the peripherals connected to the processor, here LCD, Keypad, ADC, DAC and serial

communication are initialized. The filter type is selected by the user. In next step, the FIR computation is executed. The FIR code is explained in section VI.

SERIAL COMMUNIC

ATJON

LCD

Figure 13. SOFTWARE FLOW CHART

ADC& DAC

KBD

V. IMPLEMENTATION, TESTING & RESULT

COMPUTER

Figure 14. HARDWARE SETUP

The hardware set up is shown in Fig-14. Sine wave signal

from function generator is applied at the ADC input of the ARM7 KIT. The DAC signal output is connected to the

oscilloscope. After successful compilation of the program, the

generated hex code by the KEIL compiler is downloaded to the

ARM7 LPC 2138 Microcontroller flash memory through serial cable.

The LP, HP, BP and BS filtered output at different frequencies and corresponding peak to peak voltage magnitude is monitored on the oscilloscope.

A. Low pass filter Observation:

Filter is designed according to Fpass as 0.1 kHz and Fstop as

0.5 kHz. Fig-IS, Fig-16 and Fig-17 shows the oscilloscope

screen shot of Low pass filter response at 100 Hz, 200 Hz and 300 Hz respectively. The top waveform shows the filtered

output and the bottom waveform shows the input sine wave of Waveform Generator.

Figure 15. Low pass filter response at 100 Hz, Top = DAC Filtered output, Bottom = ADC input

256

Figure 16. Low pass filter response at 200 Hz, Top = DAC Filtered output, Bottom = ADC input

Figure 17. Low pass filter response at 300 Hz, Top = DAC Filtered output, Bottom = ADC input

From the above readings it is seen that the designed FIR

Low Pass filter response behavior is as expected.

VI. PERFORMANCE ANALYSIS

The comparative performance analysis of the FIR code used in Microcontroller and FPGA is presented here.

A. C Code implementation on Micorocntroller

The C code and the flow chart out lined in Fig-18 shows two

major loops, first loop is an N order FIFO like shift operation and the second loop is Multiply and Accumulate (MAC) FIR convolution computation. For N=8 and CPU clock at 60 MHz, these two loops take approx. 15 usec each, as observed on the scope, totaling to a 30 usec ADC sampling window. The sampling window is a function of the order of the filter(N), computing accuracy (Fixed Point/Floating Point arithmetic), CPU clock and Compiler efficiency for optimum ARM7 code generation. The maximum frequency of filter operation is restricted to 1/30 usec = approx. 30 KHz, in spite of the fact that LPC 2138 ARM7 microcontroller ADC sampling speed is

112.4 usec= 416 KHz. It is observed that for N=16, the time of

computation window increases to approx. 60 usec, thus further

restricting the maximum frequency of input to 1/60 usec =

approx. 16 KHz. Although a higher order filter would enhance the accuracy, though the maximum frequency of signal is reduced from 30 KHz to 16 KHz in this case.

lowpass: for (i = N-l; i > 0; i--) {x[i] = x[i-1];} II N = 8, Shifter x[O] = GetAdcReadingO; II Read ADC

fir_out = 0; for (i = 0; i <N; i++) { y[i] = x[i] * coeff[i]; IICompute FIR algorithm

fir_out = y[i] + fir_out;}

fir_out = fir_out » IS; DACR = (fir_out «6) ;

goto lowpass ;

8 Instruction Cycles

COEFFICIENTS

8 Instruction Cycles

DATA INPUT

IIRounding off

IIDAC bit adjustment

... ::­I I

MAC UNIT

DATA OUTPUT

Figure 18. SEQUENTIAL 8 ORDER FIR COMPUTATION

B. VERILOG Code implementation on FPGA

Referring [1], the FPGA VERILOG code component given below and the architecture is shown in Fig-19. It can be seen that the FIR result output is available at the processing clock speed i.e., in present case FPGA is running at SO MHz. The

number of multipliers and adders required in the present case

are 8 and 3 respectively. These resources are available in large numbers in FPGA. For e.g. Altera CYCLONE-II

EP2C3SF6728C FPGA can accommodate a 40 order FIR filters at a clock speed more than SO MHz [1].

mult_add_I(.clockO(SO MHz), dataa_O(idata_in), .datab _ O( coefC O),.datab _1 (coefC 1 ),.datab _ 2( coefC 2),.datab_ 3( coefC 3),.result(mult_ add _resultO),.shiftouta(shift _data));

mult_ add _ 2(.clockO(SO MHz), .dataa _ O(shift _data), . datab _ O( coefC 4),. datab _1 ( coefC S),. datab _ 2( coefC 6),. datab _ 3( coefC 7),.result(mult_ add JesuIt 1 ));

adder _1 (.clock( clock),.dataa(mult_add JesultO),.datab(mult_a dd JesultI ),.result(fir Jesult));

assign firJesultJounded = firJesult[30:IS];

257

HR OUTPUT

Figure 19. PARALLEL 8 ORDER FIR COMPUTATION

Table -I

Parameters Performance Comparison

Microcontroller@60 MHz FPGA@50MHz Signal Fmax Approx 30 KHz 50 MHz

Latency Approx. 30 usec 3 Clocks = 30 nsec

Sampling rate Filter order dependent Filter order independent

Performance Poor Good

VII. CONCLUSION & FUTURESCOPE

The work presented here explains basic design and implementations of FIR filter on Microcontroller. The project

was developed with the help of many hardware, software and modeling tools such as ARM7 KIT, KEIL, MATLAB,

SIMULINK, FDATOOL and PROTEUS. A comparative

performance analysis of the FIR filter design was done between Microcontroller and FPGA as listed in Table-I, which clearly demonstrate that FPGAs are more efficient than Microcontroller for signal processing applications.

The filter code can be optimized by using suitable assembly instruction of ARM7 in place of C code. FIR filter can be implemented on a DSP processor and performance analysis can be done between Microcontroller, FPGA and DSP processor in

terms of speed, resource, power, and cost.

ACKNOWLEDGMENT

Authors wish to thank Department of Technology at SPUP University for providing lab facility and guidance to

carry out the project.

REFERENCES

[I] Shashank Shekhar Pujari, Prangya Paramita Muduli, Amruta Panda,Rasmita Badhai,Sofia Nayak, Yougajyoty Sahoo, Design & Implementation of FIR Filters using On-Board ADC-DAC & FPGA, International Conference on Information Communication & Embedded Systems (ICICES 20 14), ISBN No.978-1-4 799-3834-6/14©20 14 IEEE.

[2] U.Meyer-Baese, Digital Signal Processing with Field Programmable Gate Arrays, Springer.