PEMANCAR AMPLITUDO MODULASI DENGAN FREQUENCY HOPPING TUGAS AKHIR Diajukan untuk memenuhi salah satu syarat memperoleh gelar Sarjana Teknik pada Program Studi Teknik Elektro Disusun oleh ANDREAS RONY MARLINO NIM : 015114033 PROGRAM STUDI TEKNIK ELEKTRO FAKULTAS SAINS DAN TEKNOLOGI UNIVERSITAS SANATA DHARMA YOGYAKARTA 2007
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PEMANCAR AMPLITUDO MODULASI DENGANAmplitude Modulation), modulasi frekuensi (FM-Frequency Modulation) dan modulasi fasa (PM-Phase Modulation). Pada penelitian ini dibuat sebuah pemancar
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PEMANCAR AMPLITUDO MODULASI DENGAN
FREQUENCY HOPPING
TUGAS AKHIR
Diajukan untuk memenuhi salah satu syarat
memperoleh gelar Sarjana Teknik pada
Program Studi Teknik Elektro
Disusun oleh
ANDREAS RONY MARLINO
NIM : 015114033
PROGRAM STUDI TEKNIK ELEKTRO
FAKULTAS SAINS DAN TEKNOLOGI
UNIVERSITAS SANATA DHARMA
YOGYAKARTA
2007
AM TRANSMITTER WITH FREQUENCY HOPPING
FINAL PROJECT
Presented as Partial Fulfillment of the Requirements
to obstain the Sarjana Teknik Degree
in Electrical Engineering
By :
ANDREAS RONY MARLINO
Student Number : 015114033
ELECTRICAL ENGINEERING STUDY PROGRAM
SCIENCE AND TECHNOLOGY FACULTY
SANATA DHARMA UNIVERSITY
YOGYAKARTA
2007
ii
iii
PERNYATAAN KEASLIAN KARYA
“Saya menyatakan dengan sesungguhnya bahwa tugas akhir yang saya tulis ini
tidak memuat karya atau bagian karya orang lain, kecuali yang telah disebutkan dalam
kutipan dan daftar pustaka, sebagaimana layaknya karya ilmiah”
Yogyakarta, September 2007
Penulis,
Andreas Rony Marlino
v
Tugas akhir ini dipersembahkan untuk :
Yesus Kristus dan Bunda Maria atas karuniaNya
Kedua orang tuaku tercinta (ST,Marli Subroto dan Lusia Ema
Sudarmi) Kedua kakakku (Mas Didik Mbak Yeni dan Ms Heru)
Adikku (Dony “Itong”)
Widy.......
Teman-temanku semua
yang selalu memberikan semangat, dorongan, dan doa.
Data spektrum frekuensi sinyal informasi pada penerima AM
Frekuensi carrier pemancar 1000 KHz
1. sinyal informasi 1 kHz
2. sinyal informasi 2 kHz
3. sinyal informasi 4 kHz
4. sinyal informasi 5 kHz
5. sinyal informasi 6 kHz
6. sinyal informasi 7 kHz
7. sinyal informasi 8 kHz
Frekuensi carrier pemancar 1050 KHz
1. sinyal informasi 1 kHz
2. sinyal informasi 2 kHz
3. sinyal informasi 4 kHz
4. sinyal informasi 5 kHz
5. sinyal informasi 6 kHz
6. sinyal informasi 7 kHz
7. sinyal informasi 8 kHz
Andreas Rony Marlino 015114033 <Rev Code>
PEMANCAR AM DENGAN FREQUENCY HOPPING
Custom
1 1Monday , October 01, 2007
Title
Size Document Number Rev
Date: Sheet of
DIV 1000
R1010K
Y110.240Mhz
C1660pF
R111K
C1539pFC20
100pF
J9
9V
1
R3510K
R81K
R91.6K
T1
OT426
1 5
6
4 8
ANTENA
C19
1uF
R32
10K
VCC_BAR
R2510K
R3110K
C180.1uF
R17
100K
Q3IRF5102
13
L2
2.5mH
C5
1.6nF
R3310K
C61.8nF
U12
74HC4046/SO
34
14
6
75
1112
12
13
9
1015
168
CINVCOUT
SIN
CX
CXINHR1R2
PPP1
P2
VCOIN
DEMOZEN
VD
DVS
S
L11uH
J35
VCC (5V)1
PEMBAGI TERPROGRAM
C210.1uF
U13LM555/TO
2
5
3
7
6
4 81
TR
CV
Q
DIS
THR
R
VC
CG
ND
VCC_BAR
OSILATORREFERENSI
R627k
U10
CD4060B/SO
812
1516
45
6
7
1314
123
91011
GN
DRST
Q10VDD
Q6Q5
Q7
Q4
Q9Q8
Q12Q13Q14
Ø0Ø0Ø1
Q1
2n3904
3
2
1
XTAL OSC
R34
10K
DIV 10
U5
74LS90
141
2367
129811
510
AB
R0(1)R0(2)R9(1)R9(2)
QAQBQCQD
VCC
GN
D
TIMER
U8TCP9122P
1
45
10
12131415161718
23
6789
11
VDD
B0C0
D1
B2C2D2A3B3
POUTGND
PINA0
D0A1B1C1
A2
R18
10K
C4
100pF
R3010K
TRANSISTOR SEBAGAI SAKLAR
Q2
2n3904
3
2
1
R710K
Q13940
MODULATOR
VCO
C7100uf
R23
10K
R271Meg1
3
2
2N3904 / M
MB
T3904 / MM
PQ
3904 / PZT3904
Discrete POWER & SignalTechnologies
N
2N3904 MMBT3904
MMPQ3904 PZT3904
NPN General Purpose Amplifier
This device is designed as a general purpose amplifier and switch.The useful dynamic range extends to 100 mA as a switch and to100 MHz as an amplifier. Sourced from Process 23.
Absolute Maximum Ratings* TA = 25°C unless otherwise noted
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
NOTES :1) These ratings are based on a maximum junction temperature of 150 degrees C.2) These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
Symbol Parameter Value UnitsVCEO Collector-Emitter Voltage 40 V
VCBO Collector-Base Voltage 60 V
VEBO Emitter-Base Voltage 6.0 V
IC Collector Current - Continuous 200 mA
TJ, Tstg Operating and Storage Junction Temperature Range -55 to +150 °C
CB E
TO-92
BC
C
SOT-223
E
C
B
E
SOT-23Mark: 1A
CC
CC
CC
C C
SOIC-16
EB
EB
EB
E B
2N3904 / M
MB
T3904 / MM
PQ
3904 / PZT3904
NPN General Purpose Amplifier(continued)
Electrical Characteristics TA = 25°C unless otherwise noted
Symbol Parameter Test Conditions Min Max Units
V(BR)CEO Collector-Emitter Breakdown Voltage IC = 1.0 mA, IB = 0 40 V
V(BR)CBO Collector-Base Breakdown Voltage IC = 10 µA, IE = 0 60 V
V(BR)EBO Emitter-Base Breakdown Voltage IE = 10 µA, IC = 0 6.0 V
IBL Base Cutoff Current VCE = 30 V, VEB = 0 50 nA
ICEX Collector Cutoff Current VCE = 30 V, VEB = 0 50 nA
General DescriptionEach of these monolithic counters contains four master-
slave flip-flops and additional gating to provide a divide-by-
two counter and a three-stage binary counter for which the
count cycle length is divide-by-five for the ’LS90 and divide-
by-eight for the ’LS93.
All of these counters have a gated zero reset and the LS90
also has gated set-to-nine inputs for use in BCD nine’s com-
plement applications.
To use their maximum count length (decade or four bit bina-
ry), the B input is connected to the QA output. The input
count pulses are applied to input A and the outputs are as
described in the appropriate truth table. A symmetrical di-
vide-by-ten count can be obtained from the ’LS90 counters
by connecting the QD output to the A input and applying the
input count to the B input which gives a divide-by-ten square
wave at output QA.
FeaturesY Typical power dissipation 45 mWY Count frequency 42 MHz
Connection Diagrams (Dual-In-Line Packages)
TL/F/6381–1
Order Number DM74LS90M or DM74LS90N
See NS Package Number M14A or N14A
TL/F/6381–2
Order Number DM74LS93M or DM74LS93N
See NS Package Number M14A or N14A
C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage 7V
Input Voltage (Reset) 7V
Input Voltage (A or B) 5.5V
Operating Free Air Temperature Range
DM74LS 0§C to a70§CStorage Temperature Range b65§C to a150§C
Note: The ‘‘Absolute Maximum Ratings’’ are those valuesbeyond which the safety of the device cannot be guaran-teed. The device should not be operated at these limits. Theparametric values defined in the ‘‘Electrical Characteristics’’table are not guaranteed at the absolute maximum ratings.The ‘‘Recommended Operating Conditions’’ table will definethe conditions for actual device operation.
Recommended Operating Conditions
Symbol ParameterDM74LS90
UnitsMin Nom Max
VCC Supply Voltage 4.75 5 5.25 V
VIH High Level Input Voltage 2 V
VIL Low Level Input Voltage 0.8 V
IOH High Level Output Current b0.4 mA
IOL Low Level Output Current 8 mA
fCLK Clock Frequency (Note 1) A to QA 0 32MHz
B to QB 0 16
fCLK Clock Frequency (Note 2) A to QA 0 20MHz
B to QB 0 10
tW Pulse Width (Note 1) A 15
B 30 ns
Reset 15
tW Pulse Width (Note 2) A 25
B 50 ns
Reset 25
tREL Reset Release Time (Note 1) 25 ns
tREL Reset Release Time (Note 2) 35 ns
TA Free Air Operating Temperature 0 70 §CNote 1: CL e 15 pF, RL e 2 kX, TA e 25§C and VCC e 5V.
Note 2: CL e 50 pF, RL e 2 kX, TA e 25§C and VCC e 5V.
’LS90 Electrical Characteristicsover recommended operating free air temperature range (unless otherwise noted)
Symbol Parameter Conditions MinTyp
Max Units(Note 1)
VI Input Clamp Voltage VCC e Min, II e b18 mA b1.5 V
VOH High Level Output VCC e Min, IOH e Max2.7 3.4 V
Voltage VIL e Max, VIH e Min
VOL Low Level Output VCC e Min, IOL e Max
Voltage VIL e Max, VIH e Min 0.35 0.5V
(Note 4)
IOL e 4 mA, VCC e Min 0.25 0.4
II Input Current @ Max VCC e Max, VI e 7V Reset 0.1
Input VoltageVCC e Max A 0.2 mA
VI e 5.5VB 0.4
2
’LS90 Electrical Characteristicsover recommended operating free air temperature range (unless otherwise noted) (Continued)
Symbol Parameter Conditions MinTyp
Max Units(Note 1)
IIH High Level Input VCC e Max, VI e 2.7V Reset 20
CurrentA 40 mA
B 80
IIL Low Level Input VCC e Max, VI e 0.4V Reset b0.4
CurrentA b2.4 mA
B b3.2
IOS Short Circuit VCC e Max (Note 2)b20 b100 mA
Output Current
ICC Supply Current VCC e Max (Note 3) 9 15 mA
Note 1: All typicals are at VCC e 5V, TA e 25§C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V and all other inputs grounded.
Note 4: QA outputs are tested at IOL e Max plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability.
’LS90 Switching Characteristicsat VCC e 5V and TA e 25§C (See Section 1 for Test Waveforms and Output Load)
From (Input)RL e 2 kX
Symbol Parameter To (Output) CL e 15 pF CL e 50 pF Units
Min Max Min Max
fMAX Maximum Clock A to QA 32 20MHz
Frequency B to QB 16 10
tPLH Propagation Delay TimeA to QA 16 20 ns
Low to High Level Output
tPHL Propagation Delay TimeA to QA 18 24 ns
High to Low Level Output
tPLH Propagation Delay TimeA to QD 48 52 ns
Low to High Level Output
tPHL Propagation Delay TimeA to QD 50 60 ns
High to Low Level Output
tPLH Propagation Delay TimeB to QB 16 23 ns
Low to High Level Output
tPHL Propagation Delay TimeB to QB 21 30 ns
High to Low Level Output
tPLH Propagation Delay TimeB to QC 32 37 ns
Low to High Level Output
tPHL Propagation Delay TimeB to QC 35 44 ns
High to Low Level Output
tPLH Propagation Delay TimeB to QD 32 36 ns
Low to High Level Output
tPHL Propagation Delay TimeB to QD 35 44 ns
High to Low Level Output
tPLH Propagation Delay Time SET-9 to30 35 ns
Low to High Level Output QA, QD
tPHL Propagation Delay Time SET-9 to40 48 ns
High to Low Level Output QB, QC
tPHL Propagation Delay Time SET-0 to40 52 ns
High to Low Level Output Any Q
3
Recommended Operating Conditions
Symbol ParameterDM74LS93
UnitsMin Nom Max
VCC Supply Voltage 4.75 5 5.25 V
VIH High Level Input Voltage 2 V
VIL Low Level Input Voltage 0.8 V
IOH High Level Output Current b0.4 mA
IOL Low Level Output Current 8 mA
fCLK Clock Frequency (Note 1) A to QA 0 32
B to QB 0 16MHz
fCLK Clock Frequency (Note 2) A to QA 0 20
B to QB 0 10
tW Pulse Width (Note 1) A 15
B 30 ns
Reset 15
tW Pulse Width (Note 2) A 25
B 50 ns
Reset 25
tREL Reset Release Time (Note 1) 25 ns
tREL Reset Release Time (Note 2) 35 ns
TA Free Air Operating Temperature 0 70 §CNote 1: CL e 15 pF, RL e 2 kX, TA e 25§C and VCC e 5V.
Note 2: CL e 50 pF, RL e 2 kX, TA e 25§C and VCC e 5V.
’LS93 Electrical Characteristicsover recommended operating free air temperature range (unless otherwise noted)
Symbol Parameter Conditions MinTyp
Max Units(Note 1)
VI Input Clamp Voltage VCC e Min, II e b18 mA b1.5 V
VOH High Level Output VCC e Min, IOH e Max2.7 3.4 V
Voltage VIL e Max, VIH e Min
VOL Low Level Output VCC e Min, IOL e Max
Voltage VIL e Max, VIH e Min 0.35 0.5 V
(Note 4)
IOL e 4 mA, VCC e Min 0.25 0.4
II Input Current @Max VCC e Max, VI e 7V Reset 0.1
Input VoltageVCC e Max A 0.2 mA
VI e 5.5VB 0.4
IIH High Level Input VCC e Max Reset 20
Current VI e 2.7VA 40 mA
B 80
4
’LS93 Electrical Characteristicsover recommended operating free air temperature range (unless otherwise noted) (Continued)
Symbol Parameter Conditions MinTyp
Max Units(Note 1)
IIL Low Level Input VCC e Max, VI e 0.4V Reset b0.4
CurrentA b2.4 mA
B b1.6
IOS Short Circuit VCC e Max (Note 2)b20 b100 mA
Output Current
ICC Supply Current VCC e Max (Note 3) 9 15 mA
Note 1: All typicals are at VCC e 5V, TA e 25§C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V and all other inputs grounded.
Note 4: QA outputs are tested at IOL e max plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability.
’LS93 Switching Characteristicsat VCC e 5V and TA e 25§C (See Section 1 for Test Waveforms and Output Load)
From (Input)RL e 2 kX
Symbol Parameter To (Output) CL e 15 pF CL e 50 pF Units
Min Max Min Max
fMAX Maximum Clock A to QA 32 20MHz
FrequencyB to QB 16 10
tPLH Propagation Delay TimeA to QA 16 20 ns
Low to High Level Output
tPHL Propagation Delay TimeA to QA 18 24 ns
High to Low Level Output
tPLH Propagation Delay TimeA to QD 70 85 ns
Low to High Level Output
tPHL Propagation Delay TimeA to QD 70 90 ns
High to Low Level Output
tPLH Propagation Delay TimeB to QB 16 23 ns
Low to High Level Output
tPHL Propagation Delay TimeB to QB 21 30 ns
High to Low Level Output
tPLH Propagation Delay TimeB to QC 32 37 ns
Low to High Level Output
tPHL Propagation Delay TimeB to QC 35 44 ns
High to Low Level Output
tPLH Propagation Delay TimeB to QD 51 60 ns
Low to High Level Output
tPHL Propagation Delay TimeB to QD 51 70 ns
High to Low Level Output
tPHL Propagation Delay Time SET-0 to40 52 ns
High to Low Level Output Any Q
5
Function Tables
LS90
BCD Count Sequence
(See Note A)
CountOutput
QD QC QB QA
0 L L L L
1 L L L H
2 L L H L
3 L L H H
4 L H L L
5 L H L H
6 L H H L
7 L H H H
8 H L L L
9 H L L H
LS90
Bi-Quinary (5-2)
(See Note B)
CountOutput
QA QD QC QB
0 L L L L
1 L L L H
2 L L H L
3 L L H H
4 L H L L
5 H L L L
6 H L L H
7 H L H L
8 H L H H
9 H H L L
LS93
Count Sequence
(See Note C)
CountOutput
QD QC QB QA
0 L L L L
1 L L L H
2 L L H L
3 L L H H
4 L H L L
5 L H L H
6 L H H L
7 L H H H
8 H L L L
9 H L L H
10 H L H L
11 H L H H
12 H H L L
13 H H L H
14 H H H L
15 H H H H
Note A: Output QA is connected to input B for BCD count.
Note B: Output QD is connected to input A for bi-quinary count.
Note C: Output QA is connected to input B.
Note D: H e High Level, L e Low Level, X e Don’t Care.
LS90
Reset/Count Truth Table
Reset Inputs Output
R0(1) R0(2) R9(1) R9(2) QD QC QB QA
H H L X L L L L
H H X L L L L L
X X H H H L L H
X L X L COUNT
L X L X COUNT
L X X L COUNT
X L L X COUNT
LS93
Reset/Count Truth Table
Reset Inputs Output
R0(1) R0(2) QD QC QB QA
H H L L L L
L X COUNT
X L COUNT
6
Logic Diagrams
LS90
TL/F/6381–3
LS93
TL/F/6381–4
The J and K inputs shown without connection are for reference only and are functionally at a high level.
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
National Semiconductor National Semiconductor National Semiconductor National SemiconductorCorporation Europe Hong Kong Ltd. Japan Ltd.1111 West Bardin Road Fax: (a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309Arlington, TX 76017 Email: cnjwge@ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408Tel: 1(800) 272-9959 Deutsch Tel: (a49) 0-180-530 85 85 Tsimshatsui, KowloonFax: 1(800) 737-7018 English Tel: (a49) 0-180-532 78 32 Hong Kong
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
General DescriptionThese devices are digitally controlled analog switches uti-lizing advanced silicon-gate CMOS technology. Theseswitches have low “on” resistance and low “off” leakages.They are bidirectional switches, thus any analog input maybe used as an output and visa-versa. Also the 4066switches contain linearization circuitry which lowers the“on” resistance and increases switch linearity. The 4066devices allow control of up to 12V (peak) analog signalswith digital control signals of the same range. Each switchhas its own control input which disables each switch whenlow. All analog inputs and outputs and digital inputs areprotected from electrostatic damage by diodes to VCC andground.
Features Typical switch enable time: 15 ns
Wide analog input voltage range: 0–12V
Low “on” resistance: 30 typ. ('4066)
Low quiescent current: 80 µA maximum (74VHC)
Matched switch characteristics
Individual switch controls
Pin and function compatible with the 74HC4066
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Note 1: Absolute Maximum Ratings are those values beyond which dam-age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package: −12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
Note 4: For a power supply of 5V ± 10% the worst case on resistance (RON) occurs for VHC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current occurs
for CMOS at the higher voltage and so the 5.5V values should be used.
Note 5: At supply voltages (VCC – GND) approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended that
these devices be used to transmit digital only when using these supply voltages.
Supply Voltage (VCC) −0.5 to +15V
DC Control Input Voltage (VIN) −1.5 to VCC + 1.5V
DC Switch I/O Voltage (VIO) VEE − 0.5 to VCC + 0.5V
Clamp Diode Current (IIK, IOK) ±20 mA
DC Output Current, per pin (IOUT) ±25 mA
DC VCC or GND Current, per pin (ICC) ±50 mA
Storage Temperature Range (TSTG) −65°C to +150°CPower Dissipation (PD) (Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (TL)
(Soldering 10 seconds) 260°C
Min Max Units
Supply Voltage (VCC) 2 12 V
DC Input or Output Voltage 0 VCC V
(VIN, VOUT)
Operating Temperature Range (TA) −40 +85 °CInput Rise or Fall Times (tr, tf)
VCC = 2.0V 1000 ns
VCC = 4.5V 500 ns
VCC = 9.0V 400 ns
Symbol Parameter Conditions VCCTA=25°C TA=−40 to 85°C
UnitsTyp Guaranteed Limits
VIH Minimum HIGH Level 2.0V 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 V
9.0V 6.3 5.3 V
12.0V 8.4 8.4 V
VIL Maximum LOW Level 2.0V 0.5 0.5 V
Input Voltage 4.5V 1.35 1.35 V
9.0V 2.7 2.7 V
12.0V 3.6 3.6 V
RON Maximum “ON” Resistance VCTL = VIH, IS = 2.0 mA 4.5V 100 170 200 Ω
See (Note 5) VIS = VCC to GND 9.0V 50 85 105 Ω
(Figure 1) 12.0V 30 70 85 Ω
2.0V 120 180 215 Ω
VCTL = VIH, IS = 2.0 mA 4.5V 50 80 100 Ω
VIS = VCC or GND 9.0V 35 60 75 Ω
(Figure 1) 12.0V 20 40 60 Ω
RON Maximum “ON” Resistance VCTL = VIH 4.5V 10 15 20 Ω
Matching VIS = VCC to GND 9.0V 5 10 15 Ω
12.0V 5 10 15 Ω
IIN Maximum Control VIN = VCC or GND ±0.05 ±0.5 µA
Input Current VCC = 2 − 6V
IIZ Maximum Switch “OFF” VOS = VCC or GND 6.0V 10 ±60 ±600 nA
Leakage Current VIS = GND or VCC 9.0V 15 ±80 ±800 nA
VCTL = VIL (Figure 2) 12.0V 20 ±100 ±1000 nA
IIZ Maximum Switch “ON” VIS = VCC to GND 6.0V 10 ±40 ±150 nA
Leakage Current VCTL = VIH 9.0V 15 ±50 ±200 nA
VOS = OPEN (Figure 3) 12.0V 20 ±60 ±300 nA
ICC Maximum Quiescent VIN = VCC or GND 6.0V 1.0 10 µA
Supply Current IOUT = 0 µA 9.0V 2.0 20 µA
12.0V 4.0 40 µA
3 www.fairchildsemi.com
74VH
C4066
AC Electrical CharacteristicsVCC = 2.0V−6.0V VEE = 0V−12V, CL = 50 pF (unless otherwise specified)
Note 6: Adjust 0 dBm for F = 1 kHz (Null RL/RON Attenuation).
Note 7: VIS is centered at VCC/2.
Note 8: Adjust input for 0 dBm.
Symbol Parameter Conditions VCCTA=25°C TA=−40 to 85°C
Response (Figure 7) VIS = 2 VPP at (VCC/2) 9.0V 100 MHz
20 log(VO/VI) = −3 dB (Note 6)(Note 7)
Crosstalk Between RL = 600Ω, F = 1 MHz
any Two Switches (Note 7)(Note 8) 4.5V −52 dB
(Figure 8) 9.0V −50 dB
Peak Control to Switch RL = 600Ω, F = 1 MHz 4.5V 100 mV
Feedthrough Noise CL = 50 pF 9.0V 250 mV
(Figure 9)
Switch OFF Signal RL = 600Ω, F = 1 MHz
Feedthrough V(CT) VIL
Isolation (Note 7)(Note 8) 4.5V −42 dB
(Figure 10) 9.0V −44 dB
THD Total Harmonic RL = 10 kΩ, CL = 50 pF,
Distortion F = 1 kHz
(Figure 11) VIS = 4 VPP 4.5V .013 %
VIS = 8 VPP 9.0V .008 %
CIN Maximum Control 5 10 10 pF
Input Capacitance
CIN Maximum Switch 20 pF
Input Capacitance
CIN Maximum Feedthrough VCTL = GND 0.5 pF
Capacitance
CPD Power Dissipation 15 pF
Capacitance
www.fairchildsemi.com 4
74V
HC
4066 AC Test Circuits and Switching Time Waveforms
FIGURE 1. “ON” Resistance
FIGURE 2. “OFF” Channel Leakage Current
FIGURE 3. “ON” Channel Leakage Current
FIGURE 4. tPHL, tPLH Propagation Delay Time Signal Input to Signal Output
FIGURE 5. tPZL, tPLZ Propagation Delay Time Control to Signal Output
5 www.fairchildsemi.com
74VH
C4066
AC Test Circuits and Switching Time Waveforms (Continued)
FIGURE 6. tPZH, tPHZ Propagation Delay Time Control to Signal Output
FIGURE 7. Frequency Response
Crosstalk and Distortion Test Circuits
FIGURE 8. Crosstalk: Control Input to Signal Output
FIGURE 9. Crosstalk Between Any Two Switches
www.fairchildsemi.com 6
74V
HC
4066 Crosstalk and Distortion Test Circuits (Continued)
FIGURE 10. Switch OFF Signal Feedthrough Isolation
FIGURE 11. Sinewave Distortion
Typical Performance Characteristics
Typical “ON” Resistance Typical Crosstalk BetweenAny Two Switches
Typical Frequency Response
Special ConsiderationsIn certain applications the external load-resistor current may include both VCC and signal line components. To avoid draw-ing VCC current when switch current flows into the analog switch input pins, the voltage drop across the switch must notexceed 0.6V (calculated from the ON resistance).
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied andFairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to theuser.
2. A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Data sheet acquired from Harris SemiconductorSCHS049C − Revised October 2003
CD4060B consists of an oscillatorsection and 14 ripple-carry binary counterstages. The oscillator configuration allowsdesign of either RC or crystal oscillatorcircuits. A RESET input is provided whichresets the counter to the all-O’s state anddisables the oscillator. A high level on theRESET line accomplishes the reset function.All counter stages are master-slave flip-flops.The state of the counter is advanced one stepin binary order on the negative transition of I(and O). All inputs and outputs are fullybuffered. Schmitt trigger action on theinput-pulse line permits unlimitedinput-pulse rise and fall times.
The CD4060B-series types are supplied in16-lead hermetic dual-in-line ceramic packages(F3A suffix), 16-lead dual-in-line plasticpackages (E suffix), 16-lead small-outlinepackages (M, M96, MT, and NSR suffixes), and16-lead thin shrink small-outline packages (PWand PWR suffixes).
Copyright 2003, Texas Instruments Incorporated
PACKAGING INFORMATION
Orderable Device Status (1) PackageType
PackageDrawing
Pins PackageQty
Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CD4060BE ACTIVE PDIP N 16 25 Pb-Free(RoHS)
CU NIPDAU N / A for Pkg Type
CD4060BEE4 ACTIVE PDIP N 16 25 Pb-Free(RoHS)
CU NIPDAU N / A for Pkg Type
CD4060BF ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type
CD4060BF3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type
CD4060BM ACTIVE SOIC D 16 40 Green (RoHS &no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD4060BM96 ACTIVE SOIC D 16 2500 Green (RoHS &no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD4060BM96E4 ACTIVE SOIC D 16 2500 Green (RoHS &no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD4060BME4 ACTIVE SOIC D 16 40 Green (RoHS &no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD4060BMT ACTIVE SOIC D 16 250 Green (RoHS &no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD4060BMTE4 ACTIVE SOIC D 16 250 Green (RoHS &no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD4060BNSR ACTIVE SO NS 16 2000 Green (RoHS &no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD4060BNSRE4 ACTIVE SO NS 16 2000 Green (RoHS &no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD4060BPW ACTIVE TSSOP PW 16 90 Green (RoHS &no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD4060BPWE4 ACTIVE TSSOP PW 16 90 Green (RoHS &no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD4060BPWR ACTIVE TSSOP PW 16 2000 Green (RoHS &no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD4060BPWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS &no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part ina new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please checkhttp://www.ti.com/productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirementsfor all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be solderedat high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die andpackage, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHScompatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flameretardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak soldertemperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it isprovided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to theaccuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to takereasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis onincoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limitedinformation may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TIto Customer on an annual basis.
NOTES: A. All linear dimensions are in millimeters.B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.D. Falls within JEDEC MO-153
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvements, and other changes to its products and services at any time and to discontinueany product or service without notice. Customers should obtain the latest relevant information before placingorders and should verify that such information is current and complete. All products are sold subject to TI’s termsand conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TIdeems necessary to support this warranty. Except where mandated by government requirements, testing of allparameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible fortheir products and applications using TI components. To minimize the risks associated with customer productsand applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or processin which TI products or services are used. Information published by TI regarding third-party products or servicesdoes not constitute a license from TI to use such products or services or a warranty or endorsement thereof.Use of such information may require a license from a third party under the patents or other intellectual propertyof the third party, or a license from TI under the patents or other intellectual property of TI.
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FeaturesFeaturesFeaturesFeatures• High Current Drive Capability (200mA)• Adjustable Duty Cycle• Temperature Stability of 0.005%/°C• Timing From µSec to Hours• Turn off Time Less Than 2µSec
ApplicationsApplicationsApplicationsApplications• Precision Timing• Pulse Generation• Time Delay Generation• Sequential Timing
DescriptionDescriptionDescriptionDescriptionThe LM555/NE555/SA555 is a highly stable controllercapable of producing accurate timing pulses. With amonostable operation, the time delay is controlled by oneexternal resistor and one capacitor. With an astable operation, the frequency and duty cycle are accurately controlled by two external resistors and one capacitor.
Notes:Notes:Notes:Notes:1. When the output is high, the supply current is typically 1mA less than at VCC = 5V.2. Tested at VCC = 5.0V and VCC = 15V.3. This will determine the maximum value of RA + RB for 15V operation, the max. total R = 20MΩ, and for 5V operation, the max.
total R = 6.7MΩ.4. These parameters, although guaranteed, are not 100% tested in production.
Supply Current (Low Stable) (Note1) ICCVCC = 5V, RL = ∞ - 3 6 mA
VCC = 15V, RL = ∞ - 7.5 15 mA
Timing Error (Monostable)Initial Accuracy (Note2)Drift with Temperature (Note4)Drift with Supply Voltage (Note4)
ACCUR∆t/∆T
∆t/∆VCC
RA = 1kΩ to100kΩC = 0.1µF
- 1.0500.1
3.0
0.5
%ppm/°C
%/V
Timing Error (Astable) Intial Accuracy (Note2)Drift with Temperature (Note4)Drift with Supply Voltage (Note4)
ACCUR∆t/∆T
∆t/∆VCC
RA = 1kΩ to 100kΩC = 0.1µF
- 2.251500.3
- %ppm/°C
%/V
Control Voltage VCVCC = 15V 9.0 10.0 11.0 V
VCC = 5V 2.6 3.33 4.0 V
Threshold Voltage VTHVCC = 15V - 10.0 - V
VCC = 5V - 3.33 - V
Threshold Current (Note3) ITH ---- - 0.1 0.25 µA
Trigger Voltage VTRVCC = 5V 1.1 1.67 2.2 V
VCC = 15V 4.5 5 5.6 V
Trigger Current ITR VTR = 0V 0.01 2.0 µA
Reset Voltage VRST ---- 0.4 0.7 1.0 V
Reset Current IRST ---- 0.1 0.4 mA
Low Output Voltage VOL
VCC = 15VISINK = 10mAISINK = 50mA
- 0.060.3
0.250.75
VV
VCC = 5VISINK = 5mA - 0.05 0.35 V
High Output Voltage VOH
VCC = 15VISOURCE = 200mAISOURCE = 100mA 12.75
12.513.3
- VV
VCC = 5VISOURCE = 100mA 2.75 3.3 - V
Rise Time of Output (Note4) tR ---- - 100 - ns
Fall Time of Output (Note4) tF ---- - 100 - ns
Discharge Leakage Current ILKG ---- - 20 100 nA
LM555/NE555/SA555
4444
Application InformationApplication InformationApplication InformationApplication InformationTable 1 below is the basic operating table of 555 timer:
When the low signal input is applied to the reset terminal, the timer output remains low regardless of the threshold voltage or the trigger voltage. Only when the high signal is applied to the reset terminal, the timer's output changes according to threshold voltage and trigger voltage.When the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timer's internal discharge Tr. turns on, lowering the threshold voltage to below 1/3 of the supply voltage. During this time, the timer output is maintained low. Later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply voltage, the timer's internal discharge Tr. turns off, increasing the threshold voltage and driving the timer output again at high.
Time Delay(s)Time Delay(s)Time Delay(s)Time Delay(s)
Figure 1. Monoatable CircuitFigure 1. Monoatable CircuitFigure 1. Monoatable CircuitFigure 1. Monoatable Circuit Figure 2. Resistance and Capacitance vs.Figure 2. Resistance and Capacitance vs.Figure 2. Resistance and Capacitance vs.Figure 2. Resistance and Capacitance vs. Time delay(tTime delay(tTime delay(tTime delay(tdddd))))
Figure 3. Waveforms of Monostable OperationFigure 3. Waveforms of Monostable OperationFigure 3. Waveforms of Monostable OperationFigure 3. Waveforms of Monostable Operation
1
5
6
7
84
2
3
RESET VccDISCH
THRES
CONTGND
OUT
TRIG
+Vcc
RA
C1
C2RL
Trigger
LM555/NE555/SA555
5555
Figure 1 illustrates a monostable circuit. In this mode, the timer generates a fixed pulse whenever the trigger voltage falls below Vcc/3. When the trigger pulse voltage applied to the #2 pin falls below Vcc/3 while the timer output is low, the timer's internal flip-flop turns the discharging Tr. off and causes the timer output to become high by charging the external capacitor C1 and setting the flip-flop output at the same time. The voltage across the external capacitor C1, VC1 increases exponentially with the time constant t=RA*C and reaches 2Vcc/3 at td=1.1RA*C. Hence, capacitor C1 is charged through resistor RA. The greater the time constant RAC, the longer it takes for the VC1 to reach 2Vcc/3. In other words, the time constant RAC controls the output pulse width. When the applied voltage to the capacitor C1 reaches 2Vcc/3, the comparator on the trigger terminal resets the flip-flop, turning the discharging Tr. on. At this time, C1 begins to discharge and the timer output converts to low.In this way, the timer operating in the monostable repeats the above process. Figure 2 shows the time constant relationship based on RA and C. Figure 3 shows the general waveforms during the monostable operation. It must be noted that, for a normal operation, the trigger pulse voltage needs to maintain a minimum of Vcc/3 before the timer output turns low. That is, although the output remains unaffected even if a different trigger pulse is applied while the output is high, it may be affected and the waveform does not operate properly if the trigger pulse voltage at the end of the output pulse remains at below Vcc/3. Figure 4 shows such a timer output abnormality.
Figure 5. Astable CircuitFigure 5. Astable CircuitFigure 5. Astable CircuitFigure 5. Astable Circuit Figure 6. Capacitance and Resistance vs. FrequencyFigure 6. Capacitance and Resistance vs. FrequencyFigure 6. Capacitance and Resistance vs. FrequencyFigure 6. Capacitance and Resistance vs. Frequency
1
5
6
7
84
2
3
RESET VccDISCH
THRES
CONTGND
OUT
TRIG
+Vcc
RA
C1
C2RL
RB
LM555/NE555/SA555
6666
An astable timer operation is achieved by adding resistor RB to Figure 1 and configuring as shown on Figure 5. In the astable operation, the trigger terminal and the threshold terminal are connected so that a self-trigger is formed, operating as a multi vibrator. When the timer output is high, its internal discharging Tr. turns off and the VC1 increases by exponential function with the time constant (RA+RB)*C. When the VC1, or the threshold voltage, reaches 2Vcc/3, the comparator output on the trigger terminal becomes high,resetting the F/F and causing the timer output to become low. This in turn turns on the discharging Tr. and the C1 discharges through the discharging channel formed by RB and the discharging Tr. When the VC1 falls below Vcc/3, the comparator output on the trigger terminal becomes high and the timer output becomes high again. The discharging Tr. turns off and the VC1 rises again. In the above process, the section where the timer output is high is the time it takes for the VC1 to rise from Vcc/3 to 2Vcc/3, and the section where the timer output is low is the time it takes for the VC1 to drop from 2Vcc/3 to Vcc/3. When timer output is high, the equivalent circuit for charging capacitor C1 is as follows:
Since the duration of the timer output high state(tH) is the amount of time it takes for the VC1(t) to reach 2Vcc/3,
Figure 7. Waveforms of Astable OperationFigure 7. Waveforms of Astable OperationFigure 7. Waveforms of Astable OperationFigure 7. Waveforms of Astable Operation
Vcc
RA RB
C1 Vc1(0-)=Vcc/3
C1dvc1
dt-------------
Vcc V 0-( )–
RA RB+-------------------------------= 1( )
VC1 0+( ) VCC 3⁄= 2( )
VC1 t( ) VCC 1 23---e
- tRA RB+( )C1
------------------------------------–
–
= 3( )
LM555/NE555/SA555
7777
The equivalent circuit for discharging capacitor C1, when timer output is low is, as follows:
Since the duration of the timer output low state(tL) is the amount of time it takes for the VC1(t) to reach Vcc/3,
Since RD is normally RB>>RD although related to the size of discharging Tr.,tL=0.693RBC1 (10)
Consequently, if the timer operates in astable, the period is the same with 'T=tH+tL=0.693(RA+RB)C1+0.693RBC1=0.693(RA+2RB)C1' because the period is the sum of the charge time and discharge time. And since frequency is the reciprocal of the period, the following applies.
3. Frequency divider3. Frequency divider3. Frequency divider3. Frequency dividerBy adjusting the length of the timing cycle, the basic circuit of Figure 1 can be made to operate as a frequency divider. Figure 8. illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle.
VC1 t( ) 23---VCC V=
CC1 2
3---e
-tH
RA RB+( )C1------------------------------------–
–
= 4( )
tH C1 RA RB+( )In2 0.693 RA RB+( )C1== 5( )
C1
RB
RDVC1(0-)=2Vcc/3
C1dvC1
dt-------------- 1
RA RB+-----------------------VC1 0=+ 6( )
VC1 t( ) 23---V
CCe
- tRA RD+( )C1
-------------------------------------
= 7( )
13---VCC
23---V
CCe
-tL
RA RD+( )C1-------------------------------------
= 8( )
tL C1 RB RD+( )In2 0.693 RB RD+( )C1== 9( )
frequency, f 1T--- 1.44
RA 2RB+( )C1----------------------------------------= = 11( )
LM555/NE555/SA555
8888
4. Pulse Width Modulation4. Pulse Width Modulation4. Pulse Width Modulation4. Pulse Width ModulationThe timer output waveform may be changed by modulating the control voltage applied to the timer's pin 5 and changing the reference of the timer's internal comparators. Figure 9 illustrates the pulse width modulation circuit.When the continuous trigger pulse train is applied in the monostable mode, the timer output width is modulated according to the signal applied to the control terminal. Sine wave as well as other waveforms may be applied as a signal to the control terminal. Figure 10 shows the example of pulse width modulation waveform.
5. Pulse Position Modulation5. Pulse Position Modulation5. Pulse Position Modulation5. Pulse Position ModulationIf the modulating signal is applied to the control terminal while the timer is connected for the astable operation as in Figure 11, the timer becomes a pulse position modulator.In the pulse position modulator, the reference of the timer's internal comparators is modulated which in turn modulates the timer output according to the modulation signal applied to the control terminal.Figure 12 illustrates a sine wave for modulation signal and the resulting output pulse position modulation : however, any wave shape could be used.
Figure 8. Waveforms of Frequency Divider OperationFigure 8. Waveforms of Frequency Divider OperationFigure 8. Waveforms of Frequency Divider OperationFigure 8. Waveforms of Frequency Divider Operation
Figure 9. Circuit for Pulse Width ModulationFigure 9. Circuit for Pulse Width ModulationFigure 9. Circuit for Pulse Width ModulationFigure 9. Circuit for Pulse Width Modulation Figure 10. Waveforms of Pulse Width ModulationFigure 10. Waveforms of Pulse Width ModulationFigure 10. Waveforms of Pulse Width ModulationFigure 10. Waveforms of Pulse Width Modulation
84
7
1
2
3
5
6
CONTGND
Vcc
DISCH
THRES
RESET
TRIG
OUT
+Vcc+Vcc+Vcc+Vcc
TriggerTriggerTriggerTrigger
RRRRAAAA
CCCC
OutputOutputOutputOutputInputInputInputInput
LM555/NE555/SA555
9999
6. Linear Ramp6. Linear Ramp6. Linear Ramp6. Linear RampWhen the pull-up resistor RA in the monostable circuit shown in Figure 1 is replaced with constant current source, the VC1 increases linearly, generating a linear ramp. Figure 13 shows the linear ramp generating circuit and Figure 14 illustrates the generated linear ramp waveforms.
In Figure 13, current source is created by PNP transistor Q1 and resistor R1, R2, and RE.
For example, if Vcc=15V, RE=20kΩ, R1=5kW, R2=10kΩ, and VBE=0.7V, VE=0.7V+10V=10.7VIc=(15-10.7)/20k=0.215mA
84
7
1
2
3
5
6
CONTGND
Vcc
DISCH
THRES
RESET
TRIG
OUT
+Vcc+Vcc+Vcc+Vcc
RRRRAAAA
CCCC
RRRRBBBB
ModulationModulationModulationModulation
OutputOutputOutputOutput
Figure 11. Circuit for Pulse Position ModulationFigure 11. Circuit for Pulse Position ModulationFigure 11. Circuit for Pulse Position ModulationFigure 11. Circuit for Pulse Position Modulation Figure 12. Waveforms of pulse position modulationFigure 12. Waveforms of pulse position modulationFigure 12. Waveforms of pulse position modulationFigure 12. Waveforms of pulse position modulation
Figure 13. Circuit for Linear RampFigure 13. Circuit for Linear RampFigure 13. Circuit for Linear RampFigure 13. Circuit for Linear Ramp Figure 14. Waveforms of Linear RampFigure 14. Waveforms of Linear RampFigure 14. Waveforms of Linear RampFigure 14. Waveforms of Linear Ramp
1
5
6
7
84
2
3
RESET VccDISCH
THRES
CONTGND
OUT
TRIG
+Vcc
C2
R1
R2
C1
Q1
Output
RE
ICVCC VE–
RE---------------------------= 12( )
Here, VE is
VE VBE
R2R1 R2+----------------------VCC+= 13( )
LM555/NE555/SA555
10101010
When the trigger starts in a timer configured as shown in Figure 13, the current flowing through capacitor C1 becomes a constant current generated by PNP transistor and resistors. Hence, the VC is a linear ramp function as shown in Figure 14. The gradient S of the linear ramp function is defined as follows:
Here the Vp-p is the peak-to-peak voltage.If the electric charge amount accumulated in the capacitor is divided by the capacitance, the VC comes out as follows:
V=Q/C (15)
The above equation divided on both sides by T gives us
and may be simplified into the following equation.
S=I/C (17)
In other words, the gradient of the linear ramp function appearing across the capacitor can be obtained by using the constant current flowing through the capacitor. If the constant current flow through the capacitor is 0.215mA and the capacitance is 0.02µF, the gradient of the ramp function at both ends of the capacitor is S = 0.215m/0.022µ = 9.77V/ms.
LIFE SUPPORT POLICY LIFE SUPPORT POLICY LIFE SUPPORT POLICY LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
DISCLAIMER DISCLAIMER DISCLAIMER DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
Any and all SANYO products described or contained herein do not have specifications that can handleapplications that require extremely high levels of reliability, such as life-support systems, aircraft’scontrol systems, or other applications whose failure can be reasonably expected to result in seriousphysical and/or material damage. Consult with your SANYO representative nearest you before usingany SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values thatexceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or otherparameters) listed in products specifications of any and all SANYO products described or containedherein.
Monolithic Linear IC
6W 2-Channel, Bridge 19W typ Power Amplifier
Ordering number:ENN750F
LA4440
SANYO Electric Co.,Ltd. Semiconductor CompanyTOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
• Minimun number of external parts required.• Small pop noise at the time of power supply ON/OFF and
good starting balance.• Good ripple rejection : 46dB (typ.)• Good channel separation.• Small residual noise (Rg=0).• Low distortion over a wide range from low frequencies to
high frequencies.• Easy to design radiator fin.• Built-in audio muting function.• Built-in protectors.
a. Thermal protectorb. Overvoltage, surge voltage protectorc. Pin-to-pin short protector
SpecificationsAbsolute Maximum Ratings at Ta = 25˚C
˚C
˚C
141
13.8
0.6
37.0
30.0
R1.
7
11.0
8.0
0.8m
in
6.0
15.0
max
1.99 2.54 1.40.4
4.5
2.25
retemaraP lobmyS snoitidnoC sgnitaR tinU
egatlovylppusmumixaMV CC 1xam )s03=t(tnecseiuQ 52 V
V CC 2xam gnitarepO 81 V
egatlovylppusegruS V CC )egrus( t≤ s2.0 05 V
noitapissidrewopelbawollA xamdP 51 W
ecnatsiserlamreT θ c-j esac-ot-noitcnuJ 3
erutarepmetgnitarepO rpoT 57+ot02–
erutarepmetegarotS gtsT 051+ot04–
˚C/W
Recommended Operating Conditions at Ta = 25˚C
Tc=75˚C, See Pd max – Ta characteristic
retemaraP lobmyS snoitidnoC sgnitaR tinU
egatlovylppuS V CC 2.31 V
ecnatsiserdaoL RLoeretS 8ot2 Ω
egdirB 8ot4 Ω
LA4440
No.750–2/13
Operating Characteristics at Ta = 25˚C, VCC=13.2V, RL=4Ω, f=1kHz, Rg=600Ω, with 100×100×1.5mm3 Al fin,
See specified Test Circuit.
retemaraP lobmyS snoitidnoCsgnitaR
tinUnim pyt xam
tnerructnecseiuQ occI 001 002 Am
niagegatloV GV 5.94 5.15 5.35 Bd
rewoptuptuO POoeretS,%01=DHT 0.5 0.6 W
egdirB,%01=DHT 91 W
noitrotsidcinomrahlatoT DHT PO W1= 1.0 0.1 %
ecnatsisertupnI ri k03 Ω
egatlovesiontuptuO V ON0=gR 6.0 0.1 Vm
k01=gR Ω 0.1 0.2 Vm
oitarnoitcejerelppiR Rr VR f,Vm002= R 0=gR,zH001= 64 Bd
noitarapeslennahC peshC VO k01=gR,mBd0= Ω 54 55 Bd
noitaunettagnituM TTA VO V,mBd0= M V9= 04 Bd
slennahcneewtebecnereffidniaG ∆ GV 2 Bd
Equivalent Circuit Block Diagram
LA4440
No.750–3/13
Sample Application Circuit 1. Stereo use
Sample Application Circuit 2. Bridge amplifier 1
LA4440
No.750–4/13
Sample Application Circuit 3. Bridge amplifier 2
Description of External PartsC1 (C2) · Feedback capacitor : The low cutoff frequency depends on this capacitor.
If the capacitance value is increased, the starting time is delayed.C3 (C4) · Bootstrap capacitor : If the capacitance value is decreased, the output at low frequencies goes lower.C5 (C6) · Oscillation preventing capacitor : Polyester film capacitor, being good in temperature characteristic,
frequency characteristic, is used.The capacitance value can be reduced to 0.047µF depending on the stability of the board.
C7 (C8) · Output capacitor : The low cutoff frequency depends on this capacitor.At the bridge amplifier mode, the output capacitor is generally connected.
C9 · Decoupling capacitor :Used for the ripple filter. Since the rejection effect is saturated at a certaincapacitance value, it is meaningless to increase the capacitance value more than required. This capaci-tor, being also used for the time constant of the muting circuit, affects the starting time.
R1 (R2) · Filter resistor for preventing oscillation.R3 (R4) · Resistor for making input signal of inverting amplifier in Voltage Gain Adjust at Bridge Amplifier
Mode (No. 1).R5 · Resistor for adjusting starting time in Voltage Gain Adjust at Bridge Amplifier Mode (No. 2)C10 · Capacitor for preventing oscillation in Voltage Gain Adjust at Bridge Amplifier Mode (No. 2)C11 · Power source capacitor.R6 (R7) · Used at bridge amplifier mode in order to increase discharge speed and to secure transient stability.
Feaures of IC System and Functions of Remaining Pins(a) Since the input circuit uses PNP transistors and the input potential is designed to be 0 bias, no input coupling
capacitor is required and direct coupling is available. However, when slider contact noise caused by the variableresistor presents a problem, connect an capacitor in series with the input.
(b) The open-loop voltage gain is lowered and the negative feedback amount is reduced for stabilization. An increasein distortion resulted from the reduced negative feedback amount is avoided by use of the built-in unique distor-tion reduction circuit, and thus distortion is kept at 0.1% (typ.).
(c) A capacitor for oscillation compensation is contained as a means of reducing the number of external parts. Thecapacitance value is 35pF which determines high cutoff frequency fH (–3dB point) of the amplifier (fH≈20kHz).
(d) For preventing the IC from being damaged by a surge applied on the power line, an overvoltage protector iscontained. Overvoltage setting is 25V. It is capable of withstanding up to 50V at giant pulse surge 200ms.
(e) No damege occurs even when power is applied at a state where pins 10, 11, and 12 are short-circuited with solderbridge, etc.
(f) To minimize the variations in voltage gain, feedback resistor RNF is contained and voltage gain (51.5dB) is fixed.
Voltage Gain Adjust at Bridge Amplifier Mode (No. 1)
· The bridge amplifier configuration is as shown left, inwhich ch1 and ch2 operate as noninverting amplifierand inverting amplifier respectively.The output of the noninverting amplifier divided byresistors R3, R4 is applied, as input, to the invertingamplifier.Since attenuation (R4/R3) of the non-inverting amplifieroutput and amplification factor (Rf/R4+RNF) of theinverting amplifier are fixed to be the same, signals ofthe same level and 180° out of phase with each othercan be obtained at output pins (12) and (10). The totalvoltage gain is apparently higher than that of thenoninverting amplifier by 6dB and is approximatelycalculated by the following formula.
VG=20log + 6dB
In case of reducing the voltage gain, RNF’ is connectedto the noninverting amplifier side only and the followingformula is used.
VG=20log + 6dB
VG=20log (dB)
where (RNF+RNF’) << R5
From this formula, it is seen that connecting RNF’causes the voltage gain to be reduced at the modes ofboth stereo amplifier and bridge amplifier.
RfRNF
Voltage Gain Adjust at Bridge Amplifier Mode (No. 2)
RfRNF+RNF’
RfRNF+RNF’
2
LA4440
No.750–6/13
(g) In case of applying audio muting in each application circuit, the following circuit is used.
6V≤VM≤VCCRecommended VM=9VATT=40dB (Rg=600Ω)
Flow-in current IO is calculated by the following formula.
IO=
In case of increasing the muting attenuation, resistor 5.6kΩ is connected in series with the input, and then theattenuation is made to be 55dB. Be careful that connecting an input capacitor causes pop noise to be increased atthe time of application of AC muting. Increased RO, CO make it possible to reduce the noise. In case of com-pletely cutting off power IC, pin (5) is grounded, and then DC control is available and the attenuation is made tobe ∞.
Proper Cares in Using IC· Maximum ratingsIf the IC is used in the vicinity of the maximum ratings, even a slight variation in conditions may cause the maximumratings to be exceeded, thereby leading to breakdown. Allow an ample margin of variation for supply voltage, etc. anduse the IC in the range where the maximum ratings are not exceeded.
· Printed circuit boardWhen making the board, refer to the sample printed circuit pattern and be careful that no feedback loop is formedbetween input and output.
· Oscillation preventing capacitorNormally, a polyester film capacitor is used for 0.1µF + 4.7Ω. The capacitance value can be reduced to 0.047µF depend-ing on the stability of the board.
· OthersConnect the radiator fin of the package to GND.
LA4440
No.750–7/13
Characteristics at stereo amplifier mode
LA4440
No.750–8/13
LA4440
No.750–9/13
Characteristics at bridge amplifier mode No. 1
LA4440
No.750–10/13
LA4440
No.750–11/13
Characteristics at bridge amplifier mode No. 2
LA4440
No.750–12/13
Proper Cares in Mounging Radiator Fin1. The mounting torque is in the range of 39 to 59N · cm.2. The distance between screw holes of the radiator fin must coincide with the distance between screw holes of the IC.
With case outline dimensions L and R referred to, the screws must be tightened with the distance between them asclose to each other as possible.
3. The screw to be used must have a head equivalent to the one of truss machine screw or binder machine screw definedby JIS. Washers must be also used to protect the IC case.
4. No foreign matter such as cutting particles shall exist between heat sink and radiator fin. When applying grease on thejunction surface, it must be applied uniformly on the whole surface.
5. IC lead pins are soldered to the printed circuit board after the radiator fin is mounted on the IC.
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guaranteesof the performance, characteristics, and functions of the described products as mounted in the customer'sproducts or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and allsemiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,or that could cause damage to other property. When designing equipment, adopt safety measures sothat these kinds of accidents or events cannot occur. Such measures include but are not limited to protectivecircuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or al l SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations,such products must not be expor ted without obtaining the expor t l icense from the authorit iesconcerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic ormechanical, including photocopying and recording, or any information storage or retrieval system,or otherwise, without the prior written permission of SANYO Electric Co. , Ltd.
Any and all information described or contained herein are subject to change without notice due toproduct/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only ; it is notguaranteed for volume production. SANYO believes information herein is accurate and reliable, butno guarantees are made or implied regarding its use or any infringements of intellectual property rightsor other rights of third parties.
This catalog provides information as of February, 2000. Specifications and information herein are subject
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductorproduct or service without notice, and advises its customers to obtain the latest version of relevant informationto verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications applicable atthe time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques areutilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of eachdevice is not necessarily performed, except those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, orsevere property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTEDTO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHERCRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TIproducts in such applications requires the written approval of an appropriate TI officer. Questions concerningpotential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer’s applications, adequate design and operatingsafeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, orinfringement of patents or services described herein. Nor does TI warrant or represent that any license, eitherexpress or implied, is granted under any patent right, copyright, mask work right, or other intellectual propertyright of TI covering or relating to any combination, machine, or process in which such semiconductor productsor services might be or are used.
Copyright 1997, Texas Instruments Incorporated
Notational Conventions
iii Read This First
Preface
Read This First
About This Manual
The Texas Instruments (TI ) TLC2932 Evaluation Module TechnicalReference Manual for the TLC2932 high-performance phase-locked loopprovides information to assist managers and hardware/software engineers inapplication development.
How to Use This Manual
This document contains the following chapters:
Chapter 1 OverviewA general description of the TLC2932 Evaluation Module (TLC2932EVM), keyfeatures, and a functional overview are included.
Chapter 2 HardwareA general description of the TLC2932EVM hardware is included.
Appendix A TLC2932 Data SheetA copy of the TLC2932 data sheet is included.
Appendix B TC9122P Data Sheet SummaryA summary of the TC9122P data sheet is included.
Symbol Convention
This document uses the following convention:
TC TOSHIBA device number prefix
Information About Cautions and Warnings/Related Documentation From Texas Instruments
iv
Information About Cautions and Warnings
This book may contain cautions and warnings.
This is an example of a caution statement.
A caution statement describes a situation that could potentiallydamage your software or equipment.
This is an example of a warning statement.
A warning statement describes a situation that could potentiallycause harm to you .
The information in a caution or a warning is provided for your protection.Please read each caution and warning carefully.
Related Documentation From Texas Instruments
TLC2932 High-Performance Phase-Locked Loop Data Sheet ( literaturenumber SLAS097E) is included in Appendix A of this book. It containselectrical specifications, available temperature options, generaloverview of the device, and application information.
TLC2932 Phase-Locked Loop Building Block With AnalogVoltage-Controlled Oscillator and Phase Frequency DetectorApplication Report (literature number SLAA011B) contains anoverview of phase-locked loop functional blocks, transfer functionanalyses, evaluation module (EVM) board design, and performancecharacteristics.
Data Acquisition Circuits Data Book (literature number SLAD001) containsthe data sheets for devices that perform analog-to-digital,digital-to-analog, and related functions. It also has selection tables andpackage and ordering information.
FCC Warning
This equipment is intended for use in a laboratory test environment only. Itgenerates, uses, and can radiate radio frequency energy and has not beentested for compliance with the limits of computing devices pursuant to subpartJ of part 15 of FCC rules, which are designed to provide reasonable protectionagainst radio frequency interference. Operation of this equipment in otherenvironments may cause interference with radio communications, in whichcase the user at his own expense will be required to take whatever measuresmay be required to correct this interference.
If You Need Assistance
v Read This First
Trademarks
TI is a trademark of Texas Instruments Incorporated.
TOSHIBA is a trademark of TOSHIBA AMERICA, Inc.
If You Need Assistance. . .
If you want to. . . Do this. . .
Request more information aboutTexas Instruments Mixed SignalProducts (MSP)
Call the Product Information Center (PIC)hotline:(214) 644–5580
Or send a fax to the PIC:(214) 480–7800
Or write to:Texas Instruments IncorporatedProduct Information Center, MS 3123P.O. Box 660246Dallas, Texas 75266
Order Texas Instrumentsdocumentation
Call the PIC hotline:(214) 644–5580
Ask questions about productoperation or report suspectedproblems
Call the PIC hotline:(214) 644–5580
Report mistakes in this documentor any other TI Mixed SignalProducts documentation
Send a fax to MSP Marketing DocumentationCorrection: (214) 480–3160
Or send your comments to:Texas Instruments IncorporatedMSP Marketing Documentation Correction,MS 8710P.O. Box 660199Dallas, Texas 75266–0199
The TLC2932 evaluation module (TLC2932EVM) provides a method toevaluate the performance of the TLC2932 phase-locked-loop (PLL) buildingblock. The TLC2932EVM contains a phase frequency detector (PFD) and avoltage-controlled oscillator (VCO). This manual explains how to constructbasic frequency synthesis circuits including the design of a low-pass filter(LPF). This chapter includes the following topics:
The TLC2932EVM for the TLC2932IPW Texas Instruments CMOSphase-locked loop (PLL) integrated circuit (IC) contains a TLC2932IPW, twoTC9122P programmable counters, a loop filter, and other devices, as shownin Figure 1–1. These devices comprise a clock synthesizer on the module toevaluate basic PLL functionality and performance. The general externalconnections of the TLC2932EVM are shown in Figure 1–2.
The TLC2932EVM includes the following:
A reference frequency is generated by the crystal (XTAL) oscillator andsupplied to PFD input through the programmable counter. An external ref-erence (F–ref in) can be input through the Baby N Connector (BNC).
The 14.31818-MHz XTAL oscillator on the EVM is a standard part. It canbe replaced by any other XTAL oscillator with an oscillation frequency inthe functional range of the TC9122P programmable counter.
A lag-lead filter standard connection is available on the board. For moreflexible filter design, a free area beside the socket of TLC2932IPW isprovided.
Dip switches on the board are used to set the TC9122P programmablecounter and can be used to set the N/M counter as a frequencysynthesizer.
Figure 1–1. TLC2932EVM Block Diagram
ProgrammableCounterTC9122P
XTAL Oscillator14.31818 MHz
Selector
S3–S5
ProgrammableCounterTC9122P
Prescalar74AC11074
1/2 1/2
TLC2932IPW
Low-PassFilter
DVDD 5 VAVDD 5 V
AGND DGND
Output
U1 U2 U6
U3/U4 U5
F–ref in
TLC2932EVM Operating Specifications
1-3 Overview
1.2 TLC2932EVM Operating Specifications
If the on-board XTAL oscillator supplied with the EVM is used, DVDD shouldbe adjusted to 5.5 V instead of 5 V nominal because of the improvedperformance of the TC9122P counter at the higher DVDD.
Table 1–1 lists the supply voltage operating specifications.
Table 1–1.Supply Voltage Operating Specifications
Clock Generator UsedDVDD
(nominal) (V)AVDD
(nominal) (V)
On-board oscillator with TC9122Pprogrammable counter
5.5 5
Externally applied reference frequency atF–ref in
5 5
Evaluation of the Clock Synthesizer
1-4
1.3 Evaluation of the Clock Synthesizer
This section includes a typical evaluation using the TLC2932EVM. The PLLblock [voltage-controlled oscillator (VCO), phase frequency detector (PFD),low-pass filter (LPF), and counter] parameters of this evaluation include thefollowing:
VCO: R1 = 2.2 kΩ as RBIAS, lock frequency = 14.31818 MHz
PFD: Comparison frequency = fREF = 15.734 kHz, 14.31818-MHz XTAL oscillator as reference
LPF: Lag-lead filter C and R values are calculated in the followingsection
This section examines the calculations used to derive the C and R values forthe lag-lead filter. The design parameters selected for this example include thefollowing:
VCO range: Selected from the VCO characteristic curvebelow (see Figure 1–3)
In the case of the lag-lead filter, ωn and ζ are calculated according to thefollowing equations:
n (Kp Kv)(P N) (T1 T2) (2)
n2 T2 N(Kp Kv) (3)(T1 R2 C1, T2 R3 C1)
PFD gain
Kp 0.32 V/radVOH – VOL
4π= (4)
where VOH and VOL are obtained from the data sheet
VCO gain from Figure 1–3
(5)Kv (32 12)MHz 106(4 1)V 2
41.9 MradVsec
Evaluation of the Clock Synthesizer
1-6
The R2 and R3 values for the LPF are calculated according to the followingequations:
R2 Kp Kvn2 1(P N) 2n N(Kp Kv)C1
R3 2n N(Kp Kv)C1 (7)
(6)
When C1 is set to 1 µF, the R2 and R3 calculated values are:
R2 = 470 Ω , R3 = 240 Ω
Capacitor C2 is added to minimize high-frequency pickup at the VCO input,and the C2 value should be set equal to or smaller than C1 ⋅ 1/10 to have aminimal effect on the LPF poles, hence:
C2 = 0.1 µF is selected for this application.
1.3.2 Evaluation Board Output Waveform
Figure 1–4 shows the input frequencies and the VCO output waveform usingthe C and R values calculated in the previous section.
Figure 1–4. Input Frequencies and VCO Output Waveform
For active filtering on the EVM, space is available to build the filter using anoperational amplifier. Note the inverted output of the filter; this inverted outputcan be compensated for by changing the JP2 connections of 1 to 4, 2 to 3(normally 1 to 2, 3 to 4 for lag-lead filter).
To find the best C and R values for each application, some evaluation may berequired. The LPF characteristics resulting from standard values of R and Ccan cause the PLL performance to be slightly different from theoretical results.
Operation Notes
1-7 Overview
1.4 Operation Notes
When an external reference frequency is input through the J1 connector,an R7 resistor should be inserted as termination.
The VCO output should drive only one external device to avoid overload.
Because this evaluation board has a high-frequency VCO functionalblock, it requires the closest connection and shortest possible lead-in ofeach I/O to optimize board performance.
The supply voltage for this board should be 5 V or as specified inSection 1.2, TLC2932EVM Operating Specifications, as determined bythe peripheral IC supply voltage requirements, because the TLC2932IPWcan use both 5 V and 3 V.
For details of the 74AC11074 prescalar on this board, see the TI CMOSData Book.
For a description of the programmable counter functions, see the generalreference information included in this document from the TOSHIBATC9122P data sheet.
A bypass capacitor for the BIAS terminal should be used for anyapplication and placed as close as possible to terminal 13. This capacitoris included on the TLC2932EVM and designated as C17.
This appendix presents a copy of the TLC2932 data sheet.
Appendix A
TLC2932I Data Sheet
A-2
A.1 TLC2932 Data Sheet
TLC2932IHIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
A-3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Voltage-Controlled Oscillator (VCO)Section:– Complete Oscillator Using Only One
External Bias Resistor (R BIAS)– Lock Frequency:
22 MHz to 50 MHz (VDD = 5 V ±5%,TA = –20°C to 75°C, ×1 Output)11 MHz to 25 MHz (VDD = 5 V ±5%,TA = –20°C to 75°C, ×1/2 Output)
– Output Frequenc y . . . ×1 and ×1/2Selectable
Phase-Frequency Detector (PFD) SectionIncludes a High-Speed Edge-TriggeredDetector With Internal Charge Pump
Independent VCO, PFD Power-Down Mode
Thin Small-Outline Package (14 terminal)
CMOS Technology
Typical Applications:– Frequency Synthesis– Modulation/Demodulation– Fractional Frequency Division
Application Report Available †
CMOS Input Logic Level
description
The TLC2932I is designed for phase-locked-loop (PLL) systems and is composed of a voltage-controlledoscillator (VCO) and an edge-triggered-type phase frequency detector (PFD). The oscillation frequency rangeof the VCO is set by an external bias resistor (RBIAS). The VCO has a 1/2 frequency divider at the output stage.The high-speed PFD with internal charge pump detects the phase difference between the reference frequencyinput and signal frequency input from the external counter. Both the VCO and the PFD have inhibit functions,which can be used as a power-down mode. The TLC2932I is suitable for use as a high-performance PLL dueto the high speed and stable oscillation capability of the device.
functional block diagram
PhaseFrequencyDetector
4
5
9
6FIN–A
FIN–B
PFD INHIBIT
PFD OUT
Voltage-ControlledOscillator
12
13
103
VCO IN
BIAS
VCO INHIBITVCO OUT
2SELECT
AVAILABLE OPTIONS
PACKAGE
TA SMALL OUTLINE(PW)
–20°C to 75°C TLC2932IPWLE
Copyright 1997, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† TLC2932 Phase-Locked-Loop Building Block With Analog Voltage-Controlled Oscillator and Phase Frequency Detector (SLAA011).
1
2
3
4
5
6
7
14
13
12
11
10
9
8
LOGIC VDDSELECT
VCO OUTFIN–AFIN–B
PFD OUTLOGIC GND
VCO VDDBIASVCO INVCO GNDVCO INHIBITPFD INHIBITNC
PW PACKAGE †
(TOP VIEW)
NC – No internal connection
† Available in tape and reel only and ordered as theTLC2932IPWLE.
TLC2932IHIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
A-4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINALI/O DESCRIPTION
NAME NO.I/O DESCRIPTION
FIN–A 4 I Input reference frequency f(REF IN) is applied to FIN–A.
FIN–B 5 I Input for VCO external counter output frequency f(FIN–B). FIN–B is nominally provided from the externalcounter.
LOGIC GND 7 GND for the internal logic.
LOGIC VDD 1 Power supply for the internal logic. This power supply should be separate from VCO VDD to reducecross-coupling between supplies.
NC 8 No internal connection.
PFD INHIBIT 9 I PFD inhibit control. When PFD INHIBIT is high, PFD output is in the high-impedance state, see Table 3.
PFD OUT 6 O PFD output. When the PFD INHIBIT is high, PFD output is in the high-impedance state.
BIAS 13 I Bias supply. An external resistor (RBIAS) between VCO VDD and BIAS supplies bias for adjusting theoscillation frequency range.
SELECT 2 I VCO output frequency select. When SELECT is high, the VCO output frequency is ×1/2 and when low, theoutput frequency is ×1, see Table 1.
VCO IN 12 I VCO control voltage input. Nominally the external loop filter output connects to VCO IN to control VCOoscillation frequency.
VCO INHIBIT 10 I VCO inhibit control. When VCO INHIBIT is high, VCO OUT is low (see Table 2).
VCO GND 11 GND for VCO.
VCO OUT 3 O VCO output. When the VCO INHIBIT is high, VCO output is low.
VCO VDD 14 Power supply for VCO. This power supply should be separated from LOGIC VDD to reduce cross-couplingbetween supplies.
detailed description
VCO oscillation frequency
The VCO oscillation frequency is determined by an external resistor (RBIAS) connected between the VCO VDDand the BIAS terminals. The oscillation frequency and range depends on this resistor value. The bias resistorvalue for the minimum temperature coefficient is nominally 3.3 kΩ with 3-V at the VCO VDD terminal andnominally 2.2 kΩ with 5-V at the VCO VDD terminal. For the lock frequency range refer to the recommendedoperating conditions. Figure 1 shows the typical frequency variation and VCO control voltage.
VCO Oscillation Frequency Range
Bias Resistor (R BIAS)
1/2 VDDVCO Control Voltage (VCO IN)
VC
O O
scill
atio
n F
requ
ency
(f
)os
c
Figure 1. VCO Oscillation Frequency
TLC2932IHIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
A-5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VCO output frequency 1/2 divider
The TLC2932I SELECT terminal sets the fosc or 1/2 fosc VCO output frequency as shown in Table 1. The 1/2fosc output should be used for minimum VCO output jitter.
Table 1. VCO Output 1/2 Divider Function
SELECT VCO OUTPUT
Low fosc
High 1/2 fosc
VCO inhibit function
The VCO has an externally controlled inhibit function which inhibits the VCO output. A high level on the VCOINHIBIT terminal stops the VCO oscillation and powers down the VCO. The output maintains a low level duringthe power-down mode, refer to Table 2.
Table 2. VCO Inhibit Function
VCO INHIBIT VCO OSCILLATOR VCO OUTPUT IDD(VCO)Low Active Active Normal
High Stopped Low level Power Down
PFD operation
The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phasedifference between two frequency inputs supplied to FIN–A and FIN–B as shown in Figure 2. Nominally thereference is supplied to FIN–A, and the frequency from the external counter output is fed to FIN–B.
FIN–A
FIN–B
PFD OUT
VOH
Hi-Z
VOL
Figure 2. PFD Function Timing Chart
PFD output control
A high level on the PFD INHIBIT terminal places the PFD output in the high-impedance state and the PFD stopsphase detection as shown in Table 3. A high level on the PFD INHIBIT terminal also can be used as thepower-down mode for the PFD.
Table 3. VCO Output Control Function
PFD INHIBIT DETECTION PFD OUTPUT IDD(PFD)Low Active Active Normal
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network GND.2. For operation above 25°C free-air temperature, derate linearly at the rate of 5.6 mW/°C.
TLC2932IHIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
A-7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
PARAMETER MIN NOM MAX UNIT
Supply voltage V (each supply see Note 3)VDD = 3 V 2.85 3 3.15
VSupply voltage, VDD (each supply, see Note 3)VDD = 5 V 4.75 5 5.25
V
Input voltage, VI (inputs except VCO IN) 0 VDD V
Output current, IO (each output) 0 ±2 mA
VCO control voltage at VCO IN 0.9 VDD V
Lock frequency (×1 output)VDD = 3 V 14 21
MHzLock frequency (×1 output)VDD = 5 V 22 50
MHz
Lock frequency (×1/2 output)VDD = 3 V 7 10.5
MHzLock frequency (×1/2 output)VDD = 5 V 11 25
MHz
Bias resistor RBIASVDD = 3 V 2.2 3.3 4.3
kΩBias resistor, RBIAS VDD = 5 V 1.5 2.2 3.3kΩ
NOTE 3: It is recommended that the logic supply terminal (LOGIC VDD) and the VCO supply terminal (VCO VDD) should be at the same voltageand separated from each other.
electrical characteristics over recommended operating free-air temperature range, V DD = 3 V(unless otherwise noted)
VCO sectionPARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –2 mA 2.4 V
VOL Low-level output voltage IOL = 2 mA 0.3 V
VIT Input threshold voltage at SELECT, VCO INHIBIT 0.9 1.5 2.1 V
II Input current at SELECT, VCO INHIBIT VI = VDD or GND ±1 µA
Zi(VCO IN) Input impedance VCO IN = 1/2 VDD 10 MΩ
IDD(INH) VCO supply current (inhibit) See Note 4 0.01 1 µA
IDD(VCO) VCO supply current See Note 5 5 15 mA
NOTES: 4. Current into VCO VDD, when VCO INHIBIT = VDD, PFD is inhibited.5. Current into VCO VDD, when VCO IN = 1/2 VDD, RBIAS = 3.3 kΩ, VCO INHIBIT = GND, and PFD is inhibited.
PFD sectionPARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage at FIN–A, FIN–B 2.7 V
VIL Low-level input voltage at FIN–A, FIN–B 0.5 V
VIT Input threshold voltage at PFD INHIBIT 0.9 1.5 2.1 V
Ci Input capacitance at FIN–A, FIN–B 5 pF
Zi Input impedance at FIN–A, FIN–B 10 MΩ
IDD(Z) High-impedance-state PFD supply current See Note 6 0.01 1 µA
IDD(PFD) PFD supply current See Note 7 0.1 1.5 mA
NOTES: 6. Current into LOGIC VDD, when FIN–A, FIN–B = GND, PFD INHIBIT = VDD, no load, and VCO OUT is inhibited.7. Current into LOGIC VDD, when FIN–A, FIN–B = 1 MHz (VI(PP) = 3 V, rectangular wave), NC = GND, no load, and VCO OUT is
inhibited.
TLC2932IHIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
A-8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range, V DD = 3 V(unless otherwise noted)
VCO sectionPARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fosc Operating oscillation frequency RBIAS = 3.3 kΩ, VCO IN = 1/2 VDD 15 19 23 MHz
ts(fosc) Time to stable oscillation (see Note 8) Measured from VCO INHIBIT↓ 10 µs
t Rise timeCL = 15 pF, See Figure 3 7 14
nstr Rise timeCL = 50 pF, See Figure 3 14
ns
t Fall timeCL = 15 pF, See Figure 3 6 12
nstf Fall timeCL = 50 pF, See Figure 3 10
ns
Duty cycle at VCO OUT RBIAS = 3.3 kΩ, VCO IN = 1/2 VDD, 45% 50% 55%
α(fosc) Temperature coefficient of oscillation frequencyRBIAS = 3.3 kΩ, VCO IN = 1/2 VDD,TA = –20°C to 75°C 0.04 %/°C
kSVS(fosc) Supply voltage coefficient of oscillation frequencyRBIAS = 3.3 kΩ, VCO IN = 1.5 V,VDD = 2.85 V to 3.15 V
NOTES: 8. The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.9. The low-pass-filter (LPF) circuit is shown in Figure 28 with calculated values listed in Table 7. Jitter performance is highly dependent
on circuit layout and external device characteristics. The jitter specification was made with a carefully designed PCB with no devicesocket.
PFD sectionPARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fmax Maximum operating frequency 20 MHz
tPLZ PFD output disable time from low level 21 50ns
tPHZ PFD output disable time from high levelSee Figures 4 and 5 and Table 4
23 50ns
tPZL PFD output enable time to low levelSee Figures 4 and 5 and Table 4
11 30ns
tPZH PFD output enable time to high level 10 30ns
tr Rise timeCL = 15 pF See Figure 4
2.3 10 ns
tf Fall timeCL = 15 pF, See Figure 4
2.1 10 ns
TLC2932IHIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
A-9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, V DD = 5 V(unless otherwise noted)
VCO sectionPARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –2 mA 4 V
VOL Low-level output voltage IOL = 2 mA 0.5 V
VIT Input threshold voltage at SELECT, VCO INHIBIT 1.5 2.5 3.5 V
II Input current at SELECT, VCO INHIBIT VI = VDD or GND ±1 µA
Zi(VCO IN) Input impedance VCO IN = 1/2 VDD 10 MΩ
IDD(INH) VCO supply current (inhibit) See Note 4 0.01 1 µA
IDD(VCO) VCO supply current See Note 5 15 35 mA
NOTES: 4. Current into VCO VDD, when VCO INHIBIT = VDD, and PFD is inhibited.5. Current into VCO VDD, when VCO IN = 1/2 VDD, RBIAS = 3.3 kΩ, VCO INHIBIT = GND, and PFD is inhibited.
PFD sectionPARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage at FIN–A, FIN–B 4.5 V
VIL Low-level input voltage at FIN–A, FIN–B 1 V
VIT Input threshold voltage at PFD INHIBIT 1.5 2.5 3.5 V
Ci Input capacitance at FIN–A, FIN–B 5 pF
Zi Input impedance at FIN–A, FIN–B 10 MΩ
IDD(Z) High-impedance-state PFD supply current See Note 6 0.01 1 µA
IDD(PFD) PFD supply current See Note 7 0.15 3 mA
NOTES: 6. Current into LOGIC VDD, when FIN–A, FIN–B = GND, PFD INHIBIT = VDD, no load, and VCO OUT is inhibited.7. Current into LOGIC VDD, when FIN–A, FIN–B = 1 MHz (VI(PP) = 5 V, rectangular wave), PFD INHIBIT = GND, no load, and
VCO OUT is inhibited.
TLC2932IHIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
A-10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range, V DD = 5 V(unless otherwise noted)
VCO sectionPARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fosc Operating oscillation frequency RBIAS = 2.2 kΩ, VCO IN = 1/2 VDD 30 41 52 MHz
ts(fosc) Time to stable oscillation (see Note 8) Measured from VCO INHIBIT↓ 10 µs
t Rise timeCL = 15 pF, See Figure 3 5.5 10
nstr Rise timeCL = 50 pF, See Figure 3 8
ns
t Fall timeCL = 15 pF, See Figure 3 5 10
nstf Fall timeCL = 50 pF, See Figure 3 6
ns
Duty cycle at VCO OUT RBIAS = 2.2 kΩ, VCO IN = 1/2 VDD, 45% 50% 55%
α(fosc) Temperature coefficient of oscillation frequencyRBIAS = 2.2 kΩ, VCO IN = 1/2 VDD,TA = –20°C to 75°C 0.06 %/°C
kSVS(fosc) Supply voltage coefficient of oscillation frequencyRBIAS = 2.2 kΩ, VCO IN = 2.5 V,VDD = 4.75 V to 5.25 V
NOTES: 8: The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.9. The LPF circuit is shown in Figure 28 with calculated values listed in Table 7. Jitter performance is highly dependent on circuit layout
and external device characteristics. The jitter specification was made with a carefully designed PCB with no device socket.
PFD sectionPARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fmax Maximum operating frequency 40 MHz
tPLZ PFD output disable time from low level 21 40ns
tPHZ PFD output disable time from high levelSee Figures 4 and 5 and Table 4
20 40ns
tPZL PFD output enable time to low levelSee Figures 4 and 5 and Table 4
7.3 20ns
tPZH PFD output enable time to high level 6.5 20ns
tr Rise timeCL = 15 pF See Figure 4
2.3 10 ns
tf Fall timeCL = 15 pF, See Figure 4
1.7 10 ns
TLC2932IHIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
A-11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
tr tf
90%
10%
90%
10%VCO OUT
Figure 3. VCO Output Voltage Waveform
50%
90%10% 10%
50%
50%
tPHZtr tftPLZ
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
FIN–A†
FIN–B†
PFD INHIBIT
PFD OUT
(a) OUTPUT PULLDOWN(see Figure 5 and Table 4)
(b) OUTPUT PULLUP(see Figure 5 and Table 4)
† FIN–A and FIN–B are for reference phase only, not for timing.
90%
tPZLtPZH
GND
VOH50%50% 50%
VDD
VOL
Figure 4. PFD Output Voltage Waveform
Table 4. PFD Output Test Conditions
PARAMETER RL CL S1 S2tPZHtPHZ Open Close
tr1 kΩ 15 pF
O en Close
tPZL1 kΩ 15 pF
tPLZ Close Open
tf
Close O en
S1
S2
RL
CL
Test Point
PFD OUTDUT
VDD
Figure 5. PFD Output Test Conditions
TLC2932IHIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
A-12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 6
10
0
40
20
0 1 2 3
30
VCO OSCILLATION FREQUENCYvs
VCO CONTROL VOLTAGE
VCO IN – VCO Control Voltage – V
VDD = 3 VRBIAS = 2.2 kΩ –20°C
25°C
75°C
– V
CO
Osc
illat
ion
Fre
quen
cy –
MH
zf o
sc
Figure 7
60
40
0 1 2 3
80
VCO OSCILLATION FREQUENCYvs
VCO CONTROL VOLTAGE100
4 5
20
VCO IN – VCO Control Voltage – V
–20°C
25°C
75°C
VDD = 5 VRBIAS = 1.5 kΩ
– V
CO
Osc
illat
ion
Fre
quen
cy –
MH
zf o
sc
Figure 8
10
0
40
20
0 1 2 3
30
VCO OSCILLATION FREQUENCYvs
VCO CONTROL VOLTAGE
VCO IN – VCO Control Voltage – V
VDD = 3 VRBIAS = 3.3 kΩ
25°C
75°C
–20°C
– V
CO
Osc
illat
ion
Fre
quen
cy –
MH
zf o
sc
Figure 9
40
00 1 2 3
80
4 5
20
60
VCO OSCILLATION FREQUENCYvs
VCO CONTROL VOLTAGE
VDD = 5 VRBIAS = 2.2 kΩ
25°C
75°C
VCO IN – VCO Control Voltage – V
–20°C
– V
CO
Osc
illat
ion
Fre
quen
cy –
MH
zf o
sc
TLC2932IHIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
A-13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 10
10
0
40
20
0 1 2 3
30
VCO OSCILLATION FREQUENCYvs
VCO CONTROL VOLTAGE
VCO IN – VCO Control Voltage – V
–20°C
25°C
75°C
VDD = 3 VRBIAS = 4.3 kΩ
– V
CO
Osc
illat
ion
Fre
quen
cy –
MH
zf o
sc
Figure 11
40
00 1 2 3
80
4 5
20
60
VCO OSCILLATION FREQUENCYvs
VCO CONTROL VOLTAGE
VCO IN – VCO Control Voltage – V
–20°C
25°C
75°C
VDD = 5 VRBIAS = 3.3 kΩ
– V
CO
Osc
illat
ion
Fre
quen
cy –
MH
zf o
sc
Figure 12
20
15
10
30
25
2 2.5 3.5 4 4.5
– V
CO
Osc
illat
ion
Fre
quen
cy –
MH
z
VCO OSCILLATION FREQUENCYvs
BIAS RESISTOR
VDD = 3 VVCO IN = 1/2 VDDTA = 25°C
f osc
RBIAS – Bias Resistor – k Ω3
Figure 13
40
30
20
60
50
1.5 2 2.5 3.5
– V
CO
Osc
illat
ion
Fre
quen
cy –
MH
z
VCO OSCILLATION FREQUENCYvs
BIAS RESISTOR
VDD = 5 VVCO IN = 1/2 VDDTA = 25°C
f osc
RBIAS – Bias Resistor – k Ω3
TLC2932IHIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
A-14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 14
0.2
0.1
2 2.5 3.3
0.3
TEMPERATURE COEFFICIENT OFOSCILLATION FREQUENCY
vsBIAS RESISTOR
0.4
4 4.5
C°–
Tem
pera
ture
Coe
ffici
ent o
f Osc
illat
ion
RBIAS – Bias Resistor – k Ω
Fre
quen
cy –
% /
VDD = 3 VVCO IN = 1/2 VDDTA = –20°C to 75°C
3 3.5
(fos
c)α 0
Figure 15
0.2
0.1
1.5 2.2
0.3
TEMPERATURE COEFFICIENT OFOSCILLATION FREQUENCY
vsBIAS RESISTOR
0.4
3.5RBIAS – Bias Resistor – k Ω
VDD = 5 VVCO IN = 1/2 VDDTA = –20°C to 75°C
2 2.5 3
C°–
Tem
pera
ture
Coe
ffici
ent o
f Osc
illat
ion
Fre
quen
cy –
% /
(fos
c)α
0
Figure 16
20
18
163.05 3
22
VCO OSCILLATION FREQUENCYvs
VCO SUPPLY VOLTAGE
24
3.15VDD – VCO Supply Voltage – V
RBIAS = 3.3 kΩVCO IN = 1.5 VTA = 25°C
– V
CO
Osc
illat
ion
Fre
quen
cy –
MH
zf o
sc
Figure 17
40
36
324.75 5
44
VCO OSCILLATION FREQUENCYvs
VCO SUPPLY VOLTAGE
48
5.25VDD – VCO Supply Voltage – V
RBIAS = 2.2 kΩVCO IN = 1/2 VDDTA = 25°C
– V
CO
Osc
illat
ion
Fre
quen
cy –
MH
zf o
sc
TLC2932IHIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
A-15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 18
0.03
0.02
0.01
2 2.5 3.5 4
0.04
SUPPLY VOLTAGE COEFFICIENT OF VCOOSCILLATION FREQUENCY
vsBIAS RESISTOR
0.05
4.5RBIAS – Bias Resistor – k Ω
VDD = 2.85 V to 3.15 VVCO IN = 1/2 VDDTA = 25°C
3
V
– S
uppl
y V
olta
ge C
oeffi
cien
t of V
CO
Osc
illat
ion
Fre
quen
cy –
% /
(fos
c)α
0
Figure 19
0.005
1.5 2.5 3
0.01
3.5RBIAS – Bias Resistor – k Ω
SUPPLY VOLTAGE COEFFICIENT OF VCOOSCILLATION FREQUENCY
vsBIAS RESISTOR
VDD = 4.75 V to 5.25 VVCO IN = 1/2 VDDTA = 25°C
2
V
– S
uppl
y V
olta
ge C
oeffi
cien
t of V
CO
Osc
illat
ion
Fre
quen
cy –
% /
(fos
c)α
0
Figure 20
20
15
10
30
25
2 2.5 3.5 4 4.5
Rec
omm
ende
d Lo
ck F
requ
ency
– M
Hz
RECOMMENDED LOCK FREQUENCY(×1 OUTPUT)
vsBIAS RESISTOR
RBIAS – Bias Resistor – k Ω
VDD = 2.85 V to 3.15 VTA = –20°C to 75°C
3
Figure 21
40
30
20
101.5 2 2.5
50
60
3.5RBIAS – Bias Resistor – k Ω
Rec
omm
ende
d Lo
ck F
requ
ency
– M
Hz
RECOMMENDED LOCK FREQUENCY(×1 OUTPUT)
vsBIAS RESISTOR
VDD = 4.75 V to 5.25 VTA = –20°C to 75°C
3
TLC2932IHIGH-PERFORMANCE PHASE-LOCKED LOOP
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A-16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 22
Rec
omm
ende
d Lo
ck F
requ
ency
– M
Hz
RECOMMENDED LOCK FREQUENCY(×1/2 OUTPUT)
vsBIAS RESISTOR
RBIAS – Bias Resistor – k Ω
10
7.5
5
15
12.5
2 2.5 3.5 4 4.53
VDD = 2.85 V to 3.15 VTA = –20°C to 75°CSELECT = VDD
Figure 23
RBIAS – Bias Resistor – k Ω
Rec
omm
ende
d Lo
ck F
requ
ency
– M
Hz
RECOMMENDED LOCK FREQUENCY(×1/2 OUTPUT)
vsBIAS RESISTOR
20
15
10
51.5 2 2.5
25
30
3.53
VDD = 4.75 V to 5.25 VTA = –20°C to 75°CSELECT = VDD
TLC2932IHIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
A-17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
gain of VCO and PFD
Figure 24 is a block diagram of the PLL. Thecountdown N value depends on the inputfrequency and the desired VCO output frequencyaccording to the system application requirements.The Kp and KV values are obtained from theoperating characteristics of the device as shownin Figure 24. Kp is defined from the phase detectorVOL and VOH specifications and the equationshown in Figure 24(b). KV is defined fromFigures 8, 9, 10, and 11 as shown in Figure 24(c).
The parameters for the block diagram with theunits are as follows:
KV : VCO gain (rad/s/V)Kp : PFD gain (V/rad)Kf : LPF gain (V/V)KN : count down divider gain (1/N)
external counter
When a large N counter is required by theapplication, there is a possibility that the PLLresponse becomes slow due to the counterresponse delay time. In the case of a highfrequency application, the counter delay timeshould be accounted for in the overall PLL design.
RBIAS
The external bias resistor sets the VCO center frequency with 1/2 VDD applied to the VCO IN terminal. However,for optimum temperature performance, a resistor value of 3.3 kΩ with a 3-V supply and a resistor value of 2.5kΩ for a 5-V supply is recommended. For the most accurate results, a metal-film resistor is the better choicebut a carbon-compositiion resistor can be used with excellent results also. A 0.22 µF capacitor should beconnected from the BIAS terminal to ground as close to the device terminals as possible.
hold-in range
From the technical literature, the maximum hold-in range for an input frequency step for the three types of filterconfigurations shown in Figure 25 is as follows:
H 0.8 Kp KV Kf ()
WhereKf (∞) = the filter transfer function value at ω = ∞
Divider(KN = 1/N)
PFD(Kp)
VCO(KV)
LPF(Kf)
TLC2932
f REF
VOH
fMAX
fMIN
VIN MIN VIN MAX
–2π 2π–π 0 π
Range of Comparison
VOH
VOL
Kp =VOH – VOL
4π KV =2π(fMAX – fMIN)
VIN MAX – VIN MIN
Figure 24. Example of a PLL Block Diagram
(a)
(c)(b)
TLC2932IHIGH-PERFORMANCE PHASE-LOCKED LOOP
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A-18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
low-pass-filter (LPF) configurations
Many excellent references are available that include detailed design information about LPFs and should beconsulted for additional information. Lag-lead filters or active filters are often used. Examples of LPFs are shownin Figure 25. When the active filter of Figure 25(c) is used, the reference should be applied to FIN-B becauseof the amplifier inversion. Also, in practical filter implementations, C2 is used as additional filtering at the VCOinput. The value of C2 should be equal to or less than one tenth the value of C1.
R1
C1T1 = C1R1
(a) LAG FILTER
R1
C1
T1 = C1R1T2 = C1R2
R2
(b) LAG-LEAD FILTER
R2 C1
R1T1 = C1R1T2 = C1R2
(c) ACTIVE FILTER
A–
VI VOVI VO
VI
C2
VO
C2
Figure 25. LPF Examples for PLL
the passive filter
The transfer function for the lag-lead filter shown in Figure 25(b) is;
VOVIN
1 s T21 s (T1 T2)
WhereT1 R1 C1 and T2 R2 C1
Using this filter makes the closed loop PLL system a second-order type 1 system. The response curves of thissystem to a unit step are shown in Figure 26.
the active filter
When using the active integrator shown in Figure 25(c), the phase detector inputs must be reversed since theintegrator adds an additional inversion. Therefore, the input reference frequency should be applied to the FIN-Bterminal and the output of the VCO divider should be applied to the input reference terminal, FIN-A.
The transfer function for the active filter shown in Figure 25(c) is:
F(s) 1 s R2 C1s R1 C1
Using this filter makes the closed loop PLL system a second-order type 2 system. The response curves of thissystem to a unit step are shown in Figure 27.
basic design example
The following design example presupposes that the input reference frequency and the required frequency ofthe VCO are within the respective ranges of the device.
TLC2932IHIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
A-19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
basic design example (continued)
Assume the loop has to have a 100 µs settling time (ts) with a countdown N = 8. Using the Type 1, second orderresponse curves of Figure 26, a value of 4.5 radians is selected for ωnts with a damping factor of 0.7. Thisselection gives a good combination for settling time, accuracy, and loop gain margin. The initial parameters aresummarized in Table 5. The loop constants, KV and Kp, are calculated from the data sheet specifications andTable 6 shows these values.
The natural loop frequency is calculated as follows:
nts 4.5
Then
n 4.5
100 s 45 k-radianssec
Since
Table 5. Design Parameters
PARAMETER SYMBOL VALUE UNITS
Division factor N 8
Lockup time t 100 µs
Radian value to selected lockup time ωnt 4.5 rad
Damping factor ζ 0.7
Table 6. Device Specifications
PARAMETER SYMBOL VALUE UNITS
VCO gain 76.6 Mrad/V/s
fMAX 70 MHz
fMIN KV 20 MHz
VIN MAX
KV5 V
VIN MIN 0.9 V
PFD gain Kp 0.342357 V/rad
Table 7. Calculated Values
PARAMETER SYMBOL VALUE UNITS
Natural angular frequency ωn 45000 rad/sec
K = (KV • Kp)/N 3.277 Mrad/sec
Lag-lead filterCalculated valueNearest standard value
R11587016000
Ω
Calculated valueNearest standard value
R2308300
Ω
Selected value C1 0.1 µF
TLC2932IHIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
A-20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Using the low-pass filter in Figure 25(b) and divider ratio N, the transfer function for phase and frequency areshown in equations 1 and 2. Note that the transfer function for phase differs from the transfer function forfrequency by only the divider value N. The difference arises from the fact that the feedback for phase is unitywhile the feedback for frequency is 1/N.
Hence, transfer function of Figure 24 (a) for phase is
2(s)1(s)
Kp KV
N (T1 T2)
1 s T2
s2 s 1 KpKV T2
N(T1T2) KpKV
N(T1T2)
(1)
and the transfer function for frequency is
FOUT(s)FREF(s)
Kp KV
(T1 T2)
1 s T2
s2 s1 KpKVT2
N(T1T2) KpKV
N(T1T2)
(2)
The standard two-pole denominator is D = s2 + 2 ζ ωn s + ωn2 and comparing the coefficients of the denominatorof equation 1 and 2 with the standard two-pole denominator gives the following results.
n Kp KV
N (T1 T2)
Solving for T1 + T2
T1 T2 Kp KVN 2
n
(3)
and by using this value for T1 + T2 in equation 3 the damping factor is
n2 T2 N
Kp KV
solving for T2
T2 2 – N
Kp KV
then by substituting for T2 in equation 3
T1 KV Kp
N 2n
–2 n
NKp KV
TLC2932IHIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
A-21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
From the circuit constants and the initial design parameters then
R2 2 n
NKp KV
1C1
R1 Kp Kv
2n N
2 n
NKp KV
1
C1
The capacitor, C1, is usually chosen between 1 µF and 0.1 µF to allow for reasonable resistor values andphysical capacitor size. In this example, C1 is chosen to be 0.1 µF and the corresponding R1 and R2 calculatedvalues are listed in Table 7.
TLC2932IHIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
A-22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
00 1 2 3 4 5 6 7 8 9 10 11 12 13
ωnt
(t),
Nor
mal
ized
Res
pons
eφ 2
= 0.1
= 0.2
= 0.3
= 0.4
= 0.5 = 0.6
= 0.7
= 0.8
= 1.0
= 1.5
= 2.0
ωnts = 4.5
Figure 26. Type 1 Second-Order Step Response
TLC2932IHIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
A-23POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
00 1 2 3 4 5 6 7 8 9 10 11 12 13
ωnt
(t),
Nor
mal
ized
Out
put F
requ
ency
φ 0
ζ = 0.8
ζ = 0.1
ζ = 0.2
ζ = 0.3
ζ = 0.4
ζ = 0.5
ζ = 0.6
ζ = 0.7
ζ = 1.0
ζ = 2.0
Figure 27. Type 2 Second-Order Step Response
TLC2932IHIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
A-24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
1/2 fosc
PhaseComparator
AGND
DGND
DGND
DGND
REF IN
DVDD
AVDDVDD
LOGIC VDD (Digital)
LOGIC GND (Digital)
SELECT
FIN–A
VCO INHIBIT
PFD INHIBIT
NC
VCO GND
VCO IN
BIAS
VCO VDD
VCO
R1†
R3
C1R2C2
R4 R5 R6
S3
S4
S5
DivideByN
0.22 µF
1
2
3
4
5
6
7
14
13
12
11
10
9
8
FIN–B
† RBIAS resistor
VCO OUT
PFD OUT
Figure 28. Evaluation and Operation Schematic
PCB layout considerations
The TLC2932I contains a high frequency analog oscillator; therefore, very careful breadboarding andprinted-circuit-board (PCB) layout is required for evaluation.
The following design recommendations benefit the TLC2932I user:
External analog and digital circuitry should be physically separated and shielded as much as possible toreduce system noise.
RF breadboarding or RF PCB techniques should be used throughout the evaluation and productionprocess.
Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductanceand resistance. The ground plane is the better choice for noise reduction.
LOGIC VDD and VCO VDD should be separate PCB traces and connected to the best filtered supply pointavailable in the system to minimize supply cross-coupling.
VCO VDD to GND and LOGIC VDD to GND should be decoupled with a 0.1-µF capacitor placed as closeas possible to the appropriate device terminals.
The no-connection (NC) terminal on the package should be connected to GND.
NOTES: A. All linear dimensions are in millimeters.B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Running Title—Attribute Reference
B-1 Chapter Title—Attribute Reference
TC9122P Data Sheet Summary
This appendix presents a summary of the TC9122P data sheet.
Topic Page
B.1 Reference Information for the TC9122P Programmable Counter B-2. .
B.5 Electrical Characteristics at V DD = 7.5 V, TA = 25C B-4. . . . . . . . . . . . . .
Appendix B
Reference Information for the TC9122P Programmable Counter
B-2
B.1 Reference Information for the TC9122P Programmable Counter
The device connections, terminal functions, absolute maximum ratings, andelectrical characteristics reference data included in this document is from theTOSHIBA TC9122P data sheet.
B.2 Device Connections
The connections of the TC9122P are shown in Figure B–1.
Figure B–1.TC9122P Connections
5 V
N = 103 102 101 100
16 15 14 13 12 11 10 9 8 7 6 5 4 3
B3 A3 D2 C2 A2D1 C1 B1 A1 D0 C0 B0 A0B217 2
OUT IN
18 1
5 V
TC9122P
Terminal Functions
B-3 TC9122P Data Sheet Summary
B.3 Terminal Functions
The TC9122P terminal functions are shown in Table B–1.
Table B–1.TC9122P Terminal Functions
TerminalNo.
Name Description Notes
2 INProgrammable counter input. As this input has the self-biased amplifierinternally, input frequency can be a small signal by capacitive couplingthe input.
Internalamplifier
3–6 A0–D0 100
Program input to set divide value N by BCD. N can be set from 8 to 3999.The values below must not be set.
Eachterminal3–6 A0–D0 100
A0 B0 C0 D0 A1 B1 C1 D1 A2 B2 C2 D2 A3 B3
te ahas apull-down
7–10 A1–D1 101 10
01
00
00
00
00
00
00
00
00
00
00
00
00
pull-downresistorinternally.
11–14 A2–D2 102101
100
011
000
000
000
000
000
000
000
000
000
000
000
15, 16 A3, B3 103
101
011
111
000
000
000
000
000
000
000
000
000
000
000
17 OUTProgrammable counter output. 1/N of the IN frequency appears at thisoutput.
1, 18VDD,GND
Power supply and ground.
B.4 Absolute Maximum Ratings, T A = 25°C
The TC9122P absolute maximum ratings at TA = 25°C are shown inTable B–2.
Table B–2.TC9122P Absolute Maximum Ratings
Supply voltage range, VDD –0.3 V to 10 V
Input voltage range, VI –0.3 V to VCC + 0.3 V
Operating temperature range, TA –30°C to 75°C
Storage temperature range, Tstg –55°C to 125°C
Electrical Characteristics
B-4
B.5 Electrical Characteristics at V DD = 7.5 V, TA = 25°C
The TC9122P electrical characteristics are shown in Table B–3.
Table B–3.TC9122P Electrical Characteristics
Parameter Test Conditions Min Typ Max Unit
VDD Supply voltage 4.5 8.5 V
VI(PP) Input voltage swing fI = 15 MHz, VI = 2 Vp-p 2 7 Vp-p
IDD Supply current 15 30 mA
VIH High-level input voltage 5.5 VDD+0.3 V
VIL Low-level input voltage –0.3 2 V
VOH High-level output voltage IOH = –0.5 mA 6.5 V
VOL Low-level output voltage IOL = 0.5 mA 1 V
f Operating frequency (see Note 1) 1 15 MHz
RIN Input pulldown resistor 20 80 kΩ
Rf Amplifier feedback resistor 100 500 kΩ
NOTE 1: VDD = 7.5 V ±10%, VI(PP) = 2 Vp-p, TA = 30°C to 75°C