Beschrijving joint servo computer Linssen, Roel Gepubliceerd: 01/01/1985 Document Version Uitgevers PDF, ook bekend als Version of Record Please check the document version of this publication: • A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website. • The final author version and the galley proof are versions of the publication after peer review. • The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication Citation for published version (APA): Linssen, R. (1985). Beschrijving joint servo computer. (TH Eindhoven. Afd. Werktuigbouwkunde, Vakgroep Produktietechnologie : WPB; Vol. WPB0164). Eindhoven: Technische Hogeschool Eindhoven. General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. • Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policy If you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. Download date: 11. May. 2018
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Beschrijving joint servo computer
Linssen, Roel
Gepubliceerd: 01/01/1985
Document VersionUitgevers PDF, ook bekend als Version of Record
Please check the document version of this publication:
• A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differencesbetween the submitted version and the official published version of record. People interested in the research are advised to contact theauthor for the final version of the publication, or visit the DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers.
Link to publication
Citation for published version (APA):Linssen, R. (1985). Beschrijving joint servo computer. (TH Eindhoven. Afd. Werktuigbouwkunde, VakgroepProduktietechnologie : WPB; Vol. WPB0164). Eindhoven: Technische Hogeschool Eindhoven.
General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright ownersand it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.
• Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ?
Take down policyIf you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediatelyand investigate your claim.
De THE is sinds twee jaar betrokken bij een onderzoek
programma op het gebied van Flexibele Automatisering
Industriele Robots. Dit project, FAIR genaamd, vindt
zijn oorsprong in toenemende noodzaak om het productie
proces te automatiseren.
Dit automatiseren is weer nodig om de concurrentieposi
tie van Nederland t.o.v. andere landen (bv. Amerika en
Japan) te verbeteren.
1.2 Besturing robot
In het project FAIR is het onder meer de bedoeling om
onderzoek te plegen aan een robot met 5 assen. (zie fig. 1.1 )
Send
,...-...."",.~.:!r----........,....~~. /\ , -'- Tum
"'~~~~_";"" ___ --'"""".r J If
'------Wrtst
-------Upp~r Jrm
-----Lower arm
+---------·--Sl'and
-+---·-------Pedestal
fig. 1.1 "Robot project FAIR It
De besturing vindt plaats d.m.v. microcomputers die ver
sterkers aansturen om de motoren te laten draaien.
6
Omdat het bewegen van de robot vrij vee I berekeningen kost en omdat di t berekenen·in een zeer· korte tijd moet
gebeuren ( 1 ms.) maakt men gebruik van een " multi
processing-" systeem. Hier wordt voor elke as een apar
te microcomputer genomen, die aIleen voor zijn eigen as
de berekening uitvoert.
AIle microcomputers zijn door een busstructuur met elkaar
verbonden en ~en microcomputer zal de centrale leiding
hebben over aIle micro-computers. De hele besturing zal er dan als volgt uitzien. (zie fig 1.2 )
fig. 1.2 It Besturing robot tf
Het grote voordeel van multiprocessing is dus dat wanneer er een beweging gemaakt moet worden, de berekeningen vaar
elke as tegelijk worden uitgevoerd. Zo is het mogelijk om binnen een totale rekentijd van 1 ms. te blij'ven. Bij dit laatste is ook rekening gehouden met de keuze voor
een microprocessor. Omdat alles zo snel mogelijk moet zijn
is er voor een 16-bit processor gekozen.
De T.H. zelf heeft alle onderdelen die bij de besturing
nodig zijn zelf ontwikkeld, tot aan de microcomputer toe.
In feite komt het er op neer dat aIleen de mechanische
robot zoals te zien op fig. 1.1 gekocht is.
7
In dit verslag zal de microcomputer zelf aan bod komen.
In het tweede hoofdstuk zullen we de gebruikte micro
processor (Intel iAPX 80186) bespreken waarna in hoofd
stuk 3 de gehele microcomputer met al zijn komponenten
behandeld wordt.
OPMERKING
In dit verslag zijn gewoon aIle Engelse termen gebruikt
die in de computerwereld gebruikelijk zijn. Dit is op de
eerste plaats gedaan omdat er vaak geen goede Nederlandse vertaling mogelijk is en op de tweede plaats zo'n vertaling
vaak verwarring met zich meebrengt.
De termen met een * zijn in de hieropvolgende termenlijst opgenomen.
8
TERMENLIJST
Co-processing : Twee of meer processoren delen dezelfpe
instructiestroom. Ze volgen hetzelfde pro
gramma, maar voeren om de beurt instructies
uit omdat bepaalde instructies beter door
een bepaalde processor kunnen worden uit
gevoerd. (bv. een speciale rekenprocessor)
Multi-processing: Twee of meer processoren delen dezelfde
geheugenruimte, maar opereren op verschil
lende instructiestromen. Elke processor
heeft dus zijn eigen programma. (vaak
heeft een processor de leiding)
Time-multiplexing Met deze methode is het mogelijk om een
aantal pennen op een processor gedurende
bepaalde tijdsintervallen andere functies
te geven. Dit om het aantal aansluitpennen
van de processor (of ander I.C.) te ver
minderen.
Tegenwoordig is het veel gebruikelijk om bij een microprocessor zowel data-
als adresbus op dezelfde pennen aan te
sluiten. Dit is mogelijk omdat de proces
sor toch niet de twee bussen tegelijk kan
gebruiken.
~9
2 DE MICROPROCESSOR iAPX 80186
2.1 Inleiding 16-bit processoren
De toegepaste microprocessor, de 80186 van Intel, is een
16-bit processor. Zoals eerder vermeld heeft men voor deze
16-bit processor gekozen omdat hij snel is, maar de 16-bit
processor heeft nog een aantal voordelen (bv. t.o.v. een
8-bit processor) die we bij ons robotproject goed kunnen gebruiken:
- de microprocessor is zeer snel (klokfrequentie 8 Mhz)
16-bit processoren zijn door hUn structuur in staat tot multi-~en coprocessing~
- de 16-bit is erg nauwkeurig (16 bits data t.o.v.
8 bits data)
- de 16-bit kan een groot geheugen aanschrijven
( 1 Megabyte)
instructieset van de 16-bit processor is veel uit
gebreider en krachtiger dan bv. van een 8-bit.
We zullen nu in het kort de opbouw van de 80186 behandelen.
Voor een uitgebreide informatie willen we dan ook verwij
zen naar het Intel Handbook Vol. I (lit. 2 zie blz. 26 )
2.2 De 80186
De opbouw van de 80186 bestaat in feite uit 6 aparte func
tionele blokken. (zie fig. 2.1 )
c.P.U. - D.M.A.
Timers
( Central proces Unit)
( Direct Memory Acces )
Interrupt Controller
Chip Selector
Bus Controller
10
o
CLOCK
ENHANCED 8088-2 or
8088·2 CPU
DMA CHANNELS
INTERRUPTS
fig. 2.1 tt Blokschema iAPX 80186 n
TIMERS
Door deze opbouw is er een makkelijk computersysteem mage-
lijk omdat al deze blokken reeds op ~~n I.C. bijelkaar zitten en dus ook al op de juiste manier met elkaar verbonden
zijn. We zullen een paar belanrijke blokken in het kort behan- -
del en. (Op bi jlage I bIz. 28 is een ui tgebreider blokschema
met gegevens over de 80186 aanwezig.)
2.2.1 De C.P.U.
De Central Proces Unit bestaat bij de 80186 uit twee gedeelten: de Execution Unit (EU) en de Bus Interface Unit (BIU).
Dit stelt de microprocessor in staat om "instruction queing tt
toe te passen. Bij instruction queing hoeft de processor wanneer hij klaar
is met een instructie, geen nieuwe instructie uit het
11
geheugen op te halen. Deze staan al klaar in een soort buf
fer, de instruction queue. De Bus Interface Unit (BIU)
zorgt srvoor dat deze kleine buffer steeds vol blijft met
instructies. De Execution Unit hoeft deze instructies al
leen maar uit te voeren. Hierdoor wordt de belasting van
data en adresbussen verlaagd waardoor de computer sneller
en efficienter kan werken. (zie fig. 2.2 )
EXECUTION UNIT (EU) BUS INTERFACE ONIT (IIU)
I GEI4ERAL
I SEGMENT
RE"ISTERS REGISTERS
AI
""" I I INSTRUCTION
POINTER
I t I "III ~ I ADDRESS
MULTIPLEXED aus GENERATION ... ~ ! t AND IUS
I CONTROL
n I ... ,.. I INSTRUCTION
I QUEUE
• I I AlU
FLAGS
fig. 2.2 "CPU met EU en BIU"
De CPU bevat 14 registers. Hiervan z~Jn er 8 voor algemeen gebruik. Deze registers bestaan uit 4 data registers: accumulator-, base-, counter- en dataregister, en 4 pointer/in
dex registers: stack pointer, basepointer, sourceindex en destinationindex. Al deze registers zijn 16 bit, maar de
dataregisters kunnen zowel als 8 of16 bit register
12
gebruikt worden. Hiervoor wordt er dan gebruik gemaakt
van een upper- en lower part. (zie fig. 2.3)
AX
IX
CX
OX
SP
lip 51
Of
CS
os SS
ES
IP STATUS WORD
OR FLAGS
DATA REGISTERS
01 At! A~
lit! 8L
CH CL
DH OL
POINTER AND INDEX REGISTERS
15 0
I I SEGMENT REGISTERS
15 0
I I INSTRUCTION POINTER AND FLAGS
15 0
I 10lDlllrlslzi !Allp! iel IS 11 10 9 i 1 6 5 4 J 2 1 0
STACK POINTf:A
SASE POINTER
SOURCE INDEX
DESTINATION INDEX
CODe
DATA
STACK
EXTIIA
INSTRUCTION POINTER
fig. 2.3 It Registerset van de 80186 n
Behalve de 8 registers voor algemeen gebruik zijn er nog 4 16-bit segment registers: code-, stack-, data- en extrasegmentregister. Vervolgens resten aIleen nog de instructie pointer en het status word register (de vlaggen) Op bijlage II blz.33 is vermeld waar aIle registers voor gebruikt worden en tevens is hier de inhoud van het status word register gegeven.
13
De 80186 kan 1 Megabyte geheugen aanschrijven. Hiervoor
maak t men gebruik van segmentatie. Di t is een methode van
adressering waarbij twee gegevens nodig zijn: de offset
en een basesegment. Het basesegment wijst een gebied in
het geheugen aan (segment) en met de offset wijst men naar
de geheugenplaats binnen dat segment. Om het feitelijke
adres te berekenen wordt de base met 16 vemenigvuldigd
en bij de offset opgeteld. (zie fig. 2.4 ) Op deze wijze
krijgt men een 20 bits brede adressering zodat men tot 1 Megabyte kan adresseren.
IS' ( I ) offset
7- 0 adres (x
+ C I ) base IS + 0 segment
I ) 20 bits f. 0 adres.
(~----~~----~----~ ______ L-____ ~ 19
fig. 2.4 n segmentatie adres "
16)
Om deze adressen samen te stellen bezit de 80186 24 ver
schillende mogelijkheden. Op bijlage III blz. 34 zijn enke
le van deze mogelijkheden gegeven.
2.2.2 Direct Memory Access controller
De 80186 bezit twee onafhankelijke zeer snelle Direct Memo
ry Access kanalen die onafhankelijk van de CPU kunnen wer
ken. De DMA-kanalen zorgen ervoor dat er data (bytes/words)
getransporteerd wordt tussen alle componenten die d.m.vv-~
interne bus met elkaar verbonden zijn.
14
2.2.3 Timer
De timer bevat drie 16-bit timer/counters die ook weer
onafhankelijk van de CPU kunnen werken. Twee ervan kunnen
voor externe doeleinden gebruikt worden. Ze zijn in staat
om bv. blokgolven te produceren m.b.v. de CPU-klok of een externe k 10k.
De derde timer- telt alleen de CPU-kloksignalen en kan voor verschillende doeleinden gebruikt worden:
interrupt geven aan de CPU
de andere timers starten
een DMA-kanaal een puls geven om bepaalde
data op te halen.
V~~r een uitgebreidere behandeling van deze genoemde blok
ken en tevens van de interruptcontroller, chip-selector
en de interne bus wil ik graag verwijzen naar lit. 2 hoofd
stuk 5 • (zie blz. 26)
In het volgend~ hoofdstuk gaan we bekijken op welke manier
deze 80186 nu gebruikt wordt in de ontworpen computer.
15
3 DE JOINT SERVO COMPUTER
3.1 Inleiding
Voordat er met de 80186 een compleet microprocessorboard
kan worden opgebouwd, moeten we eerst de eisen waaraan de
joint servo computer moet voldoen uitdiepen. In verband
met de in/uitgangspoorten (I/O) zal er van te voren be
keken moeten worden wat er gemeten en geregeld moet worden.
Tevens is het van belang om te weten in hoeveel bits deze metingen verricht worden.(dit i.v.m. de nauwkeurigheid)
Om hier iets meer over te weten te komen zullen we het blokdiagram van de aansturing van een motor bekijken. (zie fig. 3.1)
• High Performance Numerical Coprocessing Capability Through 8087 Interface
~ IHTI!IIR1JPI'
CONTAOI,lJUI
::Xmir~ I
.. UGOUHT _TEA A
~---+ORO'
Flgur.1. IAPX 188 BlGck Diagram
28
The IntellAPX 18&(80186 part number) Is 8 hlghl' Integrated 1e;.bit microprocessor. The IAPX 186 effectively combines 15-20 of the most common iAPX 86 system components onto one. The 80186 provides two times greater throughput than the standard 5 MHz IAPX 86. The IAPX 186 is upward compatible with iAPX 86 and 86 softwara and adds 10 new Instruction types to the existing set.
Ffgure 2. 801. PInout OIagram
Symbol PIn No. ~ Name end Functian Vee. Vee 9.43 I S'!S\liI!II Power: + 5 d poMr IlUllOty.
Vss. Vss 26,60 I System Ground.
RESEr 57 0 ReNt 0utI3ut Indk:ale.lllat ilia 80186 CPU it: being reset. and can be used as a system ",alit. It is ac:!Mt HIGH. synchfoni%ed with 1119 PIOCIJSSOI' clock. and lasts an integer number of clock periods COI'I'QI)OfIdlng 10 IIIe length of 111411 RES signat.
Xl.X2 . 59.58 , CIystaI Inputs, Xl and X2. provide an axtemal connection lor a fundamental mode . PII","eI resonant crystal lor 111411 Intemat crystal oscillator. Xl can Interface 10 an extemeI clock IrIsIead of a crystal. In 1111. case. minimize IIIe capacitance on X2 or driWI X2 with comp/ementad X 1. The input or oacHlator frequency Is internally dMded
. ' . by two 10 generate IIIe clock signal (CLKOlII'} •
CU<OUT 56 0 CJoc:k 0utI3ut provides IIIe system wtth II 5O'lI! duty ~ WllMfonn. AI device pin timings are tQeCIlIed refatMllo C1.KOUT. CU<OUT has sufllelent MaS driWI capabillllea lor IIIe 8087 Numeric Proceseor Ex1anslon.
RES 24 I System ReNt causes ilia 8018610 Immediately 1ermlnate Its present actIvily. ctear IIIe Inklmal logic, and enter a dormant stale. This signal may be asynchronous 10 IIIe
. 80186 clock. TIle 80186 begins latching Instructlons approximalely 7 clock ~s after RES Is returned HIGH. RES is AI<lUIred 10 be LOW lor glllater IIIan .. clock ~ and Is Internally syncI\fonized. FOr J)I'OI)er inlliall%atfon. IIIe LOW-to-HIGH lnInll-lion of Am must cccur no sooner IIIan 50 microlleconds after poMr up. This Input is IIIOVIded with a Sdlmitt-1riggeI' 10 faclillale poMr-Oll Am generellon via an RC net'M)rk. When Am occurs. lIIe 80188 will drl'le IIIe SItUs nnss 10 an 1nactM!t level lor OM clock. and IIIan \ri-stale them.
29
BIJLAGE I C GEGEVENS iAPX 80186
Table 1. 10188 PIn Deacnptlon (Continued) "
Pin Symbol No. Type Name and Function
TEST 47 I TEST is _mined by the WAIT instruction. If the TEST input is HIGH when "WAIT" execution !legins. instruction execution will sUSj)end. TEST will be resampled until it goes Low. at which time execution will resume. If interrupts are enabled while the 80 t86 is waiting tor fEST. interrupts will be serviced, This
·input is synchronized internally.
TMR INO. 20 I Timer Inputs are used either all clock or control signals, depending upon the TMR INt 21 I programmed timer mode. These inputs are active HIGH (or lOW-to-HIGH
transitions are counted) and internally synchronized.
TMROUTO. 22 0 Timer outputs are used to provide single pulse or continuous waveform 98Oer-TMR OUT 1 23 0 alion. depending upon the timer mode selected.
ORQO 18 I OMA Request is driven HIGH by an external device when it desires thai a ORal 19 I OMA channel (Channel 0 or 1) perform a transfer. These signall are.active
HIGH, level-triggered, and internally synchronized.
NMI 46 I Non·Mallkable Interrupt is an edge-triggered input which causes a type 2 interrupt. NMI is not meskable internally. A transition from a I.OW to HIGH initilliea the interrupt at the next instruction boundary. NMI is latched inte ... nally. An NMI duration of one clock or more will guarantee service. This input is internally synchronized.
INTO. INn, <45.44 I Maskable Interrupt Requests can be requested bV stroCing one of these pins. INT2JiNm 42 I/O When configured as inputs, these pins are active HIGH. Interrupt Requests are 1NT3IiNTA1 41 I/O synchronized internally, INT2 and INT3 may be configured via software to
provide active-I.OW interrupt-acknowledge output signals. All interrupt inputs may be configured via software 10 be either edge- or level-triggered. To ensure recognition. all interrupt requests must remain active until the interrupt is acknowleged. When IRMX mode is selected, the function of these pins
I changes (see Interrupt Controller section of this data sl'leetl.
Al91S6, 65 0 Address Bus Outputs (16-19) and Bus Cycle Status (3-6) reflect the four most Al8/SS, 68 0 significant address bits during T,. These signals are active HIGH. During T2. A17/54, 67 0 T3. Tw. and T •• status information is available on these lines all encoded Al6/63 68 0 below:
I I low
I High I 56 Processor Cycle OMACycie
63.54. and 55 are defined all LOW during T 2-T •.
AC1S-ADO 10-17, tlO AddrelliDeta Bus (0-15) lignall conllitute the time muliplexed memory or 110 1..a addr ... (T,) and data (T2. T3. Tw. Ind T .. ) bus. The bus II ective HIGH. Ao 'a
analogous to 8Fi'E tor the lower byte of the data bus. pins 07 through 00. It is LOW during'T1 when a byle is 10 be transferred onlO the lower portion of the
, bus in mamory or I/O operations.
iIHEIS7 64 0 During T1 the Bu. High Enable signahhould be used to determine if date is to be enabled onto the most significant half 01 the data bus, pins 0,5 -Os. !FiE is LOW during T1 lor read. write, and interrupt acknowledge cycles when I byte ill to be transferred on the higher hllit 01 the bus. The 57 status information is available during T2. T3, and T •. 57 Is logicallyequivalentto SHE. The signal is active Low. and is Iristated OFF during bus HOLD.
SHE and AO Encodlngs
!mE: Value AO Value Function
0 0 Word Transfer "
0 1 Byte 1I'ansfer on upper half of data bUI (015-08) 1 0 Byte 1I'ansfer on lower half 01 data bus (07-00) 1 1 Reserved
30
BIJLAGE I D GEGEVENS iAPX 80~86
Table 1. 80188 Pin o..crlptlon (ContlnHd)
PIn Symbof No. Type Name and Function ..
ALE/QSO 61 0 Address Latch EnabielOueue Status 0 is provided by the 80188 to latch the address Into the 828218283 address latches. ALE is active HIGH. Addreues ara guarantaacftQ. be valid on tha trailing edga of ALE. Tha AU: rising edga Is generated off the rising edg9 of the CLKOUT immediately preceding T1 of the associated bus eyele, effectively one-half clock cycle earlier than In the stan-dard 8088. The trailing edge is generated off the CLKOUT rising edg9ln T1 as In the 8088. Note that ALE is never floated.
WAIOSl 63 0 Write Strobe/Queue Status 1 Indicates that the data on the bus Is to bit written into a memory or an 110 device. iNA is active tor T2, T3, and Tw of any write eye'e.1t 'uctive LO\'I( and floats during «HOLD." It Is driven HIGH for one c'ock during Reset. and then floated. When the 80188 Is In queue status mode, Ihe ALE/QSO and WJ\IQSI pins provide information about procesaorfinstructlon queue Interaction.
QS1 QSO Oueue Operation .. 0 ·0 No queue operation 0 1 First opcode byte fetched from the queue 1 1 Subsequent byte fatched from the queue 1 0 Emotv the QUeue
ROiasw 62 0 Read Strobe Indicates that the 80188 Is performing a memory or 110 read cycle. AD Is active LOW for T:2, T3. and Tw of any raed cycle. It is guaranteed notto go LOW in T2 until after the Aodress Bus is floated. m:; Is activel.OW, and floats during "HOLD." AD is driven HIGH for one clock during Rasat. and then the output driver Is floated. A _k internal puB-up mechanism on the M line hols
0 it HIGH when the line is not driven. Ourlng RESET the pin Is sampled t~. determine whether the 80188 should provIda ALE. m. and RlI. or If the
; .. Queue-Status shoull.l be orovidad. RlI should be contI9Cted to GNO to provide Queue-Status data.
ARDY 55 I Asynchronous Ready Informs the 80188 that the addreased memory ,pace or 110 device will CO!ftl)lete a data transfer. The AROY input pin wlH accept an asynchronous input. and is active HIGH. Only the rising edge is internally synchronized by the 80188. ThIs means that the failing adge of AROY must be synchronized to the 80186 clock. If connected to Vee. no WAlT states Ira insartad. AsynChronous relldy (AROy) or synchronous ready (SROy) must be active to terminate a bus cycle.
$ROY 49 I Synchronous Ready must be synchronized externally to the 80188. The usa of . SROY provides a relaxed system-timing specification on the Ready Input. This 's accomplished by eliminating the one-half clock cycle which is required for
'. Internally resolving the signal level when using the AROY input. Thl, line I, active HIGH. If this line is connected to Vee. no WAIT states are Inserted.
, ,",
Asynchronous ready (AROy) or synchronous ready (SROy) must be active before a bus cycle is terminated. If unuaed, this line should be tied LOW.
J:OCK 48 0 ~ output indicates that OIhersystem bus masters are not to gain control of the system bus while LOCK is active LOW The COCl< signal is requested by the LOCI< prefix instruction lind Is actlvatad at the beginning of the first dMa eyele aSSOCiated with the instruction following the LOCK prefix. It ramilins active until the completion 0' the instruction following the LOCK prefix. No pre-fetches will occur while ~ is asserted. ~ is active LClV( Is driven HIGH for one clock during RESET, and then floated. If unueed. this line should be tied LOW.
31
BIJLAGE I E GEGEVENS iAPX 80186
Table 1. 80181 Pin Deacrlptlon (Continued)
Pin Symbol No. Type Name and Function
!('l.ST,S! 52-54 0 Bus cycle status ~~ are encoded to pfOIIide bus-transection information:
80186 Bus Cycle Status information
~ 51 SO Bus Cycle Initiated
0 0 0 Interrupt Acknowledge 0 0 1 Read 110 0 1 0 Write 110 0 1 .1 Halt 1 0 0 Instruction Fetch 1 0 1 Raed Data Irom Memorv 1 , 0 Write Oata to Memory 1 , 1 Pal.l8iva (no bus cycle'
The status pins float during "HOLD.·
~ may be uaad as a logical MIlO indicator, and 51 as a. OT/R indicator. The status lines are drivan HIGH for one clock during Reset, and then floated until a bus cycle begins.
HOLD (inputl . 50 I HOLD Indicates thaI another bus muter is requesting the locaj bus. Tha HLOA {output} 51 O· HOLO Input Is active HIGH. HOLD may be asynChronous with rnpeetto the
80188 clock. The 80188 will issue a HI.DA (HiGH) In response to a HOLO r~uest at the end of T .. or T,. Simultaneous with the Issuance of HLOA. the 80 88 will tloat the local bus and cootrol tines. After HOLO Is detected as being l.OW, the 60186 will lower HLDA. When the 80186 needs to run another bus cycle. It will again drive the local bus and control lines.
OCI 34 0, Upper Memory ChIp Select Is an activa LOW output when_r a memory reference Is made to the defined upper portion (lK-256K block) of memory. this line is not floated during bus H01.0. The address range activating OCI is softwere programmable.
l:CS 33 O· Lowe~ Memory Chip Select is active l.OW whenever a memory reference is · made to the defined lower portion (lK-256K) of memory. ihis Une is not
IIoated during bus HOLD. The eddresa renge activating ~ is software · programmable.
Me'aO-3 38.37.36.35 0 Mid-Range Memory Chip Select signals are active LOW when a memory feference is made to the defined mid-range portion 0' memory (8K-512K1. These lines .. not floated during bus HOLD. The address rangea activating ~ are software programmable. '
PCSO 25 0 Periphe!al Chip Select signals ()-4 are active LOW when a reference Is made to
l'CSl-4. 27,26.29,30 0 the cteflnad peripheral area (&4K byte va space). These lines are not floeted during bus HOLD. The eddrel.l8 ranges activating J5CSO-4 are softwara programmable.
J5C!!iA1 31 0 Peripheral Chip Select 5 or Latched A 1 may be programmed to pfOllide a sixth peripheral chip select. or to provide an internally latched A 1 signal. The address range activating ~ is software programmable. When programmad to provide latched A1, rather then~, this pin will retain the previously latched value of A1 during a bus HOLO. Al is active HIGH ..
~A2 32 a · Peripheral Chip Select 6 'or LatChed A2 may be programmad to provide a ., seventh peripheral chip select, or to pfOllld. an internally latched A2 signal,
The address range acllvating ~ is sottwePcprogrammable. When pro-grammed to provide latched A2. rather than 56, this pin will retain the previously latched value of A2 durine a bus HOLO. A2 Is active HIGH.
r1f/4 I . 40 0 Oata Transmit/ReceiYe controls the direction of data lIow through the external 828618287 data bus transceiver. When LOw, data is transferred to the 80186. When HIGH the 80186 places write data on the data bus.
• I5ER 39 0 Data Enable is provided as an 828618287 data bus transeeivar output enable. 'D!N is activa LDW during each memory and VO access.15ER is HIGH whenever DTIR changn state.
32
BIJLAGE II FUNCTIES REGISTERS EN VLAGGEN
H
I--AH -~ -Ai: --- ACCUMULAtOR REGISTER OPERATIONS
GROUP I----~----8>1 BL
1----*-----CM CL
AX Word Multiply, Word Divide, Word 1/0
BASE
COUNT
DATA {'S
I--DH-~-OL-- DATA AL Byte Multiply, Byte Divide, Byte 15
BIJLAGE V B STUKLIJST KOMPONENTEN JOINT SERVO COMPUTER
IC 1 iAPX 80186 Microprocessor
IC 3 74LS373 Latch
IC 4 74LS373 Latch
IC 5 74LS245 Transceiver
IC 6 74LS245 Transceiver
IC 7 74LS138 Decoder/Demultiplexer
IC 8 74LS138 Decoder/Demultiplexer
IC 9 2764 UV EPROM
IC10 2764 UV EPROM
IC11 TC5565PL RAM
IC12 TC5565PL RAM
IC13 TC5565PL RAM
IC14 TC5565PL RAM
lC15 8254 PROG. Interval Timer
IC16 8255A PROG. peripheral Interface
IC17 8255A PROG. peripheral Interface
IC18 8251A PROG. Communication Interface
IC19 8251A PROG. Communication Interface
IC20 8274 Mul ti-protocol serial controller
IC21 SN75188 Line Driver
IC22 SN75189 Line Receiver
IC26 74LS04 Buffer
38
I I I
CON. 3
1.
IE] I I
B IIRISTAL
B SN'."81
B """5'68
I ~" I ~;,oc~" ~I S11-4
.. " I a.oc\<,. NmR\~
L-l
I I 102e
U
EJ VOEDIIIIGSt VO" HA1RI)("
,e1. 8151 A
lelO 'llb4\H)
EJ 81..51 G,.. MATRIX
~.l I I I
'elO
8.1.:51 fl
8255 L
5~b5 L
55bS Hi
IlQEDIIIIG. 0
l liNt..
''''' lTb4 (I..) CON. b
il tJ
lei'}
SSb'.H1
Bl'55 H
C.1 .
COM.S
&:t
CON. '-4
BIJLAGE VI A DATASHEET 5251 a
8251 A PROGRAMMABLE COMMUNICATION INTERFACE
• Synchronous and Asynchronous Operation
• Synchronous 5-8 Bit Characters; Internal or External Character Synchronization; Automatic Sync Jnlertlon
• Asynchronous 5-8 Bit Characters; Clock Rate-1, 16 or 84 nme. Baud Rate; Break Character Generation; 1, 11h, or 2 Stop Bltl; False Start Bit Detection; Automatic Break Detect and Handling
• Synchronous Baud Rate":"'DC to 64K Baud
• Asynchronous Baud Rate-DC to 19.2K Baud
• Full-Duplex, Double-Buffered Transmitter and Receiver
• Error Detection-Parity, Overrun and Framing
• Compatible with an Extended Range of Intel Microprocessors
• 28·Pln DIP Package • All Inputs and Outputs are TTL
Compatible • Available In EXPRESS
-Standard Temperature Range -Extended Tempereture Range
The Intel" 8251A is the' enhanced version of the Industry standard, Intel 8251 Universal Synchronousl Asynchronous ReceiverlTransmitter (USART). designed for data communications with Intel's microprocessor families such as MC5-48, 80. 85. and IAPX..ae. 88. The 8251 A is used as a peripheral device and is programmed by the CPU to operate using virtually any serial data transmission technique presently in use (Including IBM "bl~nc"). The USART accepts data characters from the CPU in parallel format and then converts them Into a continuous serial data stream for transmission. Simultaneously. It can receive serial data streams and convert them Into parallel data characters for the CPU. The USARTwlll signal the CPU whenever it can accept a new character for transmission or whenever It has received a character for the CPU. The CPU can read the complete status of the USARTat any time. These include data transmission errors and control signats such as SYNDer: TxEMPTY. The chip Is fabricated using N-channel silicon gate technology.
/ INTIMA" DATA BUS
FIgure 1. Block Dlagrem
T.D
fdfDV
T.l
'fi~
R.D
iiR a
FIgure 2. PIn Conffguratlon
40
BIJLAGE VI B DATASHEET 8254
8254 . PROGRAMMABLE INTERVAL TIMER
• CompaUble with Moat Micro-- • Three Independent 16-bJt Counters proc •• aora Including 8080,,* BOSSA, IAPX 88 and IAPX 8&
• Handle. Inputs from DC to 8 MHz (10 M~ for 8254-2)
• Six Programmable Counter Mode.
• Status Read-Back Command
• Binary or BCD Counting
• Single +5V Supply
• Available In EXPRESS -Standard Temperature Range
The In,eP 8254 is a counter/timer device designed to aolve the common timing control problems in microcomputer ayatem design. It provides three independent 16-bit CQunters. each capable of handllng Qlock inputs up to 10 MHz. All model are aoftware programmable. The 8254 ia a superset of the 8253.
The 8254 useS HMOS technology and comes in a 24-pin plastic or CEROIP package. ..
• Fully Compatible with InteP Microprocessor Families
• Improved Timing Characteristics
• Diract Bit SeUReset Capability Easing Control Application Interface
• Reduces $ystem Package Count
• Improved DC Driving Capability
• Available In EXPRESS . -Standard lltmperature Range -Extended lltmperature Range
The Inte'- 8255A Is a general purPOH programmab'e 110 device dllSlgned for uM with Inte'- mICroprocessors. It hea 24110 plna wblch may be Individually programmed In 2 groups of 12 and used In 3 major mod .. of op,eratlon. In the first mode (MODE 0), Meh group of 12 I/O pins may be programmed In seta of 4 to be Input or output. In MODE 1, lhe aeeond mode. each group may be programmed to have 8 Unes of Input or output. Of the remaining 4 pins. 3 are used for hand· ahaklng and Interrupt contrOl signals. The third mode of operation (MODe 2) Is a bldlre<.;tlonal bua moae which usea 8 linea lor • bidirectional bus, and 5 lines. borrowing one from the olher group. for handShaking.
.....
• -.. .. -
-{-----
------"
Flgur. 1. 825iA Block Dllgram
.. -uo .. , ....
.. -
Fltur. 2. Pin ConfIguration
42
BIJLAGE VI 0 DATASHEET 8274
inter 8274
MULTI-PROTOCOL SERIAL CONTROLLER (M'pSC)
• Byte Synchronous: • Asynchronous, Byte Synchronous and Bit Synchronous Operation - Character Synchronization, Int~ or En
• Two Independent Full Duplex Transmitters and Raceivers
• Fully Compatible with 8048, 8051, 8085, 8088, 8086, 80188 and 80186 CPU's; 8257 and 8237 DMA Controlle ... ; and 8089 VO Proc.,
• 4 Independent DMA Channels
• Baud Rate: DC to 880K Baud
• Asynchronous: -5-8 Bit Character; Odd, Even, or No
• ~ One or Two Sync Characters - Automatic CRC Generation and
Checking (CRCo16) -IBM Bisync Compatible
• Bit Synchronous: - SDLC/HDLC Flag Generation and
Recognition - 8 Bit Address Recognition - Automatic Zero Sit Insertion and
Deletion' - Automatic CRC Generation and
Checking (CCITT-16) - CelTT X.25 Compatible
• Available In EXPRESS -Sttmdard Temperature Range
The Intel- 8274 MultI-Protocol Series Controller (MPSC) is designed to interface High Speed CommunicatiOnt lines using Asynchronous, IBM Bisync, and SOlC/HOLC protocol to Intel microcomputer systems. It can tit interfaced with Intel's MCS-48, -85, -51; iAPX-B6, -88, -186 and -188 families, the 8237 OMA Controller, or tIle!108i VO Processor in polled, interrupt driven, or OMA driven modes of operation. T'
The MPSC is a 40 pin device fabricated using Intel's High Performance HMOS Technology.
• 200 ns (2764-2) Maximum Acces. nme ••• HMOS·-E Technology
• Compatible with Hlgh·Speed 8mHz IAPX 188 •• .zero WAIT State
• Two Line Control
• Pin Compatible to 27128 EPROM
• Intellgent Programmlng'IV Algorithm
• Industry Standard Pinout ••• JEDEC Approved
• Low Active Current. •. 100mA Max.
• TTL Compatible
The Intel 2784 Is a 5V only, 65,538-b1t ultl'\1Vlolet erasable and electrically programmable read·only memory (EPROM). The standafd 2784 access time 18 25(1 ns with speed selection available at 200 ns. The access time i8 compatible with highperformance mlcl'04'fOCeseors such as Intel's 8 mHz IAPX 186. In these systems. the 2764 allows Ihe mlcroproceseor to opI(8te without the addition of WAIT states. The 2764 is also compatible with the 12 MHz 8051 family.
An Important 2764 feature Is the separate output control, Output Enabie ~ from the Chip Enable control~. The ~ control eliminates bua contention In microprocessor systems. Intel's Application Note AP·n describes Ihe mICroprocessor system implementation of the ~ and C'E controls on Intel's EPROMs. AP·72 Is available from Intel's Ulerature Department.
The 2764 has a standby mode which reduces power consumption without Increasing access time. The maximum active cummt Is 100 mA, while the maximum standby current la only 40 mAo The standby mode 1$ seleoted by applying a m· high signal to the Cllnput. .
:!:1ln1o Vee tolerance I. aYIIIIe" aa An alternative to the standard :!::S% Vee tolerance for the 2164. Thts can allow the system designer more I-ay wtth regard to his powe, supply requirements end other system parameters.
The 2764 Is f.brlcated with HMOS'·! technology, Intel', high-speed Hoehennel MOS Silicon Gate TI!Chnolo9Y-
TOSHIBA MOS MEMORY PRODUCTS 8,192 WORD X 8 BIT CMOS ST ATle RAM
SILICON GATE CMOS
OESCRI PTION The TC5565P/F is 65,536 bit static random access
rMmory organized as 8.192 word~ hy 8 bits Ilsing CMOS lechnology, and operates trom a single 5V
·,upply. Advanced circuit techniqu"lS provides both
IlIgh speed and low pow!'!r teatur!!s with a maximum
operating current 01 5mA/MHl and maximlJm acCp.ss lime of 1201'15/1501'1$, When CEl is il logical low or CE t is a Inqieal high.
lhe device is placed in low power standby mode in
which standby current is 2stA typically, The TC5565P IF has three control inputs. Two chip enables ter I ,
CE2) allow for dRvice selection and datI! retention oontrol and an outPut enable inout fOE) provides
FEAnJRES
• low power Dissipation 27.5mW/MHz (Max.) Operating
• Standby Current l00jlA (Max.!: TC5565PL-12. PU5, FL-12, FL 15
lmA(Max.): TC5565P·12, P·15, F·12. F·15 • 5V Single Pow!!r Supply • POWllr Down fRalm.,s: CE7, CE t • Fully SliHir' OP'!ration • Data Retention Supply Vultaqe: 2.0 - 55V
I'tN CONNlCTlON (TOP Viewl
PtNNAMES
"0" , 11<;0':
'" , , ."" ,.
"' " n " -, .. -, " n 'u A. " '" " " A,. " '" .. .. ". .. .. '" 0, " .. n • 0, " .. 0,
" .. n,
Add, .. , I n!>ul'
Aea<l,writ" Cont,olln"u!
Data Input/Ou IPut
-p~;;;; (+5vi Ground
No Cc>"n<"I .. ,"
TC!5565P- I 2/P- I 5 - TC5!565PL- I 2/PL- I 5
TCS565F- I 2/F- IS TCSS65FL- I 2/FL- 15
fast memory access. Thus the TC5565P/F is suitable for use in vanous microprocessor application systems whpfe high speed. low power and battery back up
are r"quireti, The TC5565P/F also features pin compatibility with
the 64K 1,,( EPROM (TMM2764DI. RAM and
EPROM ilre then interchangeable in the <;ame socket.
resultina in fle~ibility in the definition of the quantity of RAM v"rsus Ei>ROM in microprocessor application sYstems,
The TC5565P/F is offered in a dual·in·line 28 pin standard plastic package.
• Access Tim/! ,.-.~: ,.-~:.:.- -~-- ---------rI'-t"-"-'"-"-~-R-.,':Ii"'lfl-1-.:_d~-1 ! '-----_ \;;~:;~',~'r 'J ::_;~:~::',:'.". i~dti;f<~ AC'=;~Ti~_~t""'~i~~=t';5~_n?::1 iCl: I "'cr,,,",, T,rne (MAX.) 120 ns t 150 ns -icE, Access Time fMAX)'--"I - 120 "S -;15On," 1.00!DO' F.n;ohle r;;;"'i~.AxT-~ ---~oon, I --10;:';:' I
• Dir&tly TTL Compatible: All InplJts and Output, • Standard 28 Pin DIP • Ptn Comp",ihle with 2764 type EPROM
• DemultJplexlng capability • Multiple Input enable for
easy expansion • Ideal for memory chip
select decoding • Direct replacement for
Inte' 3205
DESCRIPTION
1'l1tt '138 decoder accepts three binary weighted inputs (Ao, A" At) and when enabied, provides eight mutu31ly el(cluslve . • cllve lOW outputs (i5-h The device lea· tures three Enabl. Inputs: two acthfe lOW (! .. !t) and one active HIGH (EJ ). Every OIIlpul will be HIGH unless E. and e; are lOW end l!.) Is Hlati. Thill multiple enabl. function allows easy parallel e~panslon of 1M device to a 1-01·32 (5 lines to 32 lines) decoder wllh lust four 'l38s and OM in· mter.
TYPE TYPICAl. PROPAGATION I TYPICAL suPPt. Y CU .... ENT
INPUT AND OUTPUT LOADING ANO FAN·OUT TABLE· . I 54/741 54/741.S PINS DESCRIPTION
All '"puts lSul lLSul
All I Outputs 105ul lOLSul
NOTE
The device can be used a. an e;qht oulput demultiplexer by using one 01 the active LOW Enable Inputs as Ihe Oala Input and the remaining Enable Inputs as strobes. Enable Inpute not used must be perma· nently lied 10 Ihefr appropriate active MIGH or active LOW state.
TIlt '1.5245 if an octal transceiver featur· "'9 non-inverting 3·State bus compatible oulputs In bolh send and receive dirac· 1I0Il5, The outpuls are all capable of Sink· "'9,4rnA and sourcing up to 15mA, produ<:inQ very good capacitive drive charac· ,,,is tiCS. The device leatures a Chip En· lbIe (CE) Input lor easy clIScadlng and a Send/Receive ISlFI) Inpul for direction con· lrol. All Datil Inputs have hysteresis buill 4 ,11<) minimIze ac noise effec!s. J:liiii~==
FUNCTION TABLE
INPUTS INPUTSIOUTPUTS
CI $IA A. L L A.S t H INPUT H X
lit .. ;flGH yoltlOW ~ t • tOW vonaG_ ,..,.1 , • \)Qtt't CI"
(ll
!<. WlGH ImotKJane. "off< ,tat.
PIN CONFIGURATION
8. INPUTS S,.A • (Z)
INPUT AND OUTPUT LOADING AND FAN·OUT TABLE
PINS DESCRIPTION So4I74LS
All Inputs 1lSuI
All Outputs 30LSui
NOT! ... 5<&I7A{.S ,mit load (lSvn II 2o.A l'H and - O"mA Ifl
LOGIC SYMBOL LOGIC SYMBOL (IEEEnEC)
4·315
47
BIJLAGE VI I DATASHEET 74LS373
lOGIC PRODUCTS
LATCHES/FLIP-FLOPS
• 8·blt transparent latch -'373
• 8-blt positive, edgetriggered register - '374
• )OState output bufters • Common 3-State Output
Enable • Independent register and
3-State buffer operation
DESCRIPTION The '373 Is an octal Iransparent lalch COIIPled to eIght loStale output buflllfS. The two seellonll 01 the device are eon· Irolled Independently by Latch Enable (E) ~ Output Enabte (Oll) control oates.
rlltdat. on the 0 inpuls arelranslerred to lilt latch outputs wilen Ihe Lalch Enable lEI inpul Is HIGH. Th.latch remains transplIfenl to the data inputs while E Is HIGH, ~ stores the dala present ont Htup time before Ihe HIGH-Io-LOW enable tranfilIOn. The enable gate has about 400mV of hysleresis built In to help minimize problem;! thai signal and ground noi.se ctn eause on the latchino operation.
Tilt 3-Slate outpul buffers are deSloned 10 ~rive heavily loaded 3-Slete buses. MOS memQrles, or MOS microprocessors. The tefl •• LOW Output Enable (6!) controls Iff eight loStale bullers independent of ""Ialch oplII'aUon. When i5r is LOW, the 'llched or I ransparent dala appears It Ihe oulputS. When ot' II HIGH. the oulputs
PIN CONFIGURATION
'373
Y..,
'374
O. ..
54174LS373, 54/74LS374, S373. S374
'373 Octal Transparent latch With 3-State Outputs '374 Octal 0 Flip-Flop With 3-State Outputs
TYPE TY~CALPROPAGAnON TYPICAL SUPPt.., CURRENT
DELAY (rota., 74L5373 19n1 24mA
745373 10ns 100mA
74L5374 191'1s 27mA
745374 8ns 116mA
ORDERING CODE
PACKAGES COMMERCIAL RANGES MILITARY RANGES
Vee ~ 5Y • 5'1.: T.. " O"C to + 1\I°C Io\::c - 5Y + 11I'Yt: T. ~ -Sl'e 10 • 125-0
Plastic OIP N74LS373N • N74S373N
. N74LS374N • N74S374N
Plastic SO N74l53730 • N7453730 N74LS3740 • N74S3740
are in the HIGH impedance "0"" slate. whicl'l ,,"eens they wilt neither drive nor load Ihe bus.
The '37411 an lI·bit, edoe-triggered regisler coupled to e.ghl 3·Stale output butlars. The two seetions 01 the device are controlled independentty by the Clock (CP) and Output Enable (~l conlrol gate1!l
LOGIC SYMBOL
'313
, • • • lIec whit-Q" ....... '*
'314
• • , • " " 0' ..
, , . • •• 0' o. o •
"C( _filA" 0-0 ... " ,.
The register is lully edge triggered. The state of each 0 .nput, ona setup time before the lOW-In-HIGH clock transition, is translerred to the correspOndlno flip· flOp's Q outpul. The clock buffer has about 400mV 01 hysleresls built in to help minimize problems that sIonal and ground noise can caua. on Ihe clOcking opera· tlon.
LOGIC SYMBOL (IEEElIEC)
'373 '37.
48
4
BIJLAGE VI J DATASHEET SN75188
SYSTEMS INTERFACE CIRCUIT
TYPE 5176111 QUADRUPLE UNE DRIVER
• Mwts Specifications of EIA RS.Z32C
• Deti,,*, to be Intlrdlanguble witft Motorola
JORN _1..IN-UNt! P"CKAG_
lTOI'Vl1WI
MC1~L ~---------------------------, • Cummt·Limltllld Output ••• 10 mA Typlc.al
• P_·Off Output Impedanoa ... 300 !1 Min
• SI4tw Rnt Control by Load Capacitor
• Flexible Supply Vol. Range
• Input Compatible with Molt TTL end OTl Circuits
detcrlption
The S/\/75188 i •• monolithic quadruple II.,. drivet dMigned 10 interface dllt. tetmirull equipment with dati con"MTIuf"lic.tio~ equipment in conformance with !he lPII'Citications Of EIA StlH'ldard RS·232C. The devi"" i. ""araeterized for operation from O·C to 7S"C.
schematic (eaeh driver' tOOT"'lfIl 0fIt1vEAS
"""'TISI {" W"'''tQIh ........ L -tow I...,.
.---14--- x'"' 1' ........ 4i"t
"'" ... --......... -f---~ OUfflJ'
m vcc_--. __ .... _~~ ______ ~ ____ .... __ ~
fO aT",.,. O"iVlM
absolute maximum FalinII' over operating frae.air temperatura range (un'lII otherwise noted)
Supply vclt""", VCC+ at (or below! 25"C Ir",,-'" '"",per.ture 1_ Nete. 1 and 21 Supplv velt""", VCC- at (or belewl 2SoC I'''''-.'r temperature (_ NOin 1 .nd 21 InpUt velt""", range OutpUt vc'" range Conti_. total dinipatio" lit (or below 1 MOe fr""-.ir temperature ( .... Not. 3) Operating f ......... temperatur. r.nge Storage I_perature rango . . . _ _ . _
Lead t_atur. 1116 inch from _ for flO oeconds: J package . Lead temperature 1116 inch from caM for 10 seconds: ~ package
NOTes: 1~ AU votr ... ",,*tu .. at. wltf\ ,..,~t to the nMWOf'k 9'ovrnf , .. ·Wto .... ,
4 C' t .... • " t.m","a'ur •• , ~,.. '4ft. uf to .• mt,t!f/~ C
15V -15V
-15 V to 7 V -15Vro15V
lW O·C to 7S"C
.,.es°C 10 l1S·C 300°C 2flO"C
49
BIJLAGE VI K DATASHEET SN75189
SYSTEMS INTERFACE CIRCUITS
TYPES SN75189. Sm5189A aUAD LINE RECeiVERS
• Input Resistance ... 3 kU to 7 kU • Built·in Input Hystllresis (Double Thresholds)
• Input Signal Range ... !30 V
• Fully Intllrchangeable with Mototola MC1489. MC1489A
• Response Control Provides: Input Threshold Shifting Input Noise Filtel'ing
• Operates From Single 5-V Supply
schematIC (each receiver)
• Satisfies Requirements of EIA RS-232-C
JaR N DUAL·iN-LINE PACKAGE ITOI' VIEWI
r----.----+--vcc lY
v RESPONSE CONTROL --------...".--.,---+--1
~~----~--+---~--GNO
SN75189 SN7S189A
lA 1 lV 2 2Y GNO CONTROL CONTROl
poIIiu .. tOlJiC: V· A
description
The SN7S189 and SN7S199 ... ate monolithic quadruple line reeei,ers deSigned to sati.ty the requirem",," of the
standard interface between data term in.' equipment and data communication equipment as defined by EIA Standard R5-232C. A separate re1POMSa contro' term,n'" is provided for each receiver. A r~stor or a reSistor and bias
yolt. can be connected between. th .. termINI and ground to 'hift the input threshold voltage 1 ..... 1'. An external caoacitot c:.an be connected from this tlrmin,l to ground to provtde Input noiw filtering.
abIolute maximum ratings at 25"C f .... air temperature (unless otherwise notedl
Supply voltage. vee (see Note 1)
InQUt voltage Output current Continuous tOlal dissipation at ,or below} 2S'e free-air temper.tur. (see Note 2) ()ptrltlng fr .. ·.ir temperature range Storage temperature r~ Lead tem"....tur. 1116 inell from case for 60 secondo: J package L_ tempera'ure 1116 inch from case for 10 seconds: ill package
.... OTES 1 \lOlt~ ..... ~ ...... "",.m '-.o«t to ~ ..... 'fWO'. ';'0","'0 t ....... , .... j