1
PULSE & DIGITAL CIRCUITS
UNIT-I
1. Explain how Low pass RC circuit will act as Integrator
2. Discuss the response of Low pass RC circuit with i) Step
Input ii) Ramp input
3. Verify that one of the levels of the voltage across
Capacitor
V2 = V (e2x1) = (V/2) tan hx
2 (e2x+1)
When a symmetrical square wave with time period of T is applied
to a low pass RC circuit. Here x = T/(4RC).
4. Prove that an RC low pass circuit behaves like an integrator
if RC>15T, where T is the time period of the input sinusoidal
signal.
5. A symmetrical periodic square waveform with peak amplitude of
V volts, and time period of T is applied to an RC integrator
circuit as an input. Find the steady state voltage across each
element in the circuit.
6. A pulse is applied to a low-pass RC circuit. Prove by direct
integration that the area under the pulse is same as the area under
the output waveform across the capacitor. Explain the result 7. A
low pass RC network is fed by an exponential input voltage. Obtain
steady state voltage across both the elements
8. Discuss the response of Low pass RC circuit for necessary
wave forms.
9. Three low pass RC circuits are in cascade and isolated from
one another by ideal buffer amplifiers. Find the expression for the
output voltage as a function of time if the input is a step
voltage.10. Derive suitable expression for output voltage of an RC
high pass circuit if an exponential input is applied as an
input.
11. Draw the RC high pass circuit and explain its working with
step voltage input.
12. Discuss the response of High pass RC circuit with i) Step
Input ii) Ramp input
13. Explain how high pass RC circuit will act as
Differentiator.
14. A symmetrical square wave of peak-to-peak amplitude V and
frequency f is applied to a high pass RC circuit. Show that the
percentage tilt is given by /
P = 1e1/2RCf X 200%.
1+e1/2RCf
15. Discuss the response of High pass RC circuit for sq
necessary wave forms Derive the expression for the percentage tilt
when the time constant of an RC high pass circuit is very large as
compared to the period of input symmetrical square waveform.
16. When a ramp signal is transmitted through a linear RC
network, the output departs from the input. Deduce the relation for
transmission error for different time constants of the circuit as
compared to the duration of the ramp signal.
17. Derive the expression for percentage tilt (P) of a square
wave output of RC high pass circuit. What is meant by linear wave
shaping?18. Obtain the response of a high pass RC circuit for
exponential input. Prove that for any periodic input waveform the
average level of the steady state output signal from the RC high
pass circuit is always Zero. Prove the above statement for
(different periodic input waveforms) Square wave input.
19. For a parallel RLC circuit an input Vi is applied. Derive
the Q factor of the circuit.
20. Draw the response of the circuit for step input critically
damped and over damped cases for a fixed value of R and C.
21. Explain the concept of ringing circuit.
22. Give quantitative analysis of compensated and uncompensated
attenuators. Give suitable examples for each case.
23. Explain the concept of attenuators.
24. A 1 kHz symmetrical square wave of 10 V is applied to an RC
circuit having 1 ms time constant. Calculate and plot the output
for the RC configuration as i) high-pass circuit ii) Low pass
circuit.
25. A 10 Hz square wave is applied to an RC high pass circuit.
Calculate and draw the output waveform voltage levels under the
following conditions: The lower 3-dB frequency is i)0.3 Hz ii)3 Hz
iii)30 Hz.
26. An ideal 1 s pulse is fed to a low pass circuit. Calculate
and plot the output waveform under the following conditions: the
upper 3-dB frequency is i) 10 MHz ii) 0.1 MHz iii) 0.01 MHz27. A 12
Hz symmetrical square wave whose peak- to-peak amplitude is 5V is
impressed upon a high pass circuit whose lower 3 dB frequency is 15
Hz. Determine the peak to peak amplitude of the output waveform.
Find the corner voltages of the output waveform. Also sketch the
input and output waveforms on the same scale. 28. A 10 Hz
symmetrical square wave whose peak to peak amplitude of 2 V is
applied to a high pass RC circuit whose lower 3-dB frequency is 5
Hz. Calculate and sketch the output waveform for the first two
cycles. What is the peak to peak output amplitude under steady
state conditions?29. In an RC low pass circuit R=2k and C=1 F A
square with half period of 5 Sec. is applied as input to this
circuit. Determine the output waveform.
UNIT-II
1.Give the circuits of different types of shunt clippers and
explain their operation with the help of their transfer
characteristics.2. For the circuit shown in figure 2b below: Sketch
the input and output waveforms.
VR = 10V, Vi = 20 Sin t Rf = 100 Rr = 10K , V = 0 and R= 1K
,
Draw the basic circuit diagram of a DC restorer circuit and
explain its operation.For the circuit shown in figure , sketch
transfer characteristics, assume ideal diodes. (figure2a)
Explain transfer characteristics of the emitter coupled clipper
and derive the necessary
equations.
Draw the basic circuit diagram of positive peak clamper circuit
and explain its operation.
Explain the operation of a clamping circuit whose output signal
has negative offset. What
modifications are needed if the output voltage of the clamper
circuit has positive offset?
Design a diode clamper circuit to restore the positive peaks of
1 kHz input signal to a voltage
level equal to 5V. Assume that the diode voltage during forward
bias condition is 0.7 V.
Draw a circuit diagram for getting a slicing the input
sinusoidal signal to 2V on either side of
the signal. Assume that the amplitude of the applied signal is
more than 2V.
Draw the transfer characteristics of double ended clipping
circuit and explain its operation
with suitable circuit diagram.
Draw the circuit diagram of slicer circuit using Zener diodes
and explain its operation with the
help of its transfer characteristic.
Draw the circuit diagram of emitter coupled clipper. Draw its
transfer characteristics indicating all intercepts, slopes and
voltage levels derive the necessary equations.Draw the basic
circuit diagram of negative peak clamper circuit and explain its
operation.
What is meant by comparator and explain diode differentiator
comparator operation with the help of ramp input signal is
applied.
Draw the basic circuit diagram of negative peak clamper circuit
and explain its operation.
Determine Vofor the network shown in fugure 2a for the given
waveform
.Assume ideal diodes.
Explain negative peak clipper with and without reference
voltage.1.The periodic ramp voltage shown is applied to a low pass
RC circuit. Find
the equations from which to determine the steady state output
waveform
(figure1a).
2.If T1=T2=RC, find the maximum and minimum value of the output
voltage
and plot this waveform.
3.An ideal 1 -Sec pulse is fed to a low pass circuit. Calculate
and plot the
output waveform under the following conditions: The upper 3-dB
frequency
is i. 10 MHz ii. .1 MHz iii. .0.1 MHz.
4. Explain RLC ringing circuit.
5.Explain double differentiator with the help of neat
sketches.
6. A limited ramp is applied to an RC differentiator. What is
the peak of the
out put wave form for i. T = RC ii. T= 0.2RC iii. T= 5RC.
7. A symmetrical square wave whose peak-to-peak amplitude is 2V
and whose
average value is zero is applied to an RC integrating circuit.
The time constant
is half the period of the square wave. Find the peak-to-peak
value of the output
amplitude.
8. Write a short note on RC low pass circuit. Draw the output if
a step input is
applied.
9. A pulse is applied to a low-pass RC circuit. Prove by direct
integration that
the area under the pulse is same as the area under the output
waveform across
the capacitor. Explain the result.
10. Write a short notes on Highpass RC circuit as a
differentiator.
11. A square wave of 5 V amplitude with an ON time of 1 msec and
an OFF time
of 3 m sec is applied to a high pass RC circuit with R = 2K and
C = 0.1 f.
Sketch the steady state output waveform showing all the
details
12. Explain the operation of RC high pass circuit when
exponential input is applied.
13. Explain the response of a high pass circuit to an
exponential input is applied.
14. Write short note on piping process.
15. A symmetrical square wave whose average value is zero has a
peak-to-peak ampli-
tude of 20 V and a period of 2 sec. This waveform is applied to
a low pass circuit
whose upper 3dB frequency is 1/2 MHz. Calculate and sketch the
steady state
output waveform. What is the peak-to-peak output amplitude.
16. Draw the different output waveforms of a RC High Pass
circuit when it is applied
with different inputs like (a) Step-voltage input, (b) pulse
input ,
(c) square wave input. Explain the same.
16. The periodic wave form shown is applied to an RC integrating
circuit whose
time constant is 10 sec. Sketch the output. (figure 1b)
17. Calculate the maximum and minimum values of output voltage
with respect
to ground.
18. A symmetrical square wave of peak to peak amplitude V and
frequency f is
applied to a high pass RC circuit. Find the percentage tilt. How
can this tilt be reduced?
19. The square wave shown in figure1 is fed to an RC coupling
network. What are the
voltage waveforms across R and across C if
(a) RC is very large, say RC = 10T (b) RC is very small, say
RC=T/10?
20. A square wave whose peak-to-peak amplitude is 2V extends 1V
with respect to
ground. The duration of the positive section is 0.1 Sec and that
of the negative
section is 0.2 Sec. If this waveform is impressed upon an RC
integrating circuit
whose time constant is 0.2 sec. What are the steady state
maximum and minimum
values of the output waveform?
21. Draw the RC high pass circuit and explain its working with
step voltage input.
UNIT-II
1 State and prove clamping circuit theorem.
2. For the circuit shown in figure 2a an input voltage Vi
linearly varies from 0
to 150V is applied. Sketch the output waveform V0 to the same
time scale.
Assume ideal diodes.
3. Draw the circuit diagram of slicer circuit using Zener diodes
and explain its
operation with the help of its transfer characteristic.
4. Draw the circuit diagram of emitter coupled clipper. Draw its
transfer charac-
teristics indicating all intercepts, slopes and voltage levels
derive the necessary
equations.
5. Give the circuits of different types of shunt clippers and
explain their operation
with the help of their transfer characteristics.
6. For the circuit shown in figure 2b below: Sketch the input
and output waveforms.
VR = 10V, Vi = 20 Sin wt Rf = 100 Rr = 10K, V = 0 and R= 1K,
7. For the circuit shown in figure-7, sketch transfer
characteristics, assume ideal diodes.
8. Draw the basic circuit diagram of a DC restorer circuit and
explain its operation.
9. What is synchronized clamping? Explain.
10. Design a diode clamper circuit to clamp the positive peaks
of the input signal
at zero level. The frequency of the input signal is 500 Hz.
11. Draw the circuit diagram of slicer circuit using Zener
diodes and explain its
operation with the help of its transfer characteristic.
13. For the circuit shown in figure 2b: If R = 1K, VR2 = 10V,
VR1 = 7 V Rf = 0 and Rr =
i. Sketch the transfer characteristic ii. If Vi = 20 sin t
sketch the input and output waveforms.
14. Give the circuits of different types of shunt clippers and
explain their operation
with the help of their transfer characteristics.
15. For the circuit shown in figure 15: Sketch the input and
output waveforms.
VR = 10V, Vi = 20 Sin t Rf = 100 Rr = 10K, V = 0 and R= 1K,
15. Design a clipping circuit with ideal components, which can
give the waveform
shown in figure 2a for a sinusoidal input.
16. Explain transfer characteristics of the emitter coupled
clipper and derive the
necessary equations.
17. Draw the basic circuit diagram of positive peak clamper
circuit and explain
its operation.
18. Draw the basic circuit diagram of a DC restorer circuit and
explain its operation.
19. For the circuit shown in figure , sketch transfer
characteristics, assume ideal
diodes. (figure2a)
20. A clamping circuit and input wave form is shown in figure 2b
calculate and
plot to scale the steady state output
21. (a) Give the circuits of series clipper circuits and explain
their operation with the
help of transfer characteristics.
22. For the circuit shown in the figure 2b : sketch the input
and output waveforms
if R = 1 K, VR = 10 V, Vi = 20 Sin t Rf = 100 Rr = V = 0
23. Design a diode clamper to restore a d.c level of +3 Volts to
an input signal
of peak to peak value of 10 Volts. Assume drop across diode is
0.6 Volts. as
shown in the figure (figure 23) above
UNIT-III1. Describe the sequence of events that lead to reverse
recovery time, storage time, and transition time in a semiconductor
diode
2. Explain in detail the junction diode switching times.
3. Give a brief note on piece-wise linear diode
characteristics.
4. What are catching diodes?
5. Describe the switching times of BJT by considering the charge
distribution across the base region. Explain this for cut off,
active and saturation regions.
6. Define rise time, storage time, fall time, and turn off time
in the case of transistor as a switch.
7. Explain the behavior of a BJT as a switch. Give
Applications.
8. Write a short note on switching times of a transistor.
9. Explain how transistor can be used as a switch in the
circuit, under what condition a transistor is said to be OFF and ON
respectively.
10. Explain the phenomenon of latching in a transistor
switch.
11. Write Short notes on: (a) Diode switching times (b)
Switching characteristics of transistors (c) FET as a switch.
12. Explain with relevant diagrams the various transistor
switching times.
13. Explain the tests that can be performed for listing of a
transistor for saturation.
14. Give the design considerations of a transistor switch.
15. A germanium transistor is operated at room temperature in
the CE configuration. The supply voltage is 6 V, the
collector-circuit resistance is 200 and the base current is 20
percent higher than the minimum value required to drive the
transistor into saturation. Assume the following transistor
parameters: Ico=-5A, IEO=-2A, hFE=100, and rbb=250 . Find VBE(Sat)
and VCE(Sat).
16. Design a common emitter transistor switch operating with two
power supplies VCC = 18 V, -VBB = -12 V. The transistor is expected
to operate at IC = 8 mA, and IB = 0.75 mA. The static current gain
is 25. Assume Si transistor, and R2 = 5R1.17. A transistor has fT =
50 MHz, hFE=40, Cbc=3PF and operates with Vcc=12 V and Rc=500 . The
transistor is operating initially in the neighborhood of the cut-in
point. What base current must be applied to drive the transistor to
saturation in 1 sec?
18. A rectangular pulse of voltage is applied to the base of a
transistor driving it from cutoff to
saturation. Discuss the changes in the output potential. Explain
the various times involved in
the switching process.
19. Design a transistor circuit that acts as switch for the
given specifications: VCC = 20 V, IC = 5 mA. It is a Si transistor
having hFEmin = 20. Assume necessary data.20. Sketch neatly the
waveforms of current & voltages for a transistor switch with
capacitance loading circuit.
21. Realize a two input TTL NAND gate truth table and explain
its operation with suitable circuit diagram.
22. With the help of neat circuit diagram and truth table,
explain the working of diode logic AND
gate, and RTL AND gate.23. With the help of neat circuit diagram
and truth table, explain the working of a three input DTL
NAND gate.
24. What do you mean by fan in and fan out? Discuss about the
DTL NAND gate circuit which
can improve Fan out of the gate.25. Explain the following:
Realization of AND, and OR gates using universal gates.26. Why
totem pole is used in DTL? Draw the circuit diagram and explain a
DTL gate with this.
27. Verify the truth table of a two input RTL-NOR gate with the
circuit diagram and explain its
operation.28. What are the basic logic gates which perform
almost all the operations in Digital communication systems.
29. Give some applications of logic gates. Define a positive and
negative logic systems.
30. Draw a pulse train representing a 11010111 in a synchronous
positive logic digital system.31. Write the following: (a) DTL NAND
gate, (b) RTL NOR gate, (c) Prove that NAND and NOR gates are
universal gates.32. Draw the circuits for AND gate using diodes for
negative logic explain the operation. UNIT-IV
1.Describe multivibrators from the viewpoints of construction,
priniciple of working,
classification based on the output states, applications and
specifications. Mention
one specific application of each.
2. A Self-biased binary uses n-p-n silicon transistors having
values of Vce(sat)=0.4v,Vbe(sat)=0.8v and zero base to emitter
voltage for cutoff. The circuit parameters are Vcc=20v, Rc=4.7k,
R1=30k, R2=15k and Re=390.
(a) Find the stable-state currents and voltages.
(b) Find the minimum value of hfe required to give the values in
part(a)
(c) As the temperature is increased, what is the maximum value
to which ICBO
can increase before the condition is reached where neither
transistor is OFF?
3. Discuss the symmetrical and Asymmetrical triggering in case
of Bistable transistor multivibrator.
4. With the help of a neat circuit diagram, explain the
operation of an emitter-coupled
monostable multi and derive an expression for the pulse width of
the output
5. What is a monostable multivibrator? with the help of a neat
circuit diagram explain
the principle of operation of a monostable multi and derive an
expression for pulse
width.
6.Design a Monostable circuit that produces a pulse width of 10
m sec. Assume
hfe=30, VCE(sat)=0.3V, VBEsat =0.7V Ic=5mA, Vcc=6V. VBB=1.5V, Q1
ON and
Q2 OFF.
7. Discuss about triggering of monostable multivibrators. Does a
monostable mul-
tivibrator need symmetrical triggering? explain.
8. Explain how to use a monostable multi as voltage to time
converter derive the
expression for T in terms of VCC & V ?
9. Explain the reason for the occurrence of overshoot at the
base of normally ON
transistor of one shot. Derive an expression for overshoot.
10. Discuss a few applications of a monostable multivibrator.
Explain how it
differs with that of a binary
11. Design a collector coupled transistor monostable
multivibrator to produce a
time delay of 100 sec. Use transistors have hFE of 250. Use 12v
sources,
VCE(sat) = 0.3v, VBE(sat) = 0.7v and VBEcutoff = 0v
12. A collector coupled monostable multi using n-p-n silicon
transistor has the
following parameters Vcc = 12v, VBB = 3v, RC = 2k, R1 = R2 = R =
20k,
hFE = 30, rbb = 200 and c = 1000pF. Calculate and plot to scale
the wave
slopes at each base and collector. Also find width of the o/p
pulse
13. Explain the operation of Astable multivibrator with a
circuit diagram with
relevant waveforms.
14. Show that the astable multivibrator works as voltage
controlled oscillator.
15. Design a collector coupled astable multivibrator to meet the
following
specifications: f=10KHZ,VCC=12V,IC (sat)=4mA and
hFE(min)=20.Assume that
VCE (sat)=0.3V and VBE (sat)=0.7V.
16. An astable multi is used as a voltage to frequency
converter. Find the ratio
of VCC/V,if the voltage to frequency converter generates
oscillations of
frequency thrice that when V=VCC.
17. Draw the circuit diagram of a Schmitt trigger circuit and
explain its operation.
Derive the Expressions for its UTP and LTP.
18.Explain how an Schmitt trigger circuit acts as a
comparator.
19. For the given circuit ,find UTP & LTP. What is this
circuit called? Data given
hfe(min)=40, VCE(sat)=0.1 V, UBE(sat)=0.7 V Vr=0.5V,
VBE(active)=0.6V.
20. Explain how a Schmitt trigger can be used as a comparator
and as a squaring
circuit.
21. What do you understand by hysterisis? What is hysterisis
voltage? Explain
how hystersis can be eliminated in a Schmitt trigger.
22. A transistor Schmitt trigger uses n-p-n silicion transistors
with hfe(min)=30
Vce(sat)=0.1v,VBE(sat)=0.7v Vcc=12v,Rc1=2k Rc2=1k, R1=20k,
R2=100k, Re=500,Rs=2k.
23. Draw the circuit diagram. Calculate all the steady-state
currents & voltages.
(b) Determine UTP & LTP. (c) Find Hystersis voltage. (d)
Sketch the output waveform if a triangular waveform as shown is
applied to the circuit.
UNIT-V
1. Bring out the necessity and importance of Time base
circuits.
2. Write important applications of time-base circuits. With
reference to time base circuits define the following terms: i.
Flyback time ii. Transmission error.
3. What is meant by triggered sweep? What are the merits and
demerits of triggered sweep circuits.
4. How are linearly varying current waveforms generated?
5. Draw a Miller time-base circuit with n-p-n transistors and
explain its operation. Compare its performance with that of UJT
relaxation oscillator.
6. What is meant by triggered sweep? What are the merits and
demerits of triggered sweep circuits.
7. Why the time base generators are called sweep circuits?
8. Draw and explain the typical waveform of a time-base
voltage.
9. Explain the principle of working of exponential sweep circuit
with neat circuit diagram and also derive the equations for slope ,
transmission and displacement error.
10. Explain the principle of working of Miller sweep circuit.
Derive the expression for sweep speed by taking Miller integrator
circuit.
11. Draw a simple single stage transistor Miller integration
circuit and explain how it behaves as a time-base circuit.
12. In the current-sweep circuit, how linearity can be corrected
through adjustment of driving waveform. Illustrate with an
example.
13. What is a Linear time base generator? Give its
Applications
14. Write the differences between the voltage and current time
base generators?
15. With a neat diagram explain the operation of a transistor TV
sweep circuit.
16. In the TV current sweep circuit L= 5mH and total current
change required to sweep the beam across the screen is 100mA. Of
the 63.5 microsec available for a horizontal sweep and retrace
combined, 7.0 micro sec is to be used for retrace. Calculate i.
required supply voltage ii. the capacitance C and iii. the maximum
voltage that appears across the transistor.
17. Define the three errors that occur in a sweep circuit and
obtain an expression for these errors for an exponential sweep
circuit.
18. If the amplifier gain is different from unity in a bootstrap
circuit, what is the effect on the sweep voltage? What is the
effect of amplifier bandwidth on the sweep output?
19. With a neat circuit, explain a method of compensation used
to improve the linearity of a bootstrap time base circuit.
20. In the boot strap circuit shown in figure5 Vcc = 25 V, VEE =
-15 V, R = 10 K ohms, RB = 150 K ohms, C = 0.05 F. The gating
waveform has a duration of 300 s. The transistor parameters are hie
= 1.1Kohms, hre = 2.5 x 104 K ohms, hfe =50 hoe = 1/40K ohms.
i. Draw the waveform of IC1 and Vo , labeling all current and
voltage levels,
ii. What is the slope error of the sweep?
iii. What is the sweep speed and the maximum value of the sweep
voltage?
iv. What is the retrace time Tr for C to discharge
completely?
v. Calculate the recovery time T1 for C1 to recharge
completely.
21. In the UJT sweep circuit, VBB = 20V, Vyy = 50V, R=5k, C=0.01
micro F. UJT has _= 0.5. Calculate i. amplitude of sweep signal ii.
Slope and displacement errors and iii. estimated recovery time.
22. In the UJT sweep circuit, VBB = 20V, Vyy = 50V, R=5k, C=0.01
micro F. UJT has = 0.5. Calculate i. amplitude of sweep signal ii.
Slope and displacement errors and iii. estimated recovery time.
23. Explain with a circuit the working of a UJT sweep circuit
and obtain the expressions for the intrinsic stand off ratio
().
24. Draw a neat circuit diagram of UJT relaxation oscillator and
explain its operation. Can it be used as time-base circuit of a
CRO? If so how and if not why?
A free-running relaxation oscillator has sweep amplitude of 100
V and a period of 1 msec synchronizing pulses are applied to the
device such that breakdown voltage is lowered by 50 V at each
pulse. The synchronizing pulse frequency is 4 kHz. What is the
amplitude and frequency of synchronized oscillator waveform?
1. Illustrate the terms synchronization and frequency division
of a sweep generator.
UNIT-VI
1. Explain how a sinusoidal oscillator can be used as a
frequency divider.
2. Write short notes on i. Phase delay and ii. Phase jitters
3. Explain the principle of synchronization and synchronization
with frequency division.
4.Explain the method of pulse synchronization of relaxation
devices, with examples.
5. Explain about synchronization of a sweep circuits with
symmetrical signals.
6. A UJT sweep operates with a valley voltage of Vv=2V and a
peak voltage Vp=12V. A sinusoidal synchronizing voltage of 2V peak
is applied between bases. The stand-off ratio is =0.5. If the
natural frequency of sweep is 1kHz, over what range of
synchronizing signal frequency will the sweep remain in 1:1
synchronization with the synchronizing signal?
7. Explain the factors which influence the stability of a
relaxation divider with
the help of a neat waveforms.
8. A UJT sweep operates with Vv = 3V, Vp=16V and =0.5. A
sinusoidal synchronizing voltage of 2V peak is applied between
bases and the natural frequency of the sweep is 1kHz, over what
range of sync signal frequency will the sweep remain in 1:1
synchronism with the sync signal?
9. What is relaxation oscillator? Name some negative resistance
devices used as
relaxation oscillators and give its applications.
10. With the help of a circuit diagram and waveforms, explain
the frequency
division by an astable multivibrator?
11. What do you mean by synchronization ?
12. What is the condition to be met for pulse
synchronization?
13. Compare sine wave synchronization with pulse
synchronization?
14.Illustrate the terms synchronization and frequency division
of a sweep generator.
15. A free-running relaxation oscillator has sweep amplitude of
100 V and a period of 1 msec synchronizing pulses are applied to
the device such that breakdown voltage is lowered by 50 V at each
pulse. The synchronizing pulse frequency is 4 kHz. What is the
amplitude and frequency of synchronized oscillator waveform?
16..Explain the principle of synchronization and synchronization
with frequency division.
17. Explain the method of pulse synchronization of relaxation
devices, with examples.
18. Illustrate the terms synchronization and frequency division
of a sweep generator.
19. A free-running relaxation oscillator has sweep amplitude of
100 V and a period
of 1 msec synchronizing pulses are applied to the device such
that breakdown
voltage is lowered by 50 V at each pulse. The synchronizing
pulse frequency is 4 kHz. What is the amplitude and frequency of
synchronized oscillator waveform?
20. Bring out the importance of synchronization and frequency
division.
21. The relaxation oscillator when running freely, generates an
output sweep amplitude of 100V and frequency 1kHz. Synchronizing
pulses are applied such that at each pulse the breakdown voltage is
lowered by 20V. Over what frequency range may the synchronizing
pulse frequency be varied if 1:1 synchronization is to result?
22. Bring out the importance of synchronization and frequency
division.
(a) How astable multivibrator can be synchronized? Illustrate
with waveforms.
(b) A symmetrical astable multivibrator using transistor
operates from 10V supply
has a period of 1msec. Triggering pulses of spacing 750 microsec
are applied
to one base through a small capacitor from a high-impedance
source. Find the
minimum triggering pulse amplitude required to achieve 1:1
synchronization.
6. (a) What do you mean by synchronization ?
(b) What is the condition to be met for pulse
synchronization?
(c) Compare sine wave synchronization with pulse
synchronization?
UNIT-VII
7. Explain the operation of bi-directional sampling gate using
diodes. Give the equiv-
alent circuit and derive the expression for gain. Derive the
expressions for minimum
control voltages required.
7. Explain the operation of bi-directional sampling gate using
diodes. Give the equiv-
alent circuit and derive the expression for gain. Derive the
expressions for minimum
control voltages required
7. (a) What is sampling gate? Explain how it differ from Logic
gates?
(b) What is pedestal? How it effects the output of a sampling
gates?
(c) What are the drawbacks of two diode sampling gate?
7. (a) Explain how the diodes in a four-diode gate are replaced
by short circuits.
(b) Calculate the control voltage for a four-diode gate.
7. (a) Illustrate with neat circuit diagram, the operation of
unidirectional sampling
gate for multiple inputs.
(b) Explain with circuit diagram the operation of a two input
sampling gate which
does not have any loading effect on control signal.
7. (a) Illustrate with neat circuit diagram, the operation of
unidirectional sampling
gate for multiple inputs.
(b) Explain with circuit diagram the operation of a two input
sampling gate which
does not have any loading effect on control signal.
7. (a) What is a sampling gate? Explain the operation of series
gate using JFET.
Sketch the input and output waveforms.
(b) Illustrate the errors encountered in series sampling and
what is the design
procedure to minimize these errors?
(a) Distinguish between logic gate and sampling gate.
(b) Why is a sampling referred as a linear gate?
(c) Illustrate the principle of operation of a linear gate using
series switch and
shunts witch. What are the disadvantages?
7. With the help of a neat diagram, explain the working of
two-diode sampling gate.
(b) Derive expressions for gain and minimum control voltages of
a bi-directional
two- diode sampling gate.
7. (a) Illustrate with neat circuit diagram, the operation of
unidirectional sampling
gate for multiple inputs.
(b) Explain with circuit diagram the operation of a two input
sampling gate which
does not have any loading effect on control signal.
7. (a) What is sampling gate? Explain how it differ from Logic
gates?
(b) What is pedestal? How it effects the output of a sampling
gates?
(c) What are the drawbacks of two diode sampling gate?
7. (a) Draw and explain an emitter coupled bi-directional
sampling gate.
(b) For the four diode gate shown in figure 7 with a divider
resistance R used .
Vs=25V, Rf=20 ohms, RL=RC=200K ohms and R= 100 ohms. Find
Vcmin,
A and Vnmin?
UNIT-VIII
1. What is meant by blocking oscillator ? Explain the principle
of operation of monostable
blocking oscillator with base timing. Sketch the current
waveforms and derive an
expression for current pulse width.of RL.
2. Explain the recovery and loading considerations in blocking
oscillator and the effect
of providing damping. Give an alternate circuit to have pulse
period independent 8. Explain the recovery and loading
considerations in blocking oscillator and the effect of providing
damping. Give an alternate circuit to have pulse period independent
of RL.
3. Consider the triggered blocking oscillator circuit shown in
figure 8 below., using
a silicon transistor with VCE (sat) = 0.3V and VBE (sat) = 0.7V
and hFE = 50.
There are twice as many turns in the base winding as in the
collector winding. The
magnetizing inductance of the collector winding 3 mH , its
leakage inductance is
50 H and its shunt capacitance is 100 pF. During the pulse,
calculate
(a) the pulse amplitude at the collector (b) the collector
current (c) the base current and (d) the pulse width.
4. Compare the diode controlled and RC controlled astable
operated blocking oscillator.
(5. What are the advantages of RC controlled oscillator?
6. List the applications of blocking oscillators.
7. What is meant by blocking oscillator? Explain the principle
of operation of monostable
blocking oscillator with base timing. Sketch the current
waveforms and derive an
expression for current pulse width.
9. Explain the operation of an RC controlled free running
blocking oscillator with
neat sketch of circuit and voltage waveforms. Derive the
expression for duty cycle.
What are the advantages of the circuit?
10. What is meant by blocking oscillator? Explain the principle
of operation of monostable
blocking oscillator with base timing. Sketch the current
waveforms and derive an
expression for current pulse width.
11. Discuss the methods of controlling output current pulse
width in blocking
oscillators.
12. Write notes on hysteresis effect in blocking
oscillators.
13. Discuss the method of improving rise time in blocking
oscillator.
14. In the circuit (figure 8) shown below, D is a germanium
diode with V