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© 2019 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
PCB Analysis Considerations for every designerMake better PCB design decisions…
Erik NijeboerOktober 2019
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Introduction
• Increasing PCB complexity• Robust board performance
– Manufacturability– Electrical Analysis– Thermal Analysis
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• Flex-Rigid
• High-density interconnect (HDI)– Microvias– Blind/Buried, staggered vias
• BGAs
• ECAD-MCAD codesign
Increasing PCB Complexity
20%80%% time spent on designing medium to high complexity PCBs*
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• Constant Impedance
• Coupling issues between adjacent “fast” signals
• Return path discontinuities
• IR-drop
• Thermal effects
Increasing PCB Complexity
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How ensure board performance ?
• Manufacturability• Electrical Analysis• Thermal Analysis
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Design for Manufacturing/Assembly
• DFx rules are important– You can design anything but can you manufacture it ?– Bare minimum that is required
• Example rules/checks– Minimum spacing for copper/masks.– Minimum copper size (sliver, islands)– Spacing board outline (components, copper)– Flex Rigid (vias, copper, parts, bending….)– Acid traps (sharp angles)– Copper balancing (warpage)– Testpoints
– Spacing (testpoint, masks)– Pad size
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Design for Manufacturing Rules
PlacementRouting
RoutingMfg Prep
PreliminaryDFM check
CompleteDFM Check
Fix Errors
TQs*(Errors)
~1 week
TQs(Errors)
Time –function of board and list of issue found
BatchDFM
Check
Fix errors
BatchDFM
Check
>3 days
DESIGN
HOUSE
MFG
PARTNER
*: TQs: Technical Queries
FinalDFM Check
<1 week
Mfg
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Design for Manufacturing Rules
RoutingMfg Prep
BatchDFM
Check
OrCAD PCB DesignTrue DFM
DFM Rules
DESIGN
HOUSE
MFG
PARTNER
PlacementRouting
FinalDFM Check
<1 week
Mfg
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How to get DFx rules
• If possible, get rules from your manufacturer• Use industry standards or guidelines• Cadence DesignTrue DFM portal
– EMS can register here
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How ensure board performance ?
• Manufacturability• Electrical Analysis• Thermal Analysis
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Existing PCB SI Related Constaints
• Spacing and trace width5 mil 5 mil15 mil
3.5 mil
5 mil
35 mil
5 mil 15 mil
Not electrical aware !!
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Existing PCB SI Related Constaints
• Spacing and trace width• Impedance
Signal layer + plane layers directly above and below
trace9048
Not electrical aware !!
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Existing PCB SI Related Constaints
• Spacing and trace width• Impedance• Differential Pair
Running skew larger than 15 mils
Thse two opposite bends compensate
each other naturally
Static or Dynamic Phase
Not electrical aware !!
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Existing PCB SI Related Constaints
• Spacing and trace width• Impedance• Differential Pair• Relative propagation delay
– In time or length
• Number of vias• Stubs• Max parallel lines
length
spacing
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Common PCB flow
Schematic Entry
Rules for physical layout
checking
ExperienceTopologySimulation
ComponentMFR
Sign Off
SI/PI Analysis
PCB Layout
SI/PI Analysis
SI Models
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Required PCB flow
Schematic Entry
Rules for physical layout
checking
ExperienceTopologySimulation
ComponentMFR
Sign Off
SI/PI Analysis
PCB Layout
SI/PI Analysis
SI Models
Faster Feedback
Eases SI/PI expert tasks
SI/PI Analysis
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In Design and Analysis
Visions
OrCAD PCB EditorAdvanced ERCsAnalysis Workflows
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Impedance Analysis Screening
• Global view of results– Graphics– Tables & Plots
• Look for outliers– Single-ended and Differential impedance
• No SI Models required
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Coupling Analysis Screening
• Electrical coupling is more accurate than geometrical methods
• Supports a victim andworst case mode
• No SI models required
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Return Path Analysis
• Return Path Visualization• Selected results will have return
current flow visualized on planes• No Models
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Return Path Analysis
• Return Path Visualization• Selected results will have return
current flow visualized on planes• No Models• DRC for return path (deviation)
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Return Path Analysis
• Return Path Visualization• Selected results will have return
current flow visualized on planes• No Models• DRC for return path (deviation)• Insert return path vias
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IR Drop Analysis
• IR Drop can cause– Chips not powered up properly– Smaller noise margin for chip to
become unreliable– Higher current density to introduce
thermal issues• IR Drop analysis allows layout
designers to catch these problems early in the design cycle
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IR Drop Analysis
• IR Drop can cause– Chips not powered up properly– Smaller noise margin for chip to
become unreliable– Higher current density to introduce
thermal issues• IR Drop analysis allows layout
designers to catch these problems early in the design cycle
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IR Drop Analysis
• IR Drop can cause– Chips not powered up properly– Smaller noise margin for chip to
become unreliable– Higher current density to introduce
thermal issues• IR Drop analysis allows layout
designers to catch these problems early in the design cycle
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IR Drop Analysis
• IR Drop can cause– Chips not powered up properly– Smaller noise margin for chip to
become unreliable– Higher current density to introduce
thermal issues• IR Drop analysis allows layout
designers to catch these problems early in the design cycle
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How ensure board performance ?
• Manufacturability• Electrical Analysis• Thermal Analysis
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Thermal effects
• Resistance of copper goes up~30% at 80oC
• Component speeds slows down• Material loss• Power loss• Reduce signal transmission
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Thermal Analysis
• IR drop Electrical/Thermal Co-simulation– Component heating (power dissipation), including heatsinks– Joule heating (PCB copper)– Airflow – Heatmap
• Heat Transfer Map from Computational Fluid Dynamics (CFD) simulation.
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Solve Thermal issues
• Thermal vias• Heatsink
– Thermal pads
• Cooling fans• Stackup
– Add powerplanes– Ceramic substrates– Metal core
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Conclusion
To ensure PCB performance use an optimized PCB flow:• Real time DFx rules• In Design Analysis for screening for SI/PI issues• Electrical and thermal co-analysis
Visit our booth 14
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