This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
UM030 PC720 User Manual r1.10
UM030 www.abaco.com page 1 of 37
PC720 User Manual
Abaco Systems
Support Portal
This document is the property of Abaco Systems and may not be copied nor communicated to a third party without the written permission of Abaco Systems
r1.2 The SW1 function was wrong and has been corrected. ON and OFF were swapped. Added the PERST# pin location and note about the inversion of this signal.
N/A N/A N/A 2014-03-26
1.3 Reworded descriptions and fixed typos throughout
N/A N/A N/A 2014-03-27
1.4 Fixed pinout of Secondary Interface connecter, Table 6. The FMC168 option (-4) is only valid for PC720 revision 1.2 and above.
N/A N/A N/A 2014-06-05
1.5 Removed change tracking and comments from the Word version of the document
N/A N/A N/A 2014-11-18
1.6 Added details for changes to support a heat sink on the sFMC720
N/A N/A N/A 2015-01-02
1.7 Fixed the ddr3 partnumber to reflect the actual partnumber used (MT41 instead of MT14)
N/A N/A N/A 2015-01-05
1.8 Added option (-5) for fmc230 on secondary side in Table 6.
N/A N/A N/A 2016-01-06
1.9 Added LED status BNO IvK JDS 2016-11-29
1.10 Added note to Appendix C about no guaranteed flash upload using iMPACT Rebranding
4.11 PCIe Interface ........................................................................................................21 4.12 LED status .............................................................................................................23
5 Environment ................................................................................................................23 5.1 Temperature ..........................................................................................................23 5.2 Cooling ...................................................................................................................23
FPGA Field Programmable Gate Array JTAG Join Test Action Group LED Light Emitting Diode
LVDS Low Voltage Differential Signaling MGT Multi-Gigabit Transceiver MSB Most Significant Bit(s) PCB Printed Circuit Board PCI Peripheral Component Interconnect
PCIe PCI Express
1.2 Related Documents • FPGA Mezzanine Card (FMC) standard ANSI/VITA 57.1-2010 • PCI Express Card Electromechanical Specification Revision 2.0 • PCI Express 225W/300W High Power Card Electromechanical Specification Revision
1.0
2 Installation
2.1 Requirements and handling instructions • The PC720 must be installed in a PCI Express 8x connector slot minimum. • The Primary FMC can support up to 3.3V on VADJ/VIO_B. • The Secondary FMC can support up to 1.8V on VADJ/VIO_B. • Prevent electrostatic discharge by observing ESD precautions when handling the
3 General Description The PC720 is a high-performance, half-size PCI Express card with advanced Digital Signal Processing (DSP) capabilities and multiple I/O options. The PC720 offers various direct on-board interface options (2x FMC sites) that are closely coupled to the Kintex-7 and 1GB of DDR3 SDRAM. It is an excellent choice for high-performance applications that require large band signals digitization or generation through the use of accelerated frequency-domain algorithms or video applications that are bandwidth hungry. The PCIe interface can support up to eight high-speed GTX signals, with four primary signals and an additional four signals if they are not required for the secondary or primary FMC interface. The primary method of communication between the FPGA FMCs is by LVDS. The primary FMC is full High Pin-count (HPC) compliant for the LVDS signals, and supports up to four high speed lanes. The secondary FMC is a Low pin-count FMC site with optional support for four high speed lanes.
4.1.1 Board Dimensions The PC720 card complies with the PCIe Electromechanical Specifications standard except for the board width which is 205 mm instead of 167 mm. In addition, the restricted component height on the secondary side will not be compliant if a secondary FMC is used. In that case, the adjacent slot on the secondary side cannot be used, as it will be occupied by the secondary FMC. Excluding the PCIe interface, the PC720 is 205mm x 106.65mm. With only an FMC mounted on the Primary side, the PC720 consumes only one slot in a system. Please refer to Appendix D Final PC720 Assembly for more details. NOTE: In some cases, the cooling fans can conflict with the adjacent slot as well. Contact sales for detailed information.
4.1.2 Front Panel Both the Primary and Secondary FMCs have front panel I/Os available on the PCI Express card. Only the secondary FMC has its I/Os on the adjacent slot.
4.2 I2C Bus Architecture The PC720 contains an I2C bus that interfaces to the FPGA, all FMCs, the on-board CPLD, and the PCIe SMBus on the PCIe connector. A NXP PCA9548A I2C mux is used to switch the clock and data lines between all the interfaces. With the I2C bus architecture, the bus master is considered the FPGA. From that point, it is possible to gain access to the PC720 CPLD, which controls the PCIe switch, the VADJ regulator that goes to the Secondary FMC, and the four most significant bits of the LA pins of the same Secondary FMC connector. The hardware selectable address lines [A2:A0] of the PCA9548A are all grounded. Therefore, the PCA9548A slave address is found in Figure 2. Table 2 shows the I2C channels connected to PCA9548A.
1 1 1 0 0 0 0 R/W
Figure 2: PCA9548A Slave address for PC720.
SC#, SD# Connected to
Control Register Bits B3 B2 B1 B0
0 Primary FMC X X X 1 1 Secondary FMC X X 1 X 2 PC720 CPLD X 1 X X 3 PCI Express 1 X X X
The PC720 supports eight GTX signals from bank 115 and 116. Four GTX signals from bank 115 connect to PCIe interface. The other four GTX signals from bank 116 connect to the PCIe interface, the Primary FMC, or the Secondary FMC. The signals from bank 116 can be changed either manually using the DIP switches (SW1 and SW2) or using PCIe_CTL signals from the CPLD. SW 1 and 2 are off by default, which means CPLD controls the switches. Please refer to Figure 10 for the switch location. The default CPLD design does not actively drive these signals, which means they are pulled high. With the default CPLD code, the SW1 and SW2 function will be as described in Table 3. Note that PC720 r1.0 does not have a SW2. The GTX signals connect to either the PCIe interface or the Secondary FMC.
Source SW1 SW2 Connect to
SEC_DP_M2C/C2M [3..0] (Bank 116)
off X PCIe
on on Secondary FMC
on off Primary FMC
Table 3: SW Configuration
4.4 Primary FMC Interface The Kintex-7 FPGA interfaces to an FPGA Mezzanine Card (FMC) via a high pin count (HPC) VITA 57.1 site. Differential routing is applied with matched delay on all pairs. The FMC site provides flexibility for adding analog and/or digital I/O via customer developed, third party, or Abaco Systems FMC boards. Abaco Systems offers a wide variety of FMC cards that can be used on the PC720.
4.5 Secondary FMC Interface The PC720 offers a secondary FMC connector which connects four MGT signals and up to 32 LVDS signals. The secondary FMC acts as a supplemental FMC and is accessible through a PC-FMC-ADAPTER (not by default included). The secondary FMC is a Low Pin Count (LPC) FMC site with limitations.
The limitations depend on the FMC specified at the time of ordering. Table 5 lists the limitations per FMC type. In addition in all configurations the following signals are not available to the FPGA:
- PRSNT_M2C_L - PG_M2C - PG_C2M
For FPGA pin mapping information, first find the adapter type in Table 5 and then refer to the applicable column in Table 6.
Table 5. Limitations on secondary FMC site per FMC type
FMC specified at time of order:
Adapter Type: Limitations:
No FMC specified PC_FMC_ADAPTER-1 CLK1_M2C_P/N not available
LA32_P/N not available
LA33_P/N not available
FMC150, FMC151 PC_FMC_ADAPTER-0 External trigger input not available
Monitoring interrupt not available
FMC30RF PC_FMC_ADAPTER-1 None
FMC112 PC_FMC_ADAPTER-1 External trigger input not available
External trigger output not available
FMC164 PC_FMC_ADAPTER-1 External trigger input not available
FMC1681 PC_FMC_ADAPTER-4 External trigger input not available
1 Customers with a PC720 r1.1 or earlier received a PC-FMC-ADAPTER-1 which does not offer
4.6 DDR3 Memory Two DDR3 memory devices interface to the Kintex-7 through its Banks 33 and 34. The memory interface is tested at 400 MHz. Selecting a faster FPGA speed grade allows higher frequencies. The DDR3 memory devices used are the Micron MT41J256M16-HA-15EIT:E.
4.7.1 Architecture The PC720 uses a 50 MHz single-ended oscillator to support the CPLD functionality. Furthermore, the FPGA receives clock signals that originate from the two FMCs and the PCIe connector. The clock signals between the Secondary FMC and the FPGA are restricted in voltage so as not to damage the FPGA pins. The voltage levels are limited to 1.8V LVCMOS or LVDS signalling levels.
Optionally, it is possible use a PCIe 2x4 auxiliary power connector. Contact sales for more information. The power rails supplied by the PCIe connector are 12V, 3.3V and 3.3Vaux.
Power Rail Current Tolerance Capacitive Load
+3.3 V 3.0 A (max) ±9% 1000 µF +12 V 5.5 A (max) ±8% 1000 µF
+3.3Vaux 375 mA (max) ±9% 150 µF Table 9: PCIe Connector Power Supply Rail
Abaco Systems recommends using the PCIe connector as a main power source.
4.9 Fans In addition to supporting the FMCs and FPGA, the PC720 can support up to three fans: one 30x30mm fan for the FPGA and DDR3 memories and two 17x17mm fans for the primary and secondary FMCs. The PC-FMC-ADAPTER card can also use fans for additional airflow.
4.10 FPGA Configuration
4.10.1 CPLD JTAG Chain The JTAG chain on the PC720 is available for configuration and debugging purposes. The PC720 CPLD is used as JTAG control logic between the PCIe connector, the JTAG connector (Molex), two FMC connectors, and FPGA. CPLD detects the signals of each connector and determines the correct JTAG chain. Xilinx Platform USB-II is required to configure the FPGA. How to program the FPGA?
- Connect a Xilinx Platform USB-II to the host computer. - Connect a Xilinx JTAG RIBBON cable between JTAG RIBBON connector on PC720
and Xilinx Platform USB-II. - Open iMPACT and initialize the JTAG chain.
4.10.2 SPI Flash The 256Mb SPI serial flash is used to store the Kintex-7 FPGA image. It is possible to program the flash directly from the JTAG chain using Xilinx tool “iMPACT”. Please refer to Appendix C FLASH programming using iMPACT for details on configuring the SPI flash using this tool. Additionally, Abaco Systems offers a reference design that allows configuration of the flash over the PCI express connector using the Abaco Systems software tools. Refer to the software getting started guide for information how to configure the flash over the PCI Express bus.
Please note that the FPGA will configure itself using master SPI mode. The ISE bitstream generation settings target a master SPI clock of 3 MHz by default. The PC720 supports a maximum master SPI clock of 16 MHz when the SPI falling edge mode is also selected. For the fastest possible power on configuration time, the bitstream compression should also be enabled. NOTE: power up configuration can take between two and eight seconds depending on your FPGA image size and the configuration clock frequency. In some cases this is not fast enough to ensure proper detection of the FPGA by the host computer. You can: - try to slow down the BIOS - restart / reset the computer after the FPGA has loaded from flash.
4.10.3 CPLD The CPLD uses its own JTAG chain, by way of the press-fit interface, in order to be programmed. The default factory program provides the CPLD with several functions: a buffer and multiplexer for the JTAG chain to the PCIe interface and FMC interfaces; control of the VADJ regulator for the Secondary FMC; control of the PCIe switch for the high-speed signals from the FPGA Secondary Connector; and an interface to the LA32_P/N and LA33_P/N signals of the Secondary FMC. Within the CPLD, an I2C core is used to control the enable pin of the VADJ regulator and adjust its values, as well as to control the PCIe switch. With this capability, the FPGA can then control these devices by way of the CPLD. The I2C is also used to read and write to the LA32 and LA33 bits of the Secondary FMC. How to program the CPLD?
- This should not be done without contacting Abaco Systems. - Connect a Xilinx Platform USB-II to the host computer. - Connect a Xilinx JTAG cable between JTAG header and Xilinx Platform USB-II. - Open iMPACT and initialize the JTAG chain.
4.11 PCIe Interface The Kintex-7 devices can support the PCIe x1, x2, and x4 Gen2 lane widths on all the devices. Furthermore, FPGA devices that are not -1 parts can support x8 Gen 2. From the FPGA, the high-speed (DP) signals will start at DP0 for the x1 up to DP3 for the x4 lanes. For the x8
capability, the high-speed signals on the Secondary connector are accessed using the PCIe switch (SW1). The signals from the PCIe switch can be changed either manually using the DIP switch or using PCIe_CTL signals from the CPLD. SW1 is off by default, which means PCIe_CTL is pulled-up high and all 8 lanes connect to the PCIe card edge connector.
NOTE 1: the PERST# signal from the card edge connector is inverted before it arrives at the FPGA. The signal therefore must be inverted before connecting it to a default PCI Express core.
4.12 LED status The LED status on the board inside the shielding are solely for Abaco Systems testing purposes, do not draw conclusions based on the status of these LEDs.
DS1 (red)
ON: Power Good Blinking: Power not Good OFF: CPLD in reset
DS2 (red)
ON: Vadj secondary side Power Good OFF: CPLD in reset
DS3 (red)
ON: power on secondary side disabled OFF: power on secondary side enabled (can be ignored for PC720 without a secondary side)
DS4 (red)
Blinking: CPLD in reset Not blinking: CPLD not in reset
DS5 (green)
ON: 12V Power Good OFF: 12V Power Not Good
DS6 (green)
ON: 12V_AUX Power Good OFF: 12V_AUX Power Not Good
DS7 (green)
ON: 3.3V Power Good OFF: 3.3V Power Not Good
DS8 (green)
ON: 3.3V_AUX Power Good OFF: 3.3V_AUX Power Not Good
5 Environment
5.1 Temperature Operating temperature
• -40°C to +85°C (Industrial) Storage temperature:
• -40°C to +120°C
5.2 Cooling
5.2.1 Convection cooling (Standard Option) Underneath all the FMCs on the secondary side of the PC720, 3-V fans are used to cool devices. Because the adapter card restricts fan height for the Primary and Secondary FMCs, the fan height is set to 3 mm. Two fan locations are present under both FMCs to allow for air flow and/or an additional fan to be placed. Each fan uses about 37 mA (.10W) to create 0.57 CFM.
A 30mm x 30mm fan is used for the FPGA. The 12-V fan uses approximately 100 mA (1.2W) to create 5.0 CFM. The fans for the FPGA and the Primary FMC are mounted to the PC720. The fan to the Secondary FMC is mounted to the PC-FMC-ADAPTER. Abaco Systems’s warranty does not cover boards on which the maximum allowed temperature has been exceeded.
5.2.2 Heat Sink cooling (Enhanced FPGA Cooling Option) For applications where the on-board FPGA requires additional cooling, a heat sink is available. To support the heat sink, the 30mm x 30mm FAN must be moved to the bottom side of the PC720. It is important to note that making this change to the PC720 assembly will cause a violation of the PCIe specifications with regard to the bottom side maximum component height. The PCIe specification allows components with a maximum height of 2.67mm, the actual height of the FAN will be approximately 7-8mm (see Appendix D Final PC720 Assembly for details). Careful examination of clearances will be required if another card must be installed in the host system next to the PC720. The heat sink option needs to be specified at the time of order.
6 Safety This module presents no hazard to the user.
7 EMC This module is designed to operate within an enclosed host system built to provide EMC shielding. Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system. This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the system.
8 Warranty
Hardware Software/Firmware
Basic Warranty (included) 1 Year from Date of Shipment 90 Days from Date of Shipment
Extended Warranty (optional)
2 Years from Date of Shipment Year from Date of Shipment
Appendix C FLASH programming using iMPACT NOTE: flash programming using iMPACT is not guaranteed to work since the CPLD sits between the FPGA and the configuration flash (refer to Figure 1). This setup does not follow the recommended configuration schemes provided by Xilinx. iMPACT loads an enhanced programming file into the FPGA that allows access to the flash, and the user will not have any control over the timing of this enhanced bit file. A fault condition might appear during the programming because the CPLD has an effect on the timing of the SPI interface to the flash device. Therefore Abaco Systems recommends to use the PC720 Board Support Package to program a .hex file into the flash.
Choose the SPI flash and select configure single FPGA Press the green arrow.
Choose 256M as the number of storage bits from the pull down menu.Press the green arrow.