Partial Scan Design with Partial Scan Design with Guaranteed Combinational ATPG Guaranteed Combinational ATPG Vishwani D. Agrawal Vishwani D. Agrawal Agere Systems, Circuits and Systems Research Agere Systems, Circuits and Systems Research Lab Lab Murray Hill, NJ 07974, USA Murray Hill, NJ 07974, USA [email protected][email protected]Yong C. Kim and Kewal K. Saluja Yong C. Kim and Kewal K. Saluja University of Wisconsin, Dept. of ECE University of Wisconsin, Dept. of ECE Madison, WI 53706, USA Madison, WI 53706, USA [email protected]. [email protected]. edu edu and and [email protected][email protected]
20
Embed
Partial Scan Design with Guaranteed Combinational ATPG Vishwani D. Agrawal Agere Systems, Circuits and Systems Research Lab Murray Hill, NJ 07974, USA.
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
Partial Scan Design with Guaranteed Partial Scan Design with Guaranteed Combinational ATPGCombinational ATPG
Vishwani D. AgrawalVishwani D. AgrawalAgere Systems, Circuits and Systems Research LabAgere Systems, Circuits and Systems Research Lab
Murray Hill, NJ 07974, USAMurray Hill, NJ 07974, USA
2. Background and previous work2. Background and previous work
3. Combinational ATPG for general acyclic circuits3. Combinational ATPG for general acyclic circuits Balanced model generationBalanced model generation Test generation – multiple-fault modelTest generation – multiple-fault model Results Results
4. Special classes of acyclic circuits4. Special classes of acyclic circuits Internally balanced structureInternally balanced structure Balanced structureBalanced structure Strongly balanced structureStrongly balanced structure Results Results
5. Conclusion5. Conclusion
Partial scan with comb. ATPG 3Aug. 21, 2001
Problem StatementProblem Statement Partial scan design has less DFT overhead, but Partial scan design has less DFT overhead, but
is less desirable than full-scan because it is less desirable than full-scan because it requires sequential ATPGrequires sequential ATPG
Problem: To devise a combinational ATPG Problem: To devise a combinational ATPG method for general acyclic circuits; cyclic method for general acyclic circuits; cyclic structures can be made acyclic by partial scanstructures can be made acyclic by partial scan
FF1
FF2 FF2
A cyclic circuit Acyclic partial scan circuit
Partial scan with comb. ATPG 4Aug. 21, 2001
Background and Previous Work Background and Previous Work Models for Acyclic Sequential CircuitsModels for Acyclic Sequential Circuits
Iterative array model (Kunzmann and Wunderlich, Iterative array model (Kunzmann and Wunderlich, JETTAJETTA, 1990): Logic duplicated as many times as , 1990): Logic duplicated as many times as sequential depth for combinational ATPG sequential depth for combinational ATPG
Duplicated logic model (Miczo, 1986): Selective logic Duplicated logic model (Miczo, 1986): Selective logic duplication still results in large combinational ATPG duplication still results in large combinational ATPG circuitcircuit
Pseudo-combinational model (Min and Rogers, Pseudo-combinational model (Min and Rogers, JETTAJETTA, 1992): Shorting of flip-flops makes some , 1992): Shorting of flip-flops makes some faults combinationally untestablefaults combinationally untestable
Balanced structure (Gupta, et al., Balanced structure (Gupta, et al., IEEETCIEEETC, 1990): A , 1990): A sequential circuit structure with provable fault sequential circuit structure with provable fault detection by combinational ATPGdetection by combinational ATPG
Partial scan with comb. ATPG 5Aug. 21, 2001
Relevant ResultsRelevant Results
Theorem (Bushnell and Agrawal, 2000): A Theorem (Bushnell and Agrawal, 2000): A test for a testable non-flip-flop fault in a test for a testable non-flip-flop fault in a cycle-free (acyclic) circuit can always be cycle-free (acyclic) circuit can always be found with at most found with at most ddseqseq+1 time-frames.+1 time-frames.
Balanced circuit (Gupta, et al., Balanced circuit (Gupta, et al., IEEETCIEEETC, , 1990): An acyclic circuit is called balanced 1990): An acyclic circuit is called balanced if all paths between any pair of nodes have if all paths between any pair of nodes have the same sequential depth. A test for any the same sequential depth. A test for any testable fault in a balanced circuit can be testable fault in a balanced circuit can be found by combinational ATPG.found by combinational ATPG.
Partial scan with comb. ATPG 6Aug. 21, 2001
Present Contribution: Comb. ATPG for Present Contribution: Comb. ATPG for General (Unbalanced) Acyclic CircuitsGeneral (Unbalanced) Acyclic Circuits
Generate a balanced model, map faults
Done
No
Generate a test vector for a target fault using combinational ATPG
Obtain a test sequence from comb. vector
Simulate circuit to drop detected faults
More faults to be detected?
Yes
Partial scan with comb. ATPG 7Aug. 21, 2001
An ExampleAn Example
FF
Unbalanced nodes
s-a-0
FF replaced by buffer
s-a-0
s-a-0
a
b
a0
b0
a-1
b-1
Balanced
model
0
X
1
1
Combinational
vector
0
1/0 1/0
11/0
Test sequence: 11, 0X
dseq = 1
Partial scan with comb. ATPG 8Aug. 21, 2001
A Single Fault Model for a Multiple FaultA Single Fault Model for a Multiple Fault((NewNew))
s-a-1
A
B
C
b
c
a
An equivalent single stuck-at fault: output of AND gate stuck-at 1Multiple stuck-at fault: lines a and b stuck-at 1 and line c stuck-at 0.
A
B
C
b
c
a
s-a-1
s-a-1
s-a-0
Partial scan with comb. ATPG 9Aug. 21, 2001
Proof of Correctness for the New ModelProof of Correctness for the New Model Circuit equivalence: Fault-free output functionsCircuit equivalence: Fault-free output functions
A = a + a A = a + a ··bb · ·!c = a!c = a
B = b + a B = b + a ··bb · ·!c = b!c = b
C = c C = c ··!(a !(a ··bb · ·!c) = c !c) = c ·· (!a (!a + !+ !bb + + c) =c c) =c ··(!a (!a + !+ !b) + c = cb) + c = cs-a-1
Circuit statisticsCircuit statisticsNumber of gates: 2,781Number of gates: 2,781Number of FFs: 179Number of FFs: 179Number of faults: 4,603Number of faults: 4,603
* * Sun Ultra Sparc work stationSun Ultra Sparc work station
Partial scan with comb. ATPG 12Aug. 21, 2001
ISCAS’89 Circuits (Acyclic with Partial Scan)ISCAS’89 Circuits (Acyclic with Partial Scan) FC: cov. (%), FC: efficiency (%), VL: vec. Length, TGT: CPU s Sun Ultra FC: cov. (%), FC: efficiency (%), VL: vec. Length, TGT: CPU s Sun Ultra
Subclasses of Acyclic CircuitsSubclasses of Acyclic Circuits
Internally balanced (IB) circuit: A circuit that becomes Internally balanced (IB) circuit: A circuit that becomes balancedbalanced by splitting of PI fanouts (Fujiwara by splitting of PI fanouts (Fujiwara et al., IEEETC, et al., IEEETC, 2000)2000)
Acyclic circuit:Acyclic circuit: A sequential circuit without feedbackA sequential circuit without feedback
Balanced (B) circuit: A circuit in which all paths between Balanced (B) circuit: A circuit in which all paths between any pair of nodes (PIs, POs, gates or FFs) have the same any pair of nodes (PIs, POs, gates or FFs) have the same sequential depth (Gupta sequential depth (Gupta et al, IEEETC, et al, IEEETC, 1990)1990)
Strongly Strongly balanced (SB) circuit: A balanced circuit which has same depth from any PIs to any reachable POs (Balakrishnan and Chakradhar, VLSI Design `96)
Combinational circuit: A sequential circuit with Combinational circuit: A sequential circuit with full-scanfull-scan
Sequential
IB SBB
Combinational
Partial scan with comb. ATPG 15Aug. 21, 2001
Number of Scan FFs for Various SubclassesNumber of Scan FFs for Various Subclasses
Circuits Total FFs Acyclic IB B SB Comb.s5378 179 30 91 96 163 179s9234 228 152 201 209 220 228
Using a balanced circuit model and combinational Using a balanced circuit model and combinational ATPG, we can generate tests for any acyclic ATPG, we can generate tests for any acyclic sequential circuit with equal or higher fault coverage sequential circuit with equal or higher fault coverage and efficiency than obtained by sequential ATPG.and efficiency than obtained by sequential ATPG.
For acyclic circuits, the new ATPG procedure For acyclic circuits, the new ATPG procedure provides comparable fault coverage and provides comparable fault coverage and efficiency with significantly lower DFT ( partial-efficiency with significantly lower DFT ( partial-scan) overhead as compared to internally scan) overhead as compared to internally balanced, balanced, strongly balanced and balanced, balanced, strongly balanced and combinational subclasses. combinational subclasses.